wwan/t7xx/t7xx_port.h

0001 /* SPDX-License-Identifier: GPL-2.0-only
0002  *
0003  * Copyright (c) 2021, MediaTek Inc.
0004  * Copyright (c) 2021-2022, Intel Corporation.
0005  *
0006  * Authors:
0007  *  Haijun Liu <haijun.liu@mediatek.com>
0008  *  Moises Veleta <moises.veleta@intel.com>
0009  *  Ricardo Martinez <ricardo.martinez@linux.intel.com>
0010  *
0011  * Contributors:
0012  *  Amir Hanania <amir.hanania@intel.com>
0013  *  Andy Shevchenko <andriy.shevchenko@linux.intel.com>
0014  *  Chandrashekar Devegowda <chandrashekar.devegowda@intel.com>
0015  *  Eliot Lee <eliot.lee@intel.com>
0016  */
0017
0018 #ifndef __T7XX_PORT_H__
0019 #define __T7XX_PORT_H__
0020
0021 #include <linux/bits.h>
0022 #include <linux/device.h>
0023 #include <linux/mutex.h>
0024 #include <linux/sched.h>
0025 #include <linux/skbuff.h>
0026 #include <linux/spinlock.h>
0027 #include <linux/types.h>
0028 #include <linux/wait.h>
0029 #include <linux/wwan.h>
0030
0031 #include "t7xx_hif_cldma.h"
0032 #include "t7xx_pci.h"
0033
0034 #define PORT_CH_ID_MASK     GENMASK(7, 0)
0035
0036 /* Channel ID and Message ID definitions.
0037  * The channel number consists of peer_id(15:12) , channel_id(11:0)
0038  * peer_id:
0039  * 0:reserved, 1: to sAP, 2: to MD
0040  */
0041 enum port_ch {
0042     /* to MD */
0043     PORT_CH_CONTROL_RX = 0x2000,
0044     PORT_CH_CONTROL_TX = 0x2001,
0045     PORT_CH_UART1_RX = 0x2006,  /* META */
0046     PORT_CH_UART1_TX = 0x2008,
0047     PORT_CH_UART2_RX = 0x200a,  /* AT */
0048     PORT_CH_UART2_TX = 0x200c,
0049     PORT_CH_MD_LOG_RX = 0x202a, /* MD logging */
0050     PORT_CH_MD_LOG_TX = 0x202b,
0051     PORT_CH_LB_IT_RX = 0x203e,  /* Loop back test */
0052     PORT_CH_LB_IT_TX = 0x203f,
0053     PORT_CH_STATUS_RX = 0x2043, /* Status events */
0054     PORT_CH_MIPC_RX = 0x20ce,   /* MIPC */
0055     PORT_CH_MIPC_TX = 0x20cf,
0056     PORT_CH_MBIM_RX = 0x20d0,
0057     PORT_CH_MBIM_TX = 0x20d1,
0058     PORT_CH_DSS0_RX = 0x20d2,
0059     PORT_CH_DSS0_TX = 0x20d3,
0060     PORT_CH_DSS1_RX = 0x20d4,
0061     PORT_CH_DSS1_TX = 0x20d5,
0062     PORT_CH_DSS2_RX = 0x20d6,
0063     PORT_CH_DSS2_TX = 0x20d7,
0064     PORT_CH_DSS3_RX = 0x20d8,
0065     PORT_CH_DSS3_TX = 0x20d9,
0066     PORT_CH_DSS4_RX = 0x20da,
0067     PORT_CH_DSS4_TX = 0x20db,
0068     PORT_CH_DSS5_RX = 0x20dc,
0069     PORT_CH_DSS5_TX = 0x20dd,
0070     PORT_CH_DSS6_RX = 0x20de,
0071     PORT_CH_DSS6_TX = 0x20df,
0072     PORT_CH_DSS7_RX = 0x20e0,
0073     PORT_CH_DSS7_TX = 0x20e1,
0074 };
0075
0076 struct t7xx_port;
0077 struct port_ops {
0078     int (*init)(struct t7xx_port *port);
0079     int (*recv_skb)(struct t7xx_port *port, struct sk_buff *skb);
0080     void (*md_state_notify)(struct t7xx_port *port, unsigned int md_state);
0081     void (*uninit)(struct t7xx_port *port);
0082     int (*enable_chl)(struct t7xx_port *port);
0083     int (*disable_chl)(struct t7xx_port *port);
0084 };
0085
0086 struct t7xx_port_conf {
0087     enum port_ch        tx_ch;
0088     enum port_ch        rx_ch;
0089     unsigned char       txq_index;
0090     unsigned char       rxq_index;
0091     unsigned char       txq_exp_index;
0092     unsigned char       rxq_exp_index;
0093     enum cldma_id       path_id;
0094     struct port_ops     *ops;
0095     char            *name;
0096     enum wwan_port_type port_type;
0097 };
0098
0099 struct t7xx_port {
0100     /* Members not initialized in definition */
0101     const struct t7xx_port_conf *port_conf;
0102     struct wwan_port        *wwan_port;
0103     struct t7xx_pci_dev     *t7xx_dev;
0104     struct device           *dev;
0105     u16             seq_nums[2];    /* TX/RX sequence numbers */
0106     atomic_t            usage_cnt;
0107     struct              list_head entry;
0108     struct              list_head queue_entry;
0109     /* TX and RX flows are asymmetric since ports are multiplexed on
0110      * queues.
0111      *
0112      * TX: data blocks are sent directly to a queue. Each port
0113      * does not maintain a TX list; instead, they only provide
0114      * a wait_queue_head for blocking writes.
0115      *
0116      * RX: Each port uses a RX list to hold packets,
0117      * allowing the modem to dispatch RX packet as quickly as possible.
0118      */
0119     struct sk_buff_head     rx_skb_list;
0120     spinlock_t          port_update_lock; /* Protects port configuration */
0121     wait_queue_head_t       rx_wq;
0122     int             rx_length_th;
0123     bool                chan_enable;
0124     struct task_struct      *thread;
0125 };
0126
0127 struct sk_buff *t7xx_port_alloc_skb(int payload);
0128 struct sk_buff *t7xx_ctrl_alloc_skb(int payload);
0129 int t7xx_port_enqueue_skb(struct t7xx_port *port, struct sk_buff *skb);
0130 int t7xx_port_send_skb(struct t7xx_port *port, struct sk_buff *skb, unsigned int pkt_header,
0131                unsigned int ex_msg);
0132 int t7xx_port_send_ctl_skb(struct t7xx_port *port, struct sk_buff *skb, unsigned int msg,
0133                unsigned int ex_msg);
0134
0135 #endif /* __T7XX_PORT_H__ */