wwan/t7xx/t7xx_pci.h

0001 /* SPDX-License-Identifier: GPL-2.0-only
0002  *
0003  * Copyright (c) 2021, MediaTek Inc.
0004  * Copyright (c) 2021-2022, Intel Corporation.
0005  *
0006  * Authors:
0007  *  Haijun Liu <haijun.liu@mediatek.com>
0008  *  Ricardo Martinez <ricardo.martinez@linux.intel.com>
0009  *  Sreehari Kancharla <sreehari.kancharla@intel.com>
0010  *
0011  * Contributors:
0012  *  Amir Hanania <amir.hanania@intel.com>
0013  *  Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com>
0014  *  Moises Veleta <moises.veleta@intel.com>
0015  */
0016
0017 #ifndef __T7XX_PCI_H__
0018 #define __T7XX_PCI_H__
0019
0020 #include <linux/completion.h>
0021 #include <linux/irqreturn.h>
0022 #include <linux/mutex.h>
0023 #include <linux/pci.h>
0024 #include <linux/spinlock.h>
0025 #include <linux/types.h>
0026
0027 #include "t7xx_reg.h"
0028
0029 /* struct t7xx_addr_base - holds base addresses
0030  * @pcie_mac_ireg_base: PCIe MAC register base
0031  * @pcie_ext_reg_base: used to calculate base addresses for CLDMA, DPMA and MHCCIF registers
0032  * @pcie_dev_reg_trsl_addr: used to calculate the register base address
0033  * @infracfg_ao_base: base address used in CLDMA reset operations
0034  * @mhccif_rc_base: host view of MHCCIF rc base addr
0035  */
0036 struct t7xx_addr_base {
0037     void __iomem        *pcie_mac_ireg_base;
0038     void __iomem        *pcie_ext_reg_base;
0039     u32         pcie_dev_reg_trsl_addr;
0040     void __iomem        *infracfg_ao_base;
0041     void __iomem        *mhccif_rc_base;
0042 };
0043
0044 typedef irqreturn_t (*t7xx_intr_callback)(int irq, void *param);
0045
0046 /* struct t7xx_pci_dev - MTK device context structure
0047  * @intr_handler: array of handler function for request_threaded_irq
0048  * @intr_thread: array of thread_fn for request_threaded_irq
0049  * @callback_param: array of cookie passed back to interrupt functions
0050  * @pdev: PCI device
0051  * @base_addr: memory base addresses of HW components
0052  * @md: modem interface
0053  * @ccmni_ctlb: context structure used to control the network data path
0054  * @rgu_pci_irq_en: RGU callback ISR registered and active
0055  * @md_pm_entities: list of pm entities
0056  * @md_pm_entity_mtx: protects md_pm_entities list
0057  * @pm_sr_ack: ack from the device when went to sleep or woke up
0058  * @md_pm_state: state for resume/suspend
0059  * @md_pm_lock: protects PCIe sleep lock
0060  * @sleep_disable_count: PCIe L1.2 lock counter
0061  * @sleep_lock_acquire: indicates that sleep has been disabled
0062  */
0063 struct t7xx_pci_dev {
0064     t7xx_intr_callback  intr_handler[EXT_INT_NUM];
0065     t7xx_intr_callback  intr_thread[EXT_INT_NUM];
0066     void            *callback_param[EXT_INT_NUM];
0067     struct pci_dev      *pdev;
0068     struct t7xx_addr_base   base_addr;
0069     struct t7xx_modem   *md;
0070     struct t7xx_ccmni_ctrl  *ccmni_ctlb;
0071     bool            rgu_pci_irq_en;
0072
0073     /* Low Power Items */
0074     struct list_head    md_pm_entities;
0075     struct mutex        md_pm_entity_mtx;   /* Protects MD PM entities list */
0076     struct completion   pm_sr_ack;
0077     atomic_t        md_pm_state;
0078     spinlock_t      md_pm_lock;     /* Protects PCI resource lock */
0079     unsigned int        sleep_disable_count;
0080     struct completion   sleep_lock_acquire;
0081 };
0082
0083 enum t7xx_pm_id {
0084     PM_ENTITY_ID_CTRL1,
0085     PM_ENTITY_ID_CTRL2,
0086     PM_ENTITY_ID_DATA,
0087     PM_ENTITY_ID_INVALID
0088 };
0089
0090 /* struct md_pm_entity - device power management entity
0091  * @entity: list of PM Entities
0092  * @suspend: callback invoked before sending D3 request to device
0093  * @suspend_late: callback invoked after getting D3 ACK from device
0094  * @resume_early: callback invoked before sending the resume request to device
0095  * @resume: callback invoked after getting resume ACK from device
0096  * @id: unique PM entity identifier
0097  * @entity_param: parameter passed to the registered callbacks
0098  *
0099  *  This structure is used to indicate PM operations required by internal
0100  *  HW modules such as CLDMA and DPMA.
0101  */
0102 struct md_pm_entity {
0103     struct list_head    entity;
0104     int (*suspend)(struct t7xx_pci_dev *t7xx_dev, void *entity_param);
0105     void (*suspend_late)(struct t7xx_pci_dev *t7xx_dev, void *entity_param);
0106     void (*resume_early)(struct t7xx_pci_dev *t7xx_dev, void *entity_param);
0107     int (*resume)(struct t7xx_pci_dev *t7xx_dev, void *entity_param);
0108     enum t7xx_pm_id     id;
0109     void            *entity_param;
0110 };
0111
0112 void t7xx_pci_disable_sleep(struct t7xx_pci_dev *t7xx_dev);
0113 void t7xx_pci_enable_sleep(struct t7xx_pci_dev *t7xx_dev);
0114 int t7xx_pci_sleep_disable_complete(struct t7xx_pci_dev *t7xx_dev);
0115 int t7xx_pci_pm_entity_register(struct t7xx_pci_dev *t7xx_dev, struct md_pm_entity *pm_entity);
0116 int t7xx_pci_pm_entity_unregister(struct t7xx_pci_dev *t7xx_dev, struct md_pm_entity *pm_entity);
0117 void t7xx_pci_pm_init_late(struct t7xx_pci_dev *t7xx_dev);
0118 void t7xx_pci_pm_exp_detected(struct t7xx_pci_dev *t7xx_dev);
0119
0120 #endif /* __T7XX_PCI_H__ */