wwan/t7xx/t7xx_mhccif.h

0001 /* SPDX-License-Identifier: GPL-2.0-only
0002  *
0003  * Copyright (c) 2021, MediaTek Inc.
0004  * Copyright (c) 2021-2022, Intel Corporation.
0005  *
0006  * Authors:
0007  *  Haijun Liu <haijun.liu@mediatek.com>
0008  *  Sreehari Kancharla <sreehari.kancharla@intel.com>
0009  *
0010  * Contributors:
0011  *  Amir Hanania <amir.hanania@intel.com>
0012  *  Ricardo Martinez <ricardo.martinez@linux.intel.com>
0013  */
0014
0015 #ifndef __T7XX_MHCCIF_H__
0016 #define __T7XX_MHCCIF_H__
0017
0018 #include <linux/types.h>
0019
0020 #include "t7xx_pci.h"
0021 #include "t7xx_reg.h"
0022
0023 #define D2H_SW_INT_MASK (D2H_INT_EXCEPTION_INIT |       \
0024              D2H_INT_EXCEPTION_INIT_DONE |      \
0025              D2H_INT_EXCEPTION_CLEARQ_DONE |    \
0026              D2H_INT_EXCEPTION_ALLQ_RESET |     \
0027              D2H_INT_PORT_ENUM |            \
0028              D2H_INT_ASYNC_MD_HK)
0029
0030 void t7xx_mhccif_mask_set(struct t7xx_pci_dev *t7xx_dev, u32 val);
0031 void t7xx_mhccif_mask_clr(struct t7xx_pci_dev *t7xx_dev, u32 val);
0032 u32 t7xx_mhccif_mask_get(struct t7xx_pci_dev *t7xx_dev);
0033 void t7xx_mhccif_init(struct t7xx_pci_dev *t7xx_dev);
0034 u32 t7xx_mhccif_read_sw_int_sts(struct t7xx_pci_dev *t7xx_dev);
0035 void t7xx_mhccif_h2d_swint_trigger(struct t7xx_pci_dev *t7xx_dev, u32 channel);
0036
0037 #endif /*__T7XX_MHCCIF_H__ */