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0001 /* SPDX-License-Identifier: GPL-2.0-only
0002  *
0003  * Copyright (c) 2021, MediaTek Inc.
0004  * Copyright (c) 2021-2022, Intel Corporation.
0005  *
0006  * Authors:
0007  *  Amir Hanania <amir.hanania@intel.com>
0008  *  Haijun Liu <haijun.liu@mediatek.com>
0009  *  Moises Veleta <moises.veleta@intel.com>
0010  *  Ricardo Martinez <ricardo.martinez@linux.intel.com>
0011  *
0012  * Contributors:
0013  *  Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com>
0014  *  Eliot Lee <eliot.lee@intel.com>
0015  *  Sreehari Kancharla <sreehari.kancharla@intel.com>
0016  */
0017 
0018 #ifndef __T7XX_DPMAIF_H__
0019 #define __T7XX_DPMAIF_H__
0020 
0021 #include <linux/bits.h>
0022 #include <linux/types.h>
0023 
0024 #define DPMAIF_DL_PIT_SEQ_VALUE     251
0025 #define DPMAIF_UL_DRB_SIZE_WORD     4
0026 
0027 #define DPMAIF_MAX_CHECK_COUNT      1000000
0028 #define DPMAIF_CHECK_TIMEOUT_US     10000
0029 #define DPMAIF_CHECK_INIT_TIMEOUT_US    100000
0030 #define DPMAIF_CHECK_DELAY_US       10
0031 
0032 #define DPMAIF_RXQ_NUM          2
0033 #define DPMAIF_TXQ_NUM          5
0034 
0035 struct dpmaif_isr_en_mask {
0036     unsigned int            ap_ul_l2intr_en_msk;
0037     unsigned int            ap_dl_l2intr_en_msk;
0038     unsigned int            ap_udl_ip_busy_en_msk;
0039     unsigned int            ap_dl_l2intr_err_en_msk;
0040 };
0041 
0042 struct dpmaif_ul {
0043     bool                que_started;
0044     unsigned char           reserved[3];
0045     dma_addr_t          drb_base;
0046     unsigned int            drb_size_cnt;
0047 };
0048 
0049 struct dpmaif_dl {
0050     bool                que_started;
0051     unsigned char           reserved[3];
0052     dma_addr_t          pit_base;
0053     unsigned int            pit_size_cnt;
0054     dma_addr_t          bat_base;
0055     unsigned int            bat_size_cnt;
0056     dma_addr_t          frg_base;
0057     unsigned int            frg_size_cnt;
0058     unsigned int            pit_seq;
0059 };
0060 
0061 struct dpmaif_hw_info {
0062     struct device           *dev;
0063     void __iomem            *pcie_base;
0064     struct dpmaif_dl        dl_que[DPMAIF_RXQ_NUM];
0065     struct dpmaif_ul        ul_que[DPMAIF_TXQ_NUM];
0066     struct dpmaif_isr_en_mask   isr_en_mask;
0067 };
0068 
0069 /* DPMAIF HW Initialization parameter structure */
0070 struct dpmaif_hw_params {
0071     /* UL part */
0072     dma_addr_t          drb_base_addr[DPMAIF_TXQ_NUM];
0073     unsigned int            drb_size_cnt[DPMAIF_TXQ_NUM];
0074     /* DL part */
0075     dma_addr_t          pkt_bat_base_addr[DPMAIF_RXQ_NUM];
0076     unsigned int            pkt_bat_size_cnt[DPMAIF_RXQ_NUM];
0077     dma_addr_t          frg_bat_base_addr[DPMAIF_RXQ_NUM];
0078     unsigned int            frg_bat_size_cnt[DPMAIF_RXQ_NUM];
0079     dma_addr_t          pit_base_addr[DPMAIF_RXQ_NUM];
0080     unsigned int            pit_size_cnt[DPMAIF_RXQ_NUM];
0081 };
0082 
0083 enum dpmaif_hw_intr_type {
0084     DPF_INTR_INVALID_MIN,
0085     DPF_INTR_UL_DONE,
0086     DPF_INTR_UL_DRB_EMPTY,
0087     DPF_INTR_UL_MD_NOTREADY,
0088     DPF_INTR_UL_MD_PWR_NOTREADY,
0089     DPF_INTR_UL_LEN_ERR,
0090     DPF_INTR_DL_DONE,
0091     DPF_INTR_DL_SKB_LEN_ERR,
0092     DPF_INTR_DL_BATCNT_LEN_ERR,
0093     DPF_INTR_DL_PITCNT_LEN_ERR,
0094     DPF_INTR_DL_PKT_EMPTY_SET,
0095     DPF_INTR_DL_FRG_EMPTY_SET,
0096     DPF_INTR_DL_MTU_ERR,
0097     DPF_INTR_DL_FRGCNT_LEN_ERR,
0098     DPF_INTR_DL_Q0_PITCNT_LEN_ERR,
0099     DPF_INTR_DL_Q1_PITCNT_LEN_ERR,
0100     DPF_INTR_DL_HPC_ENT_TYPE_ERR,
0101     DPF_INTR_DL_Q0_DONE,
0102     DPF_INTR_DL_Q1_DONE,
0103     DPF_INTR_INVALID_MAX
0104 };
0105 
0106 #define DPF_RX_QNO0         0
0107 #define DPF_RX_QNO1         1
0108 #define DPF_RX_QNO_DFT          DPF_RX_QNO0
0109 
0110 struct dpmaif_hw_intr_st_para {
0111     unsigned int intr_cnt;
0112     enum dpmaif_hw_intr_type intr_types[DPF_INTR_INVALID_MAX - 1];
0113     unsigned int intr_queues[DPF_INTR_INVALID_MAX - 1];
0114 };
0115 
0116 #define DPMAIF_HW_BAT_REMAIN        64
0117 #define DPMAIF_HW_BAT_PKTBUF        (128 * 28)
0118 #define DPMAIF_HW_FRG_PKTBUF        128
0119 #define DPMAIF_HW_BAT_RSVLEN        64
0120 #define DPMAIF_HW_PKT_BIDCNT        1
0121 #define DPMAIF_HW_MTU_SIZE      (3 * 1024 + 8)
0122 #define DPMAIF_HW_CHK_BAT_NUM       62
0123 #define DPMAIF_HW_CHK_FRG_NUM       3
0124 #define DPMAIF_HW_CHK_PIT_NUM       (2 * DPMAIF_HW_CHK_BAT_NUM)
0125 
0126 #define DP_UL_INT_DONE_OFFSET       0
0127 #define DP_UL_INT_QDONE_MSK     GENMASK(4, 0)
0128 #define DP_UL_INT_EMPTY_MSK     GENMASK(9, 5)
0129 #define DP_UL_INT_MD_NOTREADY_MSK   GENMASK(14, 10)
0130 #define DP_UL_INT_MD_PWR_NOTREADY_MSK   GENMASK(19, 15)
0131 #define DP_UL_INT_ERR_MSK       GENMASK(24, 20)
0132 
0133 #define DP_DL_INT_QDONE_MSK     BIT(0)
0134 #define DP_DL_INT_SKB_LEN_ERR       BIT(1)
0135 #define DP_DL_INT_BATCNT_LEN_ERR    BIT(2)
0136 #define DP_DL_INT_PITCNT_LEN_ERR    BIT(3)
0137 #define DP_DL_INT_PKT_EMPTY_MSK     BIT(4)
0138 #define DP_DL_INT_FRG_EMPTY_MSK     BIT(5)
0139 #define DP_DL_INT_MTU_ERR_MSK       BIT(6)
0140 #define DP_DL_INT_FRG_LEN_ERR_MSK   BIT(7)
0141 #define DP_DL_INT_Q0_PITCNT_LEN_ERR BIT(8)
0142 #define DP_DL_INT_Q1_PITCNT_LEN_ERR BIT(9)
0143 #define DP_DL_INT_HPC_ENT_TYPE_ERR  BIT(10)
0144 #define DP_DL_INT_Q0_DONE       BIT(13)
0145 #define DP_DL_INT_Q1_DONE       BIT(14)
0146 
0147 #define DP_DL_Q0_STATUS_MASK        (DP_DL_INT_Q0_PITCNT_LEN_ERR | DP_DL_INT_Q0_DONE)
0148 #define DP_DL_Q1_STATUS_MASK        (DP_DL_INT_Q1_PITCNT_LEN_ERR | DP_DL_INT_Q1_DONE)
0149 
0150 int t7xx_dpmaif_hw_init(struct dpmaif_hw_info *hw_info, struct dpmaif_hw_params *init_param);
0151 int t7xx_dpmaif_hw_stop_all_txq(struct dpmaif_hw_info *hw_info);
0152 int t7xx_dpmaif_hw_stop_all_rxq(struct dpmaif_hw_info *hw_info);
0153 void t7xx_dpmaif_start_hw(struct dpmaif_hw_info *hw_info);
0154 int t7xx_dpmaif_hw_get_intr_cnt(struct dpmaif_hw_info *hw_info,
0155                 struct dpmaif_hw_intr_st_para *para, int qno);
0156 void t7xx_dpmaif_unmask_ulq_intr(struct dpmaif_hw_info *hw_info, unsigned int q_num);
0157 void t7xx_dpmaif_ul_update_hw_drb_cnt(struct dpmaif_hw_info *hw_info, unsigned int q_num,
0158                       unsigned int drb_entry_cnt);
0159 int t7xx_dpmaif_dl_snd_hw_bat_cnt(struct dpmaif_hw_info *hw_info, unsigned int bat_entry_cnt);
0160 int t7xx_dpmaif_dl_snd_hw_frg_cnt(struct dpmaif_hw_info *hw_info, unsigned int frg_entry_cnt);
0161 int t7xx_dpmaif_dlq_add_pit_remain_cnt(struct dpmaif_hw_info *hw_info, unsigned int dlq_pit_idx,
0162                        unsigned int pit_remain_cnt);
0163 void t7xx_dpmaif_dlq_unmask_pitcnt_len_err_intr(struct dpmaif_hw_info *hw_info,
0164                         unsigned int qno);
0165 void t7xx_dpmaif_dlq_unmask_rx_done(struct dpmaif_hw_info *hw_info, unsigned int qno);
0166 bool t7xx_dpmaif_ul_clr_done(struct dpmaif_hw_info *hw_info, unsigned int qno);
0167 void t7xx_dpmaif_ul_clr_all_intr(struct dpmaif_hw_info *hw_info);
0168 void t7xx_dpmaif_dl_clr_all_intr(struct dpmaif_hw_info *hw_info);
0169 void t7xx_dpmaif_clr_ip_busy_sts(struct dpmaif_hw_info *hw_info);
0170 void t7xx_dpmaif_dl_unmask_batcnt_len_err_intr(struct dpmaif_hw_info *hw_info);
0171 void t7xx_dpmaif_dl_unmask_pitcnt_len_err_intr(struct dpmaif_hw_info *hw_info);
0172 unsigned int t7xx_dpmaif_ul_get_rd_idx(struct dpmaif_hw_info *hw_info, unsigned int q_num);
0173 unsigned int t7xx_dpmaif_dl_get_bat_rd_idx(struct dpmaif_hw_info *hw_info, unsigned int q_num);
0174 unsigned int t7xx_dpmaif_dl_get_bat_wr_idx(struct dpmaif_hw_info *hw_info, unsigned int q_num);
0175 unsigned int t7xx_dpmaif_dl_get_frg_rd_idx(struct dpmaif_hw_info *hw_info, unsigned int q_num);
0176 unsigned int t7xx_dpmaif_dl_dlq_pit_get_wr_idx(struct dpmaif_hw_info *hw_info,
0177                            unsigned int dlq_pit_idx);
0178 
0179 #endif /* __T7XX_DPMAIF_H__ */
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