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OSCL-LXR
 
 

     

0001 /* SPDX-License-Identifier: GPL-2.0-only
0002  *
0003  * Copyright (c) 2021, MediaTek Inc.
0004  * Copyright (c) 2021-2022, Intel Corporation.
0005  *
0006  * Authors:
0007  *  Haijun Liu <haijun.liu@mediatek.com>
0008  *  Moises Veleta <moises.veleta@intel.com>
0009  *  Ricardo Martinez <ricardo.martinez@linux.intel.com>
0010  *
0011  * Contributors:
0012  *  Amir Hanania <amir.hanania@intel.com>
0013  *  Andy Shevchenko <andriy.shevchenko@linux.intel.com>
0014  *  Sreehari Kancharla <sreehari.kancharla@intel.com>
0015  */
0016 
0017 #ifndef __T7XX_CLDMA_H__
0018 #define __T7XX_CLDMA_H__
0019 
0020 #include <linux/bits.h>
0021 #include <linux/types.h>
0022 
0023 #define CLDMA_TXQ_NUM           8
0024 #define CLDMA_RXQ_NUM           8
0025 #define CLDMA_ALL_Q         GENMASK(7, 0)
0026 
0027 /* Interrupt status bits */
0028 #define EMPTY_STATUS_BITMASK        GENMASK(15, 8)
0029 #define TXRX_STATUS_BITMASK     GENMASK(7, 0)
0030 #define EQ_STA_BIT_OFFSET       8
0031 #define L2_INT_BIT_COUNT        16
0032 #define EQ_STA_BIT(index)       (BIT((index) + EQ_STA_BIT_OFFSET) & EMPTY_STATUS_BITMASK)
0033 
0034 #define TQ_ERR_INT_BITMASK      GENMASK(23, 16)
0035 #define TQ_ACTIVE_START_ERR_INT_BITMASK GENMASK(31, 24)
0036 
0037 #define RQ_ERR_INT_BITMASK      GENMASK(23, 16)
0038 #define RQ_ACTIVE_START_ERR_INT_BITMASK GENMASK(31, 24)
0039 
0040 #define CLDMA0_AO_BASE          0x10049000
0041 #define CLDMA0_PD_BASE          0x1021d000
0042 #define CLDMA1_AO_BASE          0x1004b000
0043 #define CLDMA1_PD_BASE          0x1021f000
0044 
0045 #define CLDMA_R_AO_BASE         0x10023000
0046 #define CLDMA_R_PD_BASE         0x1023d000
0047 
0048 /* CLDMA TX */
0049 #define REG_CLDMA_UL_START_ADDRL_0  0x0004
0050 #define REG_CLDMA_UL_START_ADDRH_0  0x0008
0051 #define REG_CLDMA_UL_CURRENT_ADDRL_0    0x0044
0052 #define REG_CLDMA_UL_CURRENT_ADDRH_0    0x0048
0053 #define REG_CLDMA_UL_STATUS     0x0084
0054 #define REG_CLDMA_UL_START_CMD      0x0088
0055 #define REG_CLDMA_UL_RESUME_CMD     0x008c
0056 #define REG_CLDMA_UL_STOP_CMD       0x0090
0057 #define REG_CLDMA_UL_ERROR      0x0094
0058 #define REG_CLDMA_UL_CFG        0x0098
0059 #define UL_CFG_BIT_MODE_36      BIT(5)
0060 #define UL_CFG_BIT_MODE_40      BIT(6)
0061 #define UL_CFG_BIT_MODE_64      BIT(7)
0062 #define UL_CFG_BIT_MODE_MASK        GENMASK(7, 5)
0063 
0064 #define REG_CLDMA_UL_MEM        0x009c
0065 #define UL_MEM_CHECK_DIS        BIT(0)
0066 
0067 /* CLDMA RX */
0068 #define REG_CLDMA_DL_START_CMD      0x05bc
0069 #define REG_CLDMA_DL_RESUME_CMD     0x05c0
0070 #define REG_CLDMA_DL_STOP_CMD       0x05c4
0071 #define REG_CLDMA_DL_MEM        0x0508
0072 #define DL_MEM_CHECK_DIS        BIT(0)
0073 
0074 #define REG_CLDMA_DL_CFG        0x0404
0075 #define DL_CFG_UP_HW_LAST       BIT(2)
0076 #define DL_CFG_BIT_MODE_36      BIT(10)
0077 #define DL_CFG_BIT_MODE_40      BIT(11)
0078 #define DL_CFG_BIT_MODE_64      BIT(12)
0079 #define DL_CFG_BIT_MODE_MASK        GENMASK(12, 10)
0080 
0081 #define REG_CLDMA_DL_START_ADDRL_0  0x0478
0082 #define REG_CLDMA_DL_START_ADDRH_0  0x047c
0083 #define REG_CLDMA_DL_CURRENT_ADDRL_0    0x04b8
0084 #define REG_CLDMA_DL_CURRENT_ADDRH_0    0x04bc
0085 #define REG_CLDMA_DL_STATUS     0x04f8
0086 
0087 /* CLDMA MISC */
0088 #define REG_CLDMA_L2TISAR0      0x0810
0089 #define REG_CLDMA_L2TISAR1      0x0814
0090 #define REG_CLDMA_L2TIMR0       0x0818
0091 #define REG_CLDMA_L2TIMR1       0x081c
0092 #define REG_CLDMA_L2TIMCR0      0x0820
0093 #define REG_CLDMA_L2TIMCR1      0x0824
0094 #define REG_CLDMA_L2TIMSR0      0x0828
0095 #define REG_CLDMA_L2TIMSR1      0x082c
0096 #define REG_CLDMA_L3TISAR0      0x0830
0097 #define REG_CLDMA_L3TISAR1      0x0834
0098 #define REG_CLDMA_L2RISAR0      0x0850
0099 #define REG_CLDMA_L2RISAR1      0x0854
0100 #define REG_CLDMA_L3RISAR0      0x0870
0101 #define REG_CLDMA_L3RISAR1      0x0874
0102 #define REG_CLDMA_IP_BUSY       0x08b4
0103 #define IP_BUSY_WAKEUP          BIT(0)
0104 #define CLDMA_L2TISAR0_ALL_INT_MASK GENMASK(15, 0)
0105 #define CLDMA_L2RISAR0_ALL_INT_MASK GENMASK(15, 0)
0106 
0107 /* CLDMA MISC */
0108 #define REG_CLDMA_L2RIMR0       0x0858
0109 #define REG_CLDMA_L2RIMR1       0x085c
0110 #define REG_CLDMA_L2RIMCR0      0x0860
0111 #define REG_CLDMA_L2RIMCR1      0x0864
0112 #define REG_CLDMA_L2RIMSR0      0x0868
0113 #define REG_CLDMA_L2RIMSR1      0x086c
0114 #define REG_CLDMA_BUSY_MASK     0x0954
0115 #define BUSY_MASK_PCIE          BIT(0)
0116 #define BUSY_MASK_AP            BIT(1)
0117 #define BUSY_MASK_MD            BIT(2)
0118 
0119 #define REG_CLDMA_INT_MASK      0x0960
0120 
0121 /* CLDMA RESET */
0122 #define REG_INFRA_RST4_SET      0x0730
0123 #define RST4_CLDMA1_SW_RST_SET      BIT(20)
0124 
0125 #define REG_INFRA_RST4_CLR      0x0734
0126 #define RST4_CLDMA1_SW_RST_CLR      BIT(20)
0127 
0128 #define REG_INFRA_RST2_SET      0x0140
0129 #define RST2_PMIC_SW_RST_SET        BIT(18)
0130 
0131 #define REG_INFRA_RST2_CLR      0x0144
0132 #define RST2_PMIC_SW_RST_CLR        BIT(18)
0133 
0134 enum mtk_txrx {
0135     MTK_TX,
0136     MTK_RX,
0137 };
0138 
0139 enum t7xx_hw_mode {
0140     MODE_BIT_32,
0141     MODE_BIT_36,
0142     MODE_BIT_40,
0143     MODE_BIT_64,
0144 };
0145 
0146 struct t7xx_cldma_hw {
0147     enum t7xx_hw_mode       hw_mode;
0148     void __iomem            *ap_ao_base;
0149     void __iomem            *ap_pdn_base;
0150     u32             phy_interrupt_id;
0151 };
0152 
0153 void t7xx_cldma_hw_irq_dis_txrx(struct t7xx_cldma_hw *hw_info, unsigned int qno,
0154                 enum mtk_txrx tx_rx);
0155 void t7xx_cldma_hw_irq_dis_eq(struct t7xx_cldma_hw *hw_info, unsigned int qno,
0156                   enum mtk_txrx tx_rx);
0157 void t7xx_cldma_hw_irq_en_txrx(struct t7xx_cldma_hw *hw_info, unsigned int qno,
0158                    enum mtk_txrx tx_rx);
0159 void t7xx_cldma_hw_irq_en_eq(struct t7xx_cldma_hw *hw_info, unsigned int qno, enum mtk_txrx tx_rx);
0160 unsigned int t7xx_cldma_hw_queue_status(struct t7xx_cldma_hw *hw_info, unsigned int qno,
0161                     enum mtk_txrx tx_rx);
0162 void t7xx_cldma_hw_init(struct t7xx_cldma_hw *hw_info);
0163 void t7xx_cldma_hw_resume_queue(struct t7xx_cldma_hw *hw_info, unsigned int qno,
0164                 enum mtk_txrx tx_rx);
0165 void t7xx_cldma_hw_start(struct t7xx_cldma_hw *hw_info);
0166 void t7xx_cldma_hw_start_queue(struct t7xx_cldma_hw *hw_info, unsigned int qno,
0167                    enum mtk_txrx tx_rx);
0168 void t7xx_cldma_hw_tx_done(struct t7xx_cldma_hw *hw_info, unsigned int bitmask);
0169 void t7xx_cldma_hw_rx_done(struct t7xx_cldma_hw *hw_info, unsigned int bitmask);
0170 void t7xx_cldma_hw_stop_all_qs(struct t7xx_cldma_hw *hw_info, enum mtk_txrx tx_rx);
0171 void t7xx_cldma_hw_set_start_addr(struct t7xx_cldma_hw *hw_info,
0172                   unsigned int qno, u64 address, enum mtk_txrx tx_rx);
0173 void t7xx_cldma_hw_reset(void __iomem *ao_base);
0174 void t7xx_cldma_hw_stop(struct t7xx_cldma_hw *hw_info, enum mtk_txrx tx_rx);
0175 unsigned int t7xx_cldma_hw_int_status(struct t7xx_cldma_hw *hw_info, unsigned int bitmask,
0176                       enum mtk_txrx tx_rx);
0177 void t7xx_cldma_hw_restore(struct t7xx_cldma_hw *hw_info);
0178 void t7xx_cldma_clear_ip_busy(struct t7xx_cldma_hw *hw_info);
0179 bool t7xx_cldma_tx_addr_is_set(struct t7xx_cldma_hw *hw_info, unsigned int qno);
0180 #endif
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