wwan/t7xx/t7xx_cldma.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2021, MediaTek Inc.
0004  * Copyright (c) 2021-2022, Intel Corporation.
0005  *
0006  * Authors:
0007  *  Haijun Liu <haijun.liu@mediatek.com>
0008  *  Moises Veleta <moises.veleta@intel.com>
0009  *  Ricardo Martinez <ricardo.martinez@linux.intel.com>
0010  *
0011  * Contributors:
0012  *  Amir Hanania <amir.hanania@intel.com>
0013  *  Andy Shevchenko <andriy.shevchenko@linux.intel.com>
0014  *  Eliot Lee <eliot.lee@intel.com>
0015  *  Sreehari Kancharla <sreehari.kancharla@intel.com>
0016  */
0017
0018 #include <linux/bits.h>
0019 #include <linux/delay.h>
0020 #include <linux/io.h>
0021 #include <linux/io-64-nonatomic-lo-hi.h>
0022 #include <linux/types.h>
0023
0024 #include "t7xx_cldma.h"
0025
0026 #define ADDR_SIZE   8
0027
0028 void t7xx_cldma_clear_ip_busy(struct t7xx_cldma_hw *hw_info)
0029 {
0030     u32 val;
0031
0032     val = ioread32(hw_info->ap_pdn_base + REG_CLDMA_IP_BUSY);
0033     val |= IP_BUSY_WAKEUP;
0034     iowrite32(val, hw_info->ap_pdn_base + REG_CLDMA_IP_BUSY);
0035 }
0036
0037 /**
0038  * t7xx_cldma_hw_restore() - Restore CLDMA HW registers.
0039  * @hw_info: Pointer to struct t7xx_cldma_hw.
0040  *
0041  * Restore HW after resume. Writes uplink configuration for CLDMA HW.
0042  */
0043 void t7xx_cldma_hw_restore(struct t7xx_cldma_hw *hw_info)
0044 {
0045     u32 ul_cfg;
0046
0047     ul_cfg = ioread32(hw_info->ap_pdn_base + REG_CLDMA_UL_CFG);
0048     ul_cfg &= ~UL_CFG_BIT_MODE_MASK;
0049
0050     if (hw_info->hw_mode == MODE_BIT_64)
0051         ul_cfg |= UL_CFG_BIT_MODE_64;
0052     else if (hw_info->hw_mode == MODE_BIT_40)
0053         ul_cfg |= UL_CFG_BIT_MODE_40;
0054     else if (hw_info->hw_mode == MODE_BIT_36)
0055         ul_cfg |= UL_CFG_BIT_MODE_36;
0056
0057     iowrite32(ul_cfg, hw_info->ap_pdn_base + REG_CLDMA_UL_CFG);
0058     /* Disable TX and RX invalid address check */
0059     iowrite32(UL_MEM_CHECK_DIS, hw_info->ap_pdn_base + REG_CLDMA_UL_MEM);
0060     iowrite32(DL_MEM_CHECK_DIS, hw_info->ap_pdn_base + REG_CLDMA_DL_MEM);
0061 }
0062
0063 void t7xx_cldma_hw_start_queue(struct t7xx_cldma_hw *hw_info, unsigned int qno,
0064                    enum mtk_txrx tx_rx)
0065 {
0066     void __iomem *reg;
0067     u32 val;
0068
0069     reg = tx_rx == MTK_RX ? hw_info->ap_pdn_base + REG_CLDMA_DL_START_CMD :
0070                 hw_info->ap_pdn_base + REG_CLDMA_UL_START_CMD;
0071     val = qno == CLDMA_ALL_Q ? CLDMA_ALL_Q : BIT(qno);
0072     iowrite32(val, reg);
0073 }
0074
0075 void t7xx_cldma_hw_start(struct t7xx_cldma_hw *hw_info)
0076 {
0077     /* Enable the TX & RX interrupts */
0078     iowrite32(TXRX_STATUS_BITMASK, hw_info->ap_pdn_base + REG_CLDMA_L2TIMCR0);
0079     iowrite32(TXRX_STATUS_BITMASK, hw_info->ap_ao_base + REG_CLDMA_L2RIMCR0);
0080     /* Enable the empty queue interrupt */
0081     iowrite32(EMPTY_STATUS_BITMASK, hw_info->ap_pdn_base + REG_CLDMA_L2TIMCR0);
0082     iowrite32(EMPTY_STATUS_BITMASK, hw_info->ap_ao_base + REG_CLDMA_L2RIMCR0);
0083 }
0084
0085 void t7xx_cldma_hw_reset(void __iomem *ao_base)
0086 {
0087     u32 val;
0088
0089     val = ioread32(ao_base + REG_INFRA_RST2_SET);
0090     val |= RST2_PMIC_SW_RST_SET;
0091     iowrite32(val, ao_base + REG_INFRA_RST2_SET);
0092     val = ioread32(ao_base + REG_INFRA_RST4_SET);
0093     val |= RST4_CLDMA1_SW_RST_SET;
0094     iowrite32(val, ao_base + REG_INFRA_RST4_SET);
0095     udelay(1);
0096
0097     val = ioread32(ao_base + REG_INFRA_RST4_CLR);
0098     val |= RST4_CLDMA1_SW_RST_CLR;
0099     iowrite32(val, ao_base + REG_INFRA_RST4_CLR);
0100     val = ioread32(ao_base + REG_INFRA_RST2_CLR);
0101     val |= RST2_PMIC_SW_RST_CLR;
0102     iowrite32(val, ao_base + REG_INFRA_RST2_CLR);
0103 }
0104
0105 bool t7xx_cldma_tx_addr_is_set(struct t7xx_cldma_hw *hw_info, unsigned int qno)
0106 {
0107     u32 offset = REG_CLDMA_UL_START_ADDRL_0 + qno * ADDR_SIZE;
0108
0109     return ioread64(hw_info->ap_pdn_base + offset);
0110 }
0111
0112 void t7xx_cldma_hw_set_start_addr(struct t7xx_cldma_hw *hw_info, unsigned int qno, u64 address,
0113                   enum mtk_txrx tx_rx)
0114 {
0115     u32 offset = qno * ADDR_SIZE;
0116     void __iomem *reg;
0117
0118     reg = tx_rx == MTK_RX ? hw_info->ap_ao_base + REG_CLDMA_DL_START_ADDRL_0 :
0119                 hw_info->ap_pdn_base + REG_CLDMA_UL_START_ADDRL_0;
0120     iowrite64(address, reg + offset);
0121 }
0122
0123 void t7xx_cldma_hw_resume_queue(struct t7xx_cldma_hw *hw_info, unsigned int qno,
0124                 enum mtk_txrx tx_rx)
0125 {
0126     void __iomem *base = hw_info->ap_pdn_base;
0127
0128     if (tx_rx == MTK_RX)
0129         iowrite32(BIT(qno), base + REG_CLDMA_DL_RESUME_CMD);
0130     else
0131         iowrite32(BIT(qno), base + REG_CLDMA_UL_RESUME_CMD);
0132 }
0133
0134 unsigned int t7xx_cldma_hw_queue_status(struct t7xx_cldma_hw *hw_info, unsigned int qno,
0135                     enum mtk_txrx tx_rx)
0136 {
0137     void __iomem *reg;
0138     u32 mask, val;
0139
0140     mask = qno == CLDMA_ALL_Q ? CLDMA_ALL_Q : BIT(qno);
0141     reg = tx_rx == MTK_RX ? hw_info->ap_ao_base + REG_CLDMA_DL_STATUS :
0142                 hw_info->ap_pdn_base + REG_CLDMA_UL_STATUS;
0143     val = ioread32(reg);
0144
0145     return val & mask;
0146 }
0147
0148 void t7xx_cldma_hw_tx_done(struct t7xx_cldma_hw *hw_info, unsigned int bitmask)
0149 {
0150     unsigned int ch_id;
0151
0152     ch_id = ioread32(hw_info->ap_pdn_base + REG_CLDMA_L2TISAR0);
0153     ch_id &= bitmask;
0154     /* Clear the ch IDs in the TX interrupt status register */
0155     iowrite32(ch_id, hw_info->ap_pdn_base + REG_CLDMA_L2TISAR0);
0156     ioread32(hw_info->ap_pdn_base + REG_CLDMA_L2TISAR0);
0157 }
0158
0159 void t7xx_cldma_hw_rx_done(struct t7xx_cldma_hw *hw_info, unsigned int bitmask)
0160 {
0161     unsigned int ch_id;
0162
0163     ch_id = ioread32(hw_info->ap_pdn_base + REG_CLDMA_L2RISAR0);
0164     ch_id &= bitmask;
0165     /* Clear the ch IDs in the RX interrupt status register */
0166     iowrite32(ch_id, hw_info->ap_pdn_base + REG_CLDMA_L2RISAR0);
0167     ioread32(hw_info->ap_pdn_base + REG_CLDMA_L2RISAR0);
0168 }
0169
0170 unsigned int t7xx_cldma_hw_int_status(struct t7xx_cldma_hw *hw_info, unsigned int bitmask,
0171                       enum mtk_txrx tx_rx)
0172 {
0173     void __iomem *reg;
0174     u32 val;
0175
0176     reg = tx_rx == MTK_RX ? hw_info->ap_pdn_base + REG_CLDMA_L2RISAR0 :
0177                 hw_info->ap_pdn_base + REG_CLDMA_L2TISAR0;
0178     val = ioread32(reg);
0179     return val & bitmask;
0180 }
0181
0182 void t7xx_cldma_hw_irq_dis_txrx(struct t7xx_cldma_hw *hw_info, unsigned int qno,
0183                 enum mtk_txrx tx_rx)
0184 {
0185     void __iomem *reg;
0186     u32 val;
0187
0188     reg = tx_rx == MTK_RX ? hw_info->ap_ao_base + REG_CLDMA_L2RIMSR0 :
0189                 hw_info->ap_pdn_base + REG_CLDMA_L2TIMSR0;
0190     val = qno == CLDMA_ALL_Q ? CLDMA_ALL_Q : BIT(qno);
0191     iowrite32(val, reg);
0192 }
0193
0194 void t7xx_cldma_hw_irq_dis_eq(struct t7xx_cldma_hw *hw_info, unsigned int qno, enum mtk_txrx tx_rx)
0195 {
0196     void __iomem *reg;
0197     u32 val;
0198
0199     reg = tx_rx == MTK_RX ? hw_info->ap_ao_base + REG_CLDMA_L2RIMSR0 :
0200                 hw_info->ap_pdn_base + REG_CLDMA_L2TIMSR0;
0201     val = qno == CLDMA_ALL_Q ? CLDMA_ALL_Q : BIT(qno);
0202     iowrite32(val << EQ_STA_BIT_OFFSET, reg);
0203 }
0204
0205 void t7xx_cldma_hw_irq_en_txrx(struct t7xx_cldma_hw *hw_info, unsigned int qno,
0206                    enum mtk_txrx tx_rx)
0207 {
0208     void __iomem *reg;
0209     u32 val;
0210
0211     reg = tx_rx == MTK_RX ? hw_info->ap_ao_base + REG_CLDMA_L2RIMCR0 :
0212                 hw_info->ap_pdn_base + REG_CLDMA_L2TIMCR0;
0213     val = qno == CLDMA_ALL_Q ? CLDMA_ALL_Q : BIT(qno);
0214     iowrite32(val, reg);
0215 }
0216
0217 void t7xx_cldma_hw_irq_en_eq(struct t7xx_cldma_hw *hw_info, unsigned int qno, enum mtk_txrx tx_rx)
0218 {
0219     void __iomem *reg;
0220     u32 val;
0221
0222     reg = tx_rx == MTK_RX ? hw_info->ap_ao_base + REG_CLDMA_L2RIMCR0 :
0223                 hw_info->ap_pdn_base + REG_CLDMA_L2TIMCR0;
0224     val = qno == CLDMA_ALL_Q ? CLDMA_ALL_Q : BIT(qno);
0225     iowrite32(val << EQ_STA_BIT_OFFSET, reg);
0226 }
0227
0228 /**
0229  * t7xx_cldma_hw_init() - Initialize CLDMA HW.
0230  * @hw_info: Pointer to struct t7xx_cldma_hw.
0231  *
0232  * Write uplink and downlink configuration to CLDMA HW.
0233  */
0234 void t7xx_cldma_hw_init(struct t7xx_cldma_hw *hw_info)
0235 {
0236     u32 ul_cfg, dl_cfg;
0237
0238     ul_cfg = ioread32(hw_info->ap_pdn_base + REG_CLDMA_UL_CFG);
0239     dl_cfg = ioread32(hw_info->ap_ao_base + REG_CLDMA_DL_CFG);
0240     /* Configure the DRAM address mode */
0241     ul_cfg &= ~UL_CFG_BIT_MODE_MASK;
0242     dl_cfg &= ~DL_CFG_BIT_MODE_MASK;
0243
0244     if (hw_info->hw_mode == MODE_BIT_64) {
0245         ul_cfg |= UL_CFG_BIT_MODE_64;
0246         dl_cfg |= DL_CFG_BIT_MODE_64;
0247     } else if (hw_info->hw_mode == MODE_BIT_40) {
0248         ul_cfg |= UL_CFG_BIT_MODE_40;
0249         dl_cfg |= DL_CFG_BIT_MODE_40;
0250     } else if (hw_info->hw_mode == MODE_BIT_36) {
0251         ul_cfg |= UL_CFG_BIT_MODE_36;
0252         dl_cfg |= DL_CFG_BIT_MODE_36;
0253     }
0254
0255     iowrite32(ul_cfg, hw_info->ap_pdn_base + REG_CLDMA_UL_CFG);
0256     dl_cfg |= DL_CFG_UP_HW_LAST;
0257     iowrite32(dl_cfg, hw_info->ap_ao_base + REG_CLDMA_DL_CFG);
0258     iowrite32(0, hw_info->ap_ao_base + REG_CLDMA_INT_MASK);
0259     iowrite32(BUSY_MASK_MD, hw_info->ap_ao_base + REG_CLDMA_BUSY_MASK);
0260     iowrite32(UL_MEM_CHECK_DIS, hw_info->ap_pdn_base + REG_CLDMA_UL_MEM);
0261     iowrite32(DL_MEM_CHECK_DIS, hw_info->ap_pdn_base + REG_CLDMA_DL_MEM);
0262 }
0263
0264 void t7xx_cldma_hw_stop_all_qs(struct t7xx_cldma_hw *hw_info, enum mtk_txrx tx_rx)
0265 {
0266     void __iomem *reg;
0267
0268     reg = tx_rx == MTK_RX ? hw_info->ap_pdn_base + REG_CLDMA_DL_STOP_CMD :
0269                 hw_info->ap_pdn_base + REG_CLDMA_UL_STOP_CMD;
0270     iowrite32(CLDMA_ALL_Q, reg);
0271 }
0272
0273 void t7xx_cldma_hw_stop(struct t7xx_cldma_hw *hw_info, enum mtk_txrx tx_rx)
0274 {
0275     void __iomem *reg;
0276
0277     reg = tx_rx == MTK_RX ? hw_info->ap_ao_base + REG_CLDMA_L2RIMSR0 :
0278                 hw_info->ap_pdn_base + REG_CLDMA_L2TIMSR0;
0279     iowrite32(TXRX_STATUS_BITMASK, reg);
0280     iowrite32(EMPTY_STATUS_BITMASK, reg);
0281 }