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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2020-21 Intel Corporation.
0004  */
0005 
0006 #include <linux/acpi.h>
0007 #include <linux/bitfield.h>
0008 #include <linux/module.h>
0009 #include <net/rtnetlink.h>
0010 
0011 #include "iosm_ipc_imem.h"
0012 #include "iosm_ipc_pcie.h"
0013 #include "iosm_ipc_protocol.h"
0014 
0015 MODULE_DESCRIPTION("IOSM Driver");
0016 MODULE_LICENSE("GPL v2");
0017 
0018 /* WWAN GUID */
0019 static guid_t wwan_acpi_guid = GUID_INIT(0xbad01b75, 0x22a8, 0x4f48, 0x87, 0x92,
0020                        0xbd, 0xde, 0x94, 0x67, 0x74, 0x7d);
0021 
0022 static void ipc_pcie_resources_release(struct iosm_pcie *ipc_pcie)
0023 {
0024     /* Free the MSI resources. */
0025     ipc_release_irq(ipc_pcie);
0026 
0027     /* Free mapped doorbell scratchpad bus memory into CPU space. */
0028     iounmap(ipc_pcie->scratchpad);
0029 
0030     /* Free mapped IPC_REGS bus memory into CPU space. */
0031     iounmap(ipc_pcie->ipc_regs);
0032 
0033     /* Releases all PCI I/O and memory resources previously reserved by a
0034      * successful call to pci_request_regions.  Call this function only
0035      * after all use of the PCI regions has ceased.
0036      */
0037     pci_release_regions(ipc_pcie->pci);
0038 }
0039 
0040 static void ipc_pcie_cleanup(struct iosm_pcie *ipc_pcie)
0041 {
0042     /* Free the shared memory resources. */
0043     ipc_imem_cleanup(ipc_pcie->imem);
0044 
0045     ipc_pcie_resources_release(ipc_pcie);
0046 
0047     /* Signal to the system that the PCI device is not in use. */
0048     pci_disable_device(ipc_pcie->pci);
0049 }
0050 
0051 static void ipc_pcie_deinit(struct iosm_pcie *ipc_pcie)
0052 {
0053     kfree(ipc_pcie->imem);
0054     kfree(ipc_pcie);
0055 }
0056 
0057 static void ipc_pcie_remove(struct pci_dev *pci)
0058 {
0059     struct iosm_pcie *ipc_pcie = pci_get_drvdata(pci);
0060 
0061     ipc_pcie_cleanup(ipc_pcie);
0062 
0063     ipc_pcie_deinit(ipc_pcie);
0064 }
0065 
0066 static int ipc_pcie_resources_request(struct iosm_pcie *ipc_pcie)
0067 {
0068     struct pci_dev *pci = ipc_pcie->pci;
0069     u32 cap = 0;
0070     u32 ret;
0071 
0072     /* Reserved PCI I/O and memory resources.
0073      * Mark all PCI regions associated with PCI device pci as
0074      * being reserved by owner IOSM_IPC.
0075      */
0076     ret = pci_request_regions(pci, "IOSM_IPC");
0077     if (ret) {
0078         dev_err(ipc_pcie->dev, "failed pci request regions");
0079         goto pci_request_region_fail;
0080     }
0081 
0082     /* Reserve the doorbell IPC REGS memory resources.
0083      * Remap the memory into CPU space. Arrange for the physical address
0084      * (BAR) to be visible from this driver.
0085      * pci_ioremap_bar() ensures that the memory is marked uncachable.
0086      */
0087     ipc_pcie->ipc_regs = pci_ioremap_bar(pci, ipc_pcie->ipc_regs_bar_nr);
0088 
0089     if (!ipc_pcie->ipc_regs) {
0090         dev_err(ipc_pcie->dev, "IPC REGS ioremap error");
0091         ret = -EBUSY;
0092         goto ipc_regs_remap_fail;
0093     }
0094 
0095     /* Reserve the MMIO scratchpad memory resources.
0096      * Remap the memory into CPU space. Arrange for the physical address
0097      * (BAR) to be visible from this driver.
0098      * pci_ioremap_bar() ensures that the memory is marked uncachable.
0099      */
0100     ipc_pcie->scratchpad =
0101         pci_ioremap_bar(pci, ipc_pcie->scratchpad_bar_nr);
0102 
0103     if (!ipc_pcie->scratchpad) {
0104         dev_err(ipc_pcie->dev, "doorbell scratchpad ioremap error");
0105         ret = -EBUSY;
0106         goto scratch_remap_fail;
0107     }
0108 
0109     /* Install the irq handler triggered by CP. */
0110     ret = ipc_acquire_irq(ipc_pcie);
0111     if (ret) {
0112         dev_err(ipc_pcie->dev, "acquiring MSI irq failed!");
0113         goto irq_acquire_fail;
0114     }
0115 
0116     /* Enable bus-mastering for the IOSM IPC device. */
0117     pci_set_master(pci);
0118 
0119     /* Enable LTR if possible
0120      * This is needed for L1.2!
0121      */
0122     pcie_capability_read_dword(ipc_pcie->pci, PCI_EXP_DEVCAP2, &cap);
0123     if (cap & PCI_EXP_DEVCAP2_LTR)
0124         pcie_capability_set_word(ipc_pcie->pci, PCI_EXP_DEVCTL2,
0125                      PCI_EXP_DEVCTL2_LTR_EN);
0126 
0127     dev_dbg(ipc_pcie->dev, "link between AP and CP is fully on");
0128 
0129     return ret;
0130 
0131 irq_acquire_fail:
0132     iounmap(ipc_pcie->scratchpad);
0133 scratch_remap_fail:
0134     iounmap(ipc_pcie->ipc_regs);
0135 ipc_regs_remap_fail:
0136     pci_release_regions(pci);
0137 pci_request_region_fail:
0138     return ret;
0139 }
0140 
0141 bool ipc_pcie_check_aspm_enabled(struct iosm_pcie *ipc_pcie,
0142                  bool parent)
0143 {
0144     struct pci_dev *pdev;
0145     u16 value = 0;
0146     u32 enabled;
0147 
0148     if (parent)
0149         pdev = ipc_pcie->pci->bus->self;
0150     else
0151         pdev = ipc_pcie->pci;
0152 
0153     pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &value);
0154     enabled = value & PCI_EXP_LNKCTL_ASPMC;
0155     dev_dbg(ipc_pcie->dev, "ASPM L1: 0x%04X 0x%03X", pdev->device, value);
0156 
0157     return (enabled == PCI_EXP_LNKCTL_ASPM_L1 ||
0158         enabled == PCI_EXP_LNKCTL_ASPMC);
0159 }
0160 
0161 bool ipc_pcie_check_data_link_active(struct iosm_pcie *ipc_pcie)
0162 {
0163     struct pci_dev *parent;
0164     u16 link_status = 0;
0165 
0166     if (!ipc_pcie->pci->bus || !ipc_pcie->pci->bus->self) {
0167         dev_err(ipc_pcie->dev, "root port not found");
0168         return false;
0169     }
0170 
0171     parent = ipc_pcie->pci->bus->self;
0172 
0173     pcie_capability_read_word(parent, PCI_EXP_LNKSTA, &link_status);
0174     dev_dbg(ipc_pcie->dev, "Link status: 0x%04X", link_status);
0175 
0176     return link_status & PCI_EXP_LNKSTA_DLLLA;
0177 }
0178 
0179 static bool ipc_pcie_check_aspm_supported(struct iosm_pcie *ipc_pcie,
0180                       bool parent)
0181 {
0182     struct pci_dev *pdev;
0183     u32 support;
0184     u32 cap = 0;
0185 
0186     if (parent)
0187         pdev = ipc_pcie->pci->bus->self;
0188     else
0189         pdev = ipc_pcie->pci;
0190     pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &cap);
0191     support = u32_get_bits(cap, PCI_EXP_LNKCAP_ASPMS);
0192     if (support < PCI_EXP_LNKCTL_ASPM_L1) {
0193         dev_dbg(ipc_pcie->dev, "ASPM L1 not supported: 0x%04X",
0194             pdev->device);
0195         return false;
0196     }
0197     return true;
0198 }
0199 
0200 void ipc_pcie_config_aspm(struct iosm_pcie *ipc_pcie)
0201 {
0202     bool parent_aspm_enabled, dev_aspm_enabled;
0203 
0204     /* check if both root port and child supports ASPM L1 */
0205     if (!ipc_pcie_check_aspm_supported(ipc_pcie, true) ||
0206         !ipc_pcie_check_aspm_supported(ipc_pcie, false))
0207         return;
0208 
0209     parent_aspm_enabled = ipc_pcie_check_aspm_enabled(ipc_pcie, true);
0210     dev_aspm_enabled = ipc_pcie_check_aspm_enabled(ipc_pcie, false);
0211 
0212     dev_dbg(ipc_pcie->dev, "ASPM parent: %s device: %s",
0213         parent_aspm_enabled ? "Enabled" : "Disabled",
0214         dev_aspm_enabled ? "Enabled" : "Disabled");
0215 }
0216 
0217 /* Initializes PCIe endpoint configuration */
0218 static void ipc_pcie_config_init(struct iosm_pcie *ipc_pcie)
0219 {
0220     /* BAR0 is used for doorbell */
0221     ipc_pcie->ipc_regs_bar_nr = IPC_DOORBELL_BAR0;
0222 
0223     /* update HW configuration */
0224     ipc_pcie->scratchpad_bar_nr = IPC_SCRATCHPAD_BAR2;
0225     ipc_pcie->doorbell_reg_offset = IPC_DOORBELL_CH_OFFSET;
0226     ipc_pcie->doorbell_write = IPC_WRITE_PTR_REG_0;
0227     ipc_pcie->doorbell_capture = IPC_CAPTURE_PTR_REG_0;
0228 }
0229 
0230 /* This will read the BIOS WWAN RTD3 settings:
0231  * D0L1.2/D3L2/Disabled
0232  */
0233 static enum ipc_pcie_sleep_state ipc_pcie_read_bios_cfg(struct device *dev)
0234 {
0235     union acpi_object *object;
0236     acpi_handle handle_acpi;
0237 
0238     handle_acpi = ACPI_HANDLE(dev);
0239     if (!handle_acpi) {
0240         pr_debug("pci device is NOT ACPI supporting device\n");
0241         goto default_ret;
0242     }
0243 
0244     object = acpi_evaluate_dsm(handle_acpi, &wwan_acpi_guid, 0, 3, NULL);
0245 
0246     if (object && object->integer.value == 3)
0247         return IPC_PCIE_D3L2;
0248 
0249 default_ret:
0250     return IPC_PCIE_D0L12;
0251 }
0252 
0253 static int ipc_pcie_probe(struct pci_dev *pci,
0254               const struct pci_device_id *pci_id)
0255 {
0256     struct iosm_pcie *ipc_pcie = kzalloc(sizeof(*ipc_pcie), GFP_KERNEL);
0257 
0258     pr_debug("Probing device 0x%X from the vendor 0x%X", pci_id->device,
0259          pci_id->vendor);
0260 
0261     if (!ipc_pcie)
0262         goto ret_fail;
0263 
0264     /* Initialize ipc dbg component for the PCIe device */
0265     ipc_pcie->dev = &pci->dev;
0266 
0267     /* Set the driver specific data. */
0268     pci_set_drvdata(pci, ipc_pcie);
0269 
0270     /* Save the address of the PCI device configuration. */
0271     ipc_pcie->pci = pci;
0272 
0273     /* Update platform configuration */
0274     ipc_pcie_config_init(ipc_pcie);
0275 
0276     /* Initialize the device before it is used. Ask low-level code
0277      * to enable I/O and memory. Wake up the device if it was suspended.
0278      */
0279     if (pci_enable_device(pci)) {
0280         dev_err(ipc_pcie->dev, "failed to enable the AP PCIe device");
0281         /* If enable of PCIe device has failed then calling
0282          * ipc_pcie_cleanup will panic the system. More over
0283          * ipc_pcie_cleanup() is required to be called after
0284          * ipc_imem_mount()
0285          */
0286         goto pci_enable_fail;
0287     }
0288 
0289     ipc_pcie_config_aspm(ipc_pcie);
0290     dev_dbg(ipc_pcie->dev, "PCIe device enabled.");
0291 
0292     /* Read WWAN RTD3 BIOS Setting
0293      */
0294     ipc_pcie->d3l2_support = ipc_pcie_read_bios_cfg(&pci->dev);
0295 
0296     ipc_pcie->suspend = 0;
0297 
0298     if (ipc_pcie_resources_request(ipc_pcie))
0299         goto resources_req_fail;
0300 
0301     /* Establish the link to the imem layer. */
0302     ipc_pcie->imem = ipc_imem_init(ipc_pcie, pci->device,
0303                        ipc_pcie->scratchpad, ipc_pcie->dev);
0304     if (!ipc_pcie->imem) {
0305         dev_err(ipc_pcie->dev, "failed to init imem");
0306         goto imem_init_fail;
0307     }
0308 
0309     return 0;
0310 
0311 imem_init_fail:
0312     ipc_pcie_resources_release(ipc_pcie);
0313 resources_req_fail:
0314     pci_disable_device(pci);
0315 pci_enable_fail:
0316     kfree(ipc_pcie);
0317 ret_fail:
0318     return -EIO;
0319 }
0320 
0321 static const struct pci_device_id iosm_ipc_ids[] = {
0322     { PCI_DEVICE(PCI_VENDOR_ID_INTEL, INTEL_CP_DEVICE_7560_ID) },
0323     { PCI_DEVICE(PCI_VENDOR_ID_INTEL, INTEL_CP_DEVICE_7360_ID) },
0324     {}
0325 };
0326 MODULE_DEVICE_TABLE(pci, iosm_ipc_ids);
0327 
0328 /* Enter sleep in s2idle case
0329  */
0330 static int __maybe_unused ipc_pcie_suspend_s2idle(struct iosm_pcie *ipc_pcie)
0331 {
0332     ipc_cp_irq_sleep_control(ipc_pcie, IPC_MEM_DEV_PM_FORCE_SLEEP);
0333 
0334     /* Complete all memory stores before setting bit */
0335     smp_mb__before_atomic();
0336 
0337     set_bit(0, &ipc_pcie->suspend);
0338 
0339     /* Complete all memory stores after setting bit */
0340     smp_mb__after_atomic();
0341 
0342     ipc_imem_pm_s2idle_sleep(ipc_pcie->imem, true);
0343 
0344     return 0;
0345 }
0346 
0347 /* Resume from sleep in s2idle case
0348  */
0349 static int __maybe_unused ipc_pcie_resume_s2idle(struct iosm_pcie *ipc_pcie)
0350 {
0351     ipc_cp_irq_sleep_control(ipc_pcie, IPC_MEM_DEV_PM_FORCE_ACTIVE);
0352 
0353     ipc_imem_pm_s2idle_sleep(ipc_pcie->imem, false);
0354 
0355     /* Complete all memory stores before clearing bit. */
0356     smp_mb__before_atomic();
0357 
0358     clear_bit(0, &ipc_pcie->suspend);
0359 
0360     /* Complete all memory stores after clearing bit. */
0361     smp_mb__after_atomic();
0362     return 0;
0363 }
0364 
0365 int __maybe_unused ipc_pcie_suspend(struct iosm_pcie *ipc_pcie)
0366 {
0367     /* The HAL shall ask the shared memory layer whether D3 is allowed. */
0368     ipc_imem_pm_suspend(ipc_pcie->imem);
0369 
0370     dev_dbg(ipc_pcie->dev, "SUSPEND done");
0371     return 0;
0372 }
0373 
0374 int __maybe_unused ipc_pcie_resume(struct iosm_pcie *ipc_pcie)
0375 {
0376     /* The HAL shall inform the shared memory layer that the device is
0377      * active.
0378      */
0379     ipc_imem_pm_resume(ipc_pcie->imem);
0380 
0381     dev_dbg(ipc_pcie->dev, "RESUME done");
0382     return 0;
0383 }
0384 
0385 static int __maybe_unused ipc_pcie_suspend_cb(struct device *dev)
0386 {
0387     struct iosm_pcie *ipc_pcie;
0388     struct pci_dev *pdev;
0389 
0390     pdev = to_pci_dev(dev);
0391 
0392     ipc_pcie = pci_get_drvdata(pdev);
0393 
0394     switch (ipc_pcie->d3l2_support) {
0395     case IPC_PCIE_D0L12:
0396         ipc_pcie_suspend_s2idle(ipc_pcie);
0397         break;
0398     case IPC_PCIE_D3L2:
0399         ipc_pcie_suspend(ipc_pcie);
0400         break;
0401     }
0402 
0403     return 0;
0404 }
0405 
0406 static int __maybe_unused ipc_pcie_resume_cb(struct device *dev)
0407 {
0408     struct iosm_pcie *ipc_pcie;
0409     struct pci_dev *pdev;
0410 
0411     pdev = to_pci_dev(dev);
0412 
0413     ipc_pcie = pci_get_drvdata(pdev);
0414 
0415     switch (ipc_pcie->d3l2_support) {
0416     case IPC_PCIE_D0L12:
0417         ipc_pcie_resume_s2idle(ipc_pcie);
0418         break;
0419     case IPC_PCIE_D3L2:
0420         ipc_pcie_resume(ipc_pcie);
0421         break;
0422     }
0423 
0424     return 0;
0425 }
0426 
0427 static SIMPLE_DEV_PM_OPS(iosm_ipc_pm, ipc_pcie_suspend_cb, ipc_pcie_resume_cb);
0428 
0429 static struct pci_driver iosm_ipc_driver = {
0430     .name = KBUILD_MODNAME,
0431     .probe = ipc_pcie_probe,
0432     .remove = ipc_pcie_remove,
0433     .driver = {
0434         .pm = &iosm_ipc_pm,
0435     },
0436     .id_table = iosm_ipc_ids,
0437 };
0438 module_pci_driver(iosm_ipc_driver);
0439 
0440 int ipc_pcie_addr_map(struct iosm_pcie *ipc_pcie, unsigned char *data,
0441               size_t size, dma_addr_t *mapping, int direction)
0442 {
0443     if (ipc_pcie->pci) {
0444         *mapping = dma_map_single(&ipc_pcie->pci->dev, data, size,
0445                       direction);
0446         if (dma_mapping_error(&ipc_pcie->pci->dev, *mapping)) {
0447             dev_err(ipc_pcie->dev, "dma mapping failed");
0448             return -EINVAL;
0449         }
0450     }
0451     return 0;
0452 }
0453 
0454 void ipc_pcie_addr_unmap(struct iosm_pcie *ipc_pcie, size_t size,
0455              dma_addr_t mapping, int direction)
0456 {
0457     if (!mapping)
0458         return;
0459     if (ipc_pcie->pci)
0460         dma_unmap_single(&ipc_pcie->pci->dev, mapping, size, direction);
0461 }
0462 
0463 struct sk_buff *ipc_pcie_alloc_local_skb(struct iosm_pcie *ipc_pcie,
0464                      gfp_t flags, size_t size)
0465 {
0466     struct sk_buff *skb;
0467 
0468     if (!ipc_pcie || !size) {
0469         pr_err("invalid pcie object or size");
0470         return NULL;
0471     }
0472 
0473     skb = __netdev_alloc_skb(NULL, size, flags);
0474     if (!skb)
0475         return NULL;
0476 
0477     IPC_CB(skb)->op_type = (u8)UL_DEFAULT;
0478     IPC_CB(skb)->mapping = 0;
0479 
0480     return skb;
0481 }
0482 
0483 struct sk_buff *ipc_pcie_alloc_skb(struct iosm_pcie *ipc_pcie, size_t size,
0484                    gfp_t flags, dma_addr_t *mapping,
0485                    int direction, size_t headroom)
0486 {
0487     struct sk_buff *skb = ipc_pcie_alloc_local_skb(ipc_pcie, flags,
0488                                size + headroom);
0489     if (!skb)
0490         return NULL;
0491 
0492     if (headroom)
0493         skb_reserve(skb, headroom);
0494 
0495     if (ipc_pcie_addr_map(ipc_pcie, skb->data, size, mapping, direction)) {
0496         dev_kfree_skb(skb);
0497         return NULL;
0498     }
0499 
0500     BUILD_BUG_ON(sizeof(*IPC_CB(skb)) > sizeof(skb->cb));
0501 
0502     /* Store the mapping address in skb scratch pad for later usage */
0503     IPC_CB(skb)->mapping = *mapping;
0504     IPC_CB(skb)->direction = direction;
0505     IPC_CB(skb)->len = size;
0506 
0507     return skb;
0508 }
0509 
0510 void ipc_pcie_kfree_skb(struct iosm_pcie *ipc_pcie, struct sk_buff *skb)
0511 {
0512     if (!skb)
0513         return;
0514 
0515     ipc_pcie_addr_unmap(ipc_pcie, IPC_CB(skb)->len, IPC_CB(skb)->mapping,
0516                 IPC_CB(skb)->direction);
0517     IPC_CB(skb)->mapping = 0;
0518     dev_kfree_skb(skb);
0519 }
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