wwan/iosm/iosm_ipc_mmio.h

0001 /* SPDX-License-Identifier: GPL-2.0-only
0002  *
0003  * Copyright (C) 2020-21 Intel Corporation.
0004  */
0005
0006 #ifndef IOSM_IPC_MMIO_H
0007 #define IOSM_IPC_MMIO_H
0008
0009 /* Minimal IOSM CP VERSION which has valid CP_CAPABILITIES field */
0010 #define IOSM_CP_VERSION 0x0100UL
0011
0012 /* DL dir Aggregation support mask */
0013 #define DL_AGGR BIT(9)
0014
0015 /* UL dir Aggregation support mask */
0016 #define UL_AGGR BIT(8)
0017
0018 /* UL flow credit support mask */
0019 #define UL_FLOW_CREDIT BIT(21)
0020
0021 /* Possible states of the IPC finite state machine. */
0022 enum ipc_mem_device_ipc_state {
0023     IPC_MEM_DEVICE_IPC_UNINIT,
0024     IPC_MEM_DEVICE_IPC_INIT,
0025     IPC_MEM_DEVICE_IPC_RUNNING,
0026     IPC_MEM_DEVICE_IPC_RECOVERY,
0027     IPC_MEM_DEVICE_IPC_ERROR,
0028     IPC_MEM_DEVICE_IPC_DONT_CARE,
0029     IPC_MEM_DEVICE_IPC_INVALID = -1
0030 };
0031
0032 /* Boot ROM exit status. */
0033 enum rom_exit_code {
0034     IMEM_ROM_EXIT_OPEN_EXT = 0x01,
0035     IMEM_ROM_EXIT_OPEN_MEM = 0x02,
0036     IMEM_ROM_EXIT_CERT_EXT = 0x10,
0037     IMEM_ROM_EXIT_CERT_MEM = 0x20,
0038     IMEM_ROM_EXIT_FAIL = 0xFF
0039 };
0040
0041 /* Boot stages */
0042 enum ipc_mem_exec_stage {
0043     IPC_MEM_EXEC_STAGE_RUN = 0x600DF00D,
0044     IPC_MEM_EXEC_STAGE_CRASH = 0x8BADF00D,
0045     IPC_MEM_EXEC_STAGE_CD_READY = 0xBADC0DED,
0046     IPC_MEM_EXEC_STAGE_BOOT = 0xFEEDB007,
0047     IPC_MEM_EXEC_STAGE_PSI = 0xFEEDBEEF,
0048     IPC_MEM_EXEC_STAGE_EBL = 0xFEEDCAFE,
0049     IPC_MEM_EXEC_STAGE_INVALID = 0xFFFFFFFF
0050 };
0051
0052 /* mmio scratchpad info */
0053 struct mmio_offset {
0054     int exec_stage;
0055     int chip_info;
0056     int rom_exit_code;
0057     int psi_address;
0058     int psi_size;
0059     int ipc_status;
0060     int context_info;
0061     int ap_win_base;
0062     int ap_win_end;
0063     int cp_version;
0064     int cp_capability;
0065 };
0066
0067 /**
0068  * struct iosm_mmio - MMIO region mapped to the doorbell scratchpad.
0069  * @base:       Base address of MMIO region
0070  * @dev:        Pointer to device structure
0071  * @offset:     Start offset
0072  * @context_info_addr:  Physical base address of context info structure
0073  * @chip_info_version:  Version of chip info structure
0074  * @chip_info_size: Size of chip info structure
0075  * @mux_protocol:   mux protocol
0076  * @has_ul_flow_credit: Ul flow credit support
0077  * @has_slp_no_prot:    Device sleep no protocol support
0078  * @has_mcr_support:    Usage of mcr support
0079  */
0080 struct iosm_mmio {
0081     unsigned char __iomem *base;
0082     struct device *dev;
0083     struct mmio_offset offset;
0084     phys_addr_t context_info_addr;
0085     unsigned int chip_info_version;
0086     unsigned int chip_info_size;
0087     u32 mux_protocol;
0088     u8 has_ul_flow_credit:1,
0089        has_slp_no_prot:1,
0090        has_mcr_support:1;
0091 };
0092
0093 /**
0094  * ipc_mmio_init - Allocate mmio instance data
0095  * @mmio_addr:  Mapped AP base address of the MMIO area.
0096  * @dev:    Pointer to device structure
0097  *
0098  * Returns: address of mmio instance data or NULL if fails.
0099  */
0100 struct iosm_mmio *ipc_mmio_init(void __iomem *mmio_addr, struct device *dev);
0101
0102 /**
0103  * ipc_mmio_set_psi_addr_and_size - Set start address and size of the
0104  *                  primary system image (PSI) for the
0105  *                  FW dowload.
0106  * @ipc_mmio:   Pointer to mmio instance
0107  * @addr:   PSI address
0108  * @size:   PSI immage size
0109  */
0110 void ipc_mmio_set_psi_addr_and_size(struct iosm_mmio *ipc_mmio, dma_addr_t addr,
0111                     u32 size);
0112
0113 /**
0114  * ipc_mmio_set_contex_info_addr - Stores the Context Info Address in
0115  *                 MMIO instance to share it with CP during
0116  *                 mmio_init.
0117  * @ipc_mmio:   Pointer to mmio instance
0118  * @addr:   64-bit address of AP context information.
0119  */
0120 void ipc_mmio_set_contex_info_addr(struct iosm_mmio *ipc_mmio,
0121                    phys_addr_t addr);
0122
0123 /**
0124  * ipc_mmio_get_cp_version - Get the CP IPC version
0125  * @ipc_mmio:   Pointer to mmio instance
0126  *
0127  * Returns: version number on success and failure value on error.
0128  */
0129 int ipc_mmio_get_cp_version(struct iosm_mmio *ipc_mmio);
0130
0131 /**
0132  * ipc_mmio_get_rom_exit_code - Get exit code from CP boot rom download app
0133  * @ipc_mmio:   Pointer to mmio instance
0134  *
0135  * Returns: exit code from CP boot rom download APP
0136  */
0137 enum rom_exit_code ipc_mmio_get_rom_exit_code(struct iosm_mmio *ipc_mmio);
0138
0139 /**
0140  * ipc_mmio_get_exec_stage - Query CP execution stage
0141  * @ipc_mmio:   Pointer to mmio instance
0142  *
0143  * Returns: CP execution stage
0144  */
0145 enum ipc_mem_exec_stage ipc_mmio_get_exec_stage(struct iosm_mmio *ipc_mmio);
0146
0147 /**
0148  * ipc_mmio_get_ipc_state - Query CP IPC state
0149  * @ipc_mmio:   Pointer to mmio instance
0150  *
0151  * Returns: CP IPC state
0152  */
0153 enum ipc_mem_device_ipc_state
0154 ipc_mmio_get_ipc_state(struct iosm_mmio *ipc_mmio);
0155
0156 /**
0157  * ipc_mmio_copy_chip_info - Copy size bytes of CP chip info structure
0158  *               into caller provided buffer
0159  * @ipc_mmio:   Pointer to mmio instance
0160  * @dest:   Pointer to caller provided buff
0161  * @size:   Number of bytes to copy
0162  */
0163 void ipc_mmio_copy_chip_info(struct iosm_mmio *ipc_mmio, void *dest,
0164                  size_t size);
0165
0166 /**
0167  * ipc_mmio_config - Write context info and AP memory range addresses.
0168  *           This needs to be called when CP is in
0169  *           IPC_MEM_DEVICE_IPC_INIT state
0170  *
0171  * @ipc_mmio:   Pointer to mmio instance
0172  */
0173 void ipc_mmio_config(struct iosm_mmio *ipc_mmio);
0174
0175 /**
0176  * ipc_mmio_update_cp_capability - Read and update modem capability, from mmio
0177  *                 capability offset
0178  *
0179  * @ipc_mmio:   Pointer to mmio instance
0180  */
0181 void ipc_mmio_update_cp_capability(struct iosm_mmio *ipc_mmio);
0182
0183 #endif