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0006 #ifndef _IOSM_IPC_FLASH_H
0007 #define _IOSM_IPC_FLASH_H
0008
0009
0010 #define IOSM_FLS_BUF_SIZE 0x00100000
0011
0012 #define IOSM_ERASE_START_ADDR 0x00000000
0013
0014 #define IOSM_ERASE_LEN 0xFFFFFFFF
0015
0016 #define IOSM_EBL_HEAD_SIZE 8
0017
0018 #define IOSM_EBL_W_PAYL_SIZE 2048
0019
0020 #define IOSM_EBL_W_PACK_SIZE (IOSM_EBL_HEAD_SIZE + IOSM_EBL_W_PAYL_SIZE)
0021
0022 #define IOSM_EBL_DW_PAYL_SIZE 16384
0023
0024 #define IOSM_EBL_DW_PACK_SIZE (IOSM_EBL_HEAD_SIZE + IOSM_EBL_DW_PAYL_SIZE)
0025
0026 #define IOSM_EBL_NAME 32
0027
0028 #define IOSM_MAX_ERRORS 8
0029
0030 #define IOSM_READ_SIZE 2
0031
0032 #define IOSM_LER_ACK_SIZE 2
0033
0034 #define IOSM_PSI_ACK 8
0035
0036 #define IOSM_EXT_CAP_SWID_OOS_PACK 0x02
0037
0038 #define IOSM_EBL_RSP_BUFF 0x0041
0039
0040 #define IOSM_SWID_STR 64
0041
0042 #define IOSM_RPSI_LOAD_SIZE 0
0043
0044 #define IOSM_EBL_CKSM 0x0000FFFF
0045
0046 #define IOSM_MSG_LEN_ARG 0
0047
0048 #define IOSM_MDM_SEND_DATA 0x0000
0049
0050 #define IOSM_MDM_ERASE_RSP 0x0001
0051
0052 #define IOSM_EBL_PAYL_SHIFT 16
0053
0054 #define IOSM_SET_FLAG 1
0055
0056 #define IOSM_FLASH_ERASE_CHECK_TIMEOUT 100
0057
0058 #define IOSM_FLASH_ERASE_CHECK_INTERVAL 20
0059
0060 #define IOSM_LER_RSP_SIZE 60
0061
0062
0063
0064
0065
0066
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0069
0070
0071
0072
0073
0074 enum iosm_flash_package_type {
0075 FLASH_SET_PROT_CONF = 0x0086,
0076 FLASH_SEC_START = 0x0204,
0077 FLASH_SEC_END,
0078 FLASH_SET_ADDRESS = 0x0802,
0079 FLASH_ERASE_START = 0x0805,
0080 FLASH_ERASE_CHECK,
0081 FLASH_OOS_CONTROL = 0x080C,
0082 FLASH_OOS_DATA_READ = 0x080E,
0083 FLASH_WRITE_IMAGE_RAW,
0084 };
0085
0086
0087
0088
0089
0090
0091
0092 enum iosm_out_of_session_action {
0093 FLASH_OOSC_ACTION_READ = 2,
0094 FLASH_OOSC_ACTION_ERASE = 3,
0095 };
0096
0097
0098
0099
0100
0101
0102
0103 enum iosm_out_of_session_type {
0104 FLASH_OOSC_TYPE_ALL_FLASH = 8,
0105 FLASH_OOSC_TYPE_SWID_TABLE = 16,
0106 };
0107
0108
0109
0110
0111
0112
0113
0114
0115 enum iosm_ebl_caps {
0116 IOSM_CAP_NOT_ENHANCED = 0x00,
0117 IOSM_CAP_USE_EXT_CAP = 0x01,
0118 IOSM_EXT_CAP_ERASE_ALL = 0x08,
0119 IOSM_EXT_CAP_COMMIT_ALL = 0x20,
0120 };
0121
0122
0123
0124
0125
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0129
0130
0131 enum iosm_ebl_rsp {
0132 EBL_CAPS_FLAG = 50,
0133 EBL_SKIP_ERASE = 54,
0134 EBL_SKIP_CRC = 55,
0135 EBL_EXT_CAPS_HANDLED = 57,
0136 EBL_OOS_CONFIG = 64,
0137 EBL_RSP_SW_INFO_VER = 70,
0138 };
0139
0140
0141
0142
0143
0144
0145
0146
0147 enum iosm_mdm_send_recv_data {
0148 IOSM_MDM_SEND_2 = 2,
0149 IOSM_MDM_SEND_4 = 4,
0150 IOSM_MDM_SEND_8 = 8,
0151 IOSM_MDM_SEND_16 = 16,
0152 };
0153
0154
0155
0156
0157
0158
0159 struct iosm_ebl_one_error {
0160 u16 error_class;
0161 u16 error_code;
0162 };
0163
0164
0165
0166
0167
0168 struct iosm_ebl_error {
0169 struct iosm_ebl_one_error error[IOSM_MAX_ERRORS];
0170 };
0171
0172
0173
0174
0175
0176
0177
0178
0179
0180 struct iosm_swid_table {
0181 u32 number_of_data_sets;
0182 char sw_id_type[IOSM_EBL_NAME];
0183 u32 sw_id_val;
0184 char rf_engine_id_type[IOSM_EBL_NAME];
0185 u32 rf_engine_id_val;
0186 };
0187
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0189
0190
0191
0192
0193
0194
0195 struct iosm_flash_msg_control {
0196 __le32 action;
0197 __le32 type;
0198 __le32 length;
0199 __le32 arguments;
0200 };
0201
0202
0203
0204
0205
0206
0207
0208 struct iosm_flash_data {
0209 __le16 checksum;
0210 __le16 pack_id;
0211 __le32 msg_length;
0212 };
0213
0214 int ipc_flash_boot_psi(struct iosm_devlink *ipc_devlink,
0215 const struct firmware *fw);
0216
0217 int ipc_flash_boot_ebl(struct iosm_devlink *ipc_devlink,
0218 const struct firmware *fw);
0219
0220 int ipc_flash_boot_set_capabilities(struct iosm_devlink *ipc_devlink,
0221 u8 *mdm_rsp);
0222
0223 int ipc_flash_link_establish(struct iosm_imem *ipc_imem);
0224
0225 int ipc_flash_read_swid(struct iosm_devlink *ipc_devlink, u8 *mdm_rsp);
0226
0227 int ipc_flash_send_fls(struct iosm_devlink *ipc_devlink,
0228 const struct firmware *fw, u8 *mdm_rsp);
0229 #endif