wwan/iosm/iosm_ipc_chnl_cfg.h

0001 /* SPDX-License-Identifier: GPL-2.0-only
0002  *
0003  * Copyright (C) 2020-21 Intel Corporation
0004  */
0005
0006 #ifndef IOSM_IPC_CHNL_CFG_H
0007 #define IOSM_IPC_CHNL_CFG_H
0008
0009 #include "iosm_ipc_mux.h"
0010
0011 /* Number of TDs on the trace channel */
0012 #define IPC_MEM_TDS_TRC 32
0013
0014 /* Trace channel TD buffer size. */
0015 #define IPC_MEM_MAX_DL_TRC_BUF_SIZE 8192
0016
0017 /* Channel ID */
0018 enum ipc_channel_id {
0019     IPC_MEM_IP_CHL_ID_0 = 0,
0020     IPC_MEM_CTRL_CHL_ID_1,
0021     IPC_MEM_CTRL_CHL_ID_2,
0022     IPC_MEM_CTRL_CHL_ID_3,
0023     IPC_MEM_CTRL_CHL_ID_4,
0024     IPC_MEM_CTRL_CHL_ID_5,
0025     IPC_MEM_CTRL_CHL_ID_6,
0026     IPC_MEM_CTRL_CHL_ID_7,
0027 };
0028
0029 /**
0030  * struct ipc_chnl_cfg - IPC channel configuration structure
0031  * @id:             Interface ID
0032  * @ul_pipe:            Uplink datastream
0033  * @dl_pipe:            Downlink datastream
0034  * @ul_nr_of_entries:       Number of Transfer descriptor uplink pipe
0035  * @dl_nr_of_entries:       Number of Transfer descriptor downlink pipe
0036  * @dl_buf_size:        Downlink buffer size
0037  * @wwan_port_type:     Wwan subsystem port type
0038  * @accumulation_backoff:   Time in usec for data accumalation
0039  */
0040 struct ipc_chnl_cfg {
0041     u32 id;
0042     u32 ul_pipe;
0043     u32 dl_pipe;
0044     u32 ul_nr_of_entries;
0045     u32 dl_nr_of_entries;
0046     u32 dl_buf_size;
0047     u32 wwan_port_type;
0048     u32 accumulation_backoff;
0049 };
0050
0051 /**
0052  * ipc_chnl_cfg_get - Get pipe configuration.
0053  * @chnl_cfg:       Array of ipc_chnl_cfg struct
0054  * @index:      Channel index (upto MAX_CHANNELS)
0055  *
0056  * Return: 0 on success and failure value on error
0057  */
0058 int ipc_chnl_cfg_get(struct ipc_chnl_cfg *chnl_cfg, int index);
0059
0060 #endif