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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /* ZD1211 USB-WLAN driver for Linux
0003  *
0004  * Copyright (C) 2005-2007 Ulrich Kunitz <kune@deine-taler.de>
0005  * Copyright (C) 2006-2007 Daniel Drake <dsd@gentoo.org>
0006  */
0007 
0008 #include <linux/kernel.h>
0009 
0010 #include "zd_rf.h"
0011 #include "zd_usb.h"
0012 #include "zd_chip.h"
0013 
0014 static const u32 rf2959_table[][2] = {
0015     RF_CHANNEL( 1) = { 0x181979, 0x1e6666 },
0016     RF_CHANNEL( 2) = { 0x181989, 0x1e6666 },
0017     RF_CHANNEL( 3) = { 0x181999, 0x1e6666 },
0018     RF_CHANNEL( 4) = { 0x1819a9, 0x1e6666 },
0019     RF_CHANNEL( 5) = { 0x1819b9, 0x1e6666 },
0020     RF_CHANNEL( 6) = { 0x1819c9, 0x1e6666 },
0021     RF_CHANNEL( 7) = { 0x1819d9, 0x1e6666 },
0022     RF_CHANNEL( 8) = { 0x1819e9, 0x1e6666 },
0023     RF_CHANNEL( 9) = { 0x1819f9, 0x1e6666 },
0024     RF_CHANNEL(10) = { 0x181a09, 0x1e6666 },
0025     RF_CHANNEL(11) = { 0x181a19, 0x1e6666 },
0026     RF_CHANNEL(12) = { 0x181a29, 0x1e6666 },
0027     RF_CHANNEL(13) = { 0x181a39, 0x1e6666 },
0028     RF_CHANNEL(14) = { 0x181a60, 0x1c0000 },
0029 };
0030 
0031 #if 0
0032 static int bits(u32 rw, int from, int to)
0033 {
0034     rw &= ~(0xffffffffU << (to+1));
0035     rw >>= from;
0036     return rw;
0037 }
0038 
0039 static int bit(u32 rw, int bit)
0040 {
0041     return bits(rw, bit, bit);
0042 }
0043 
0044 static void dump_regwrite(u32 rw)
0045 {
0046     int reg = bits(rw, 18, 22);
0047     int rw_flag = bits(rw, 23, 23);
0048     PDEBUG("rf2959 %#010x reg %d rw %d", rw, reg, rw_flag);
0049 
0050     switch (reg) {
0051     case 0:
0052         PDEBUG("reg0 CFG1 ref_sel %d hibernate %d rf_vco_reg_en %d"
0053                " if_vco_reg_en %d if_vga_en %d",
0054                bits(rw, 14, 15), bit(rw, 3), bit(rw, 2), bit(rw, 1),
0055                bit(rw, 0));
0056         break;
0057     case 1:
0058         PDEBUG("reg1 IFPLL1 pll_en1 %d kv_en1 %d vtc_en1 %d lpf1 %d"
0059                " cpl1 %d pdp1 %d autocal_en1 %d ld_en1 %d ifloopr %d"
0060                " ifloopc %d dac1 %d",
0061                bit(rw, 17), bit(rw, 16), bit(rw, 15), bit(rw, 14),
0062                bit(rw, 13), bit(rw, 12), bit(rw, 11), bit(rw, 10),
0063                bits(rw, 7, 9), bits(rw, 4, 6), bits(rw, 0, 3));
0064         break;
0065     case 2:
0066         PDEBUG("reg2 IFPLL2 n1 %d num1 %d",
0067                bits(rw, 6, 17), bits(rw, 0, 5));
0068         break;
0069     case 3:
0070         PDEBUG("reg3 IFPLL3 num %d", bits(rw, 0, 17));
0071         break;
0072     case 4:
0073         PDEBUG("reg4 IFPLL4 dn1 %#04x ct_def1 %d kv_def1 %d",
0074                bits(rw, 8, 16), bits(rw, 4, 7), bits(rw, 0, 3));
0075         break;
0076     case 5:
0077         PDEBUG("reg5 RFPLL1 pll_en %d kv_en %d vtc_en %d lpf %d cpl %d"
0078                " pdp %d autocal_en %d ld_en %d rfloopr %d rfloopc %d"
0079                " dac %d",
0080                bit(rw, 17), bit(rw, 16), bit(rw, 15), bit(rw, 14),
0081                bit(rw, 13), bit(rw, 12), bit(rw, 11), bit(rw, 10),
0082                bits(rw, 7, 9), bits(rw, 4, 6), bits(rw, 0,3));
0083         break;
0084     case 6:
0085         PDEBUG("reg6 RFPLL2 n %d num %d",
0086                bits(rw, 6, 17), bits(rw, 0, 5));
0087         break;
0088     case 7:
0089         PDEBUG("reg7 RFPLL3 num2 %d", bits(rw, 0, 17));
0090         break;
0091     case 8:
0092         PDEBUG("reg8 RFPLL4 dn %#06x ct_def %d kv_def %d",
0093                bits(rw, 8, 16), bits(rw, 4, 7), bits(rw, 0, 3));
0094         break;
0095     case 9:
0096         PDEBUG("reg9 CAL1 tvco %d tlock %d m_ct_value %d ld_window %d",
0097                bits(rw, 13, 17), bits(rw, 8, 12), bits(rw, 3, 7),
0098                bits(rw, 0, 2));
0099         break;
0100     case 10:
0101         PDEBUG("reg10 TXRX1 rxdcfbbyps %d pcontrol %d txvgc %d"
0102                " rxlpfbw %d txlpfbw %d txdiffmode %d txenmode %d"
0103                " intbiasen %d tybypass %d",
0104                bit(rw, 17), bits(rw, 15, 16), bits(rw, 10, 14),
0105                bits(rw, 7, 9), bits(rw, 4, 6), bit(rw, 3), bit(rw, 2),
0106                bit(rw, 1), bit(rw, 0));
0107         break;
0108     case 11:
0109         PDEBUG("reg11 PCNT1 mid_bias %d p_desired %d pc_offset %d"
0110             " tx_delay %d",
0111             bits(rw, 15, 17), bits(rw, 9, 14), bits(rw, 3, 8),
0112             bits(rw, 0, 2));
0113         break;
0114     case 12:
0115         PDEBUG("reg12 PCNT2 max_power %d mid_power %d min_power %d",
0116                bits(rw, 12, 17), bits(rw, 6, 11), bits(rw, 0, 5));
0117         break;
0118     case 13:
0119         PDEBUG("reg13 VCOT1 rfpll vco comp %d ifpll vco comp %d"
0120                " lobias %d if_biasbuf %d if_biasvco %d rf_biasbuf %d"
0121                " rf_biasvco %d",
0122                bit(rw, 17), bit(rw, 16), bit(rw, 15),
0123                bits(rw, 8, 9), bits(rw, 5, 7), bits(rw, 3, 4),
0124                bits(rw, 0, 2));
0125         break;
0126     case 14:
0127         PDEBUG("reg14 IQCAL rx_acal %d rx_pcal %d"
0128                " tx_acal %d tx_pcal %d",
0129                bits(rw, 13, 17), bits(rw, 9, 12), bits(rw, 4, 8),
0130                bits(rw, 0, 3));
0131         break;
0132     }
0133 }
0134 #endif /* 0 */
0135 
0136 static int rf2959_init_hw(struct zd_rf *rf)
0137 {
0138     int r;
0139     struct zd_chip *chip = zd_rf_to_chip(rf);
0140 
0141     static const struct zd_ioreq16 ioreqs[] = {
0142         { ZD_CR2,   0x1E }, { ZD_CR9,   0x20 }, { ZD_CR10,  0x89 },
0143         { ZD_CR11,  0x00 }, { ZD_CR15,  0xD0 }, { ZD_CR17,  0x68 },
0144         { ZD_CR19,  0x4a }, { ZD_CR20,  0x0c }, { ZD_CR21,  0x0E },
0145         { ZD_CR23,  0x48 },
0146         /* normal size for cca threshold */
0147         { ZD_CR24,  0x14 },
0148         /* { ZD_CR24,  0x20 }, */
0149         { ZD_CR26,  0x90 }, { ZD_CR27,  0x30 }, { ZD_CR29,  0x20 },
0150         { ZD_CR31,  0xb2 }, { ZD_CR32,  0x43 }, { ZD_CR33,  0x28 },
0151         { ZD_CR38,  0x30 }, { ZD_CR34,  0x0f }, { ZD_CR35,  0xF0 },
0152         { ZD_CR41,  0x2a }, { ZD_CR46,  0x7F }, { ZD_CR47,  0x1E },
0153         { ZD_CR51,  0xc5 }, { ZD_CR52,  0xc5 }, { ZD_CR53,  0xc5 },
0154         { ZD_CR79,  0x58 }, { ZD_CR80,  0x30 }, { ZD_CR81,  0x30 },
0155         { ZD_CR82,  0x00 }, { ZD_CR83,  0x24 }, { ZD_CR84,  0x04 },
0156         { ZD_CR85,  0x00 }, { ZD_CR86,  0x10 }, { ZD_CR87,  0x2A },
0157         { ZD_CR88,  0x10 }, { ZD_CR89,  0x24 }, { ZD_CR90,  0x18 },
0158         /* { ZD_CR91,  0x18 }, */
0159         /* should solve continuous CTS frame problems */
0160         { ZD_CR91,  0x00 },
0161         { ZD_CR92,  0x0a }, { ZD_CR93,  0x00 }, { ZD_CR94,  0x01 },
0162         { ZD_CR95,  0x00 }, { ZD_CR96,  0x40 }, { ZD_CR97,  0x37 },
0163         { ZD_CR98,  0x05 }, { ZD_CR99,  0x28 }, { ZD_CR100, 0x00 },
0164         { ZD_CR101, 0x13 }, { ZD_CR102, 0x27 }, { ZD_CR103, 0x27 },
0165         { ZD_CR104, 0x18 }, { ZD_CR105, 0x12 },
0166         /* normal size */
0167         { ZD_CR106, 0x1a },
0168         /* { ZD_CR106, 0x22 }, */
0169         { ZD_CR107, 0x24 }, { ZD_CR108, 0x0a }, { ZD_CR109, 0x13 },
0170         { ZD_CR110, 0x2F }, { ZD_CR111, 0x27 }, { ZD_CR112, 0x27 },
0171         { ZD_CR113, 0x27 }, { ZD_CR114, 0x27 }, { ZD_CR115, 0x40 },
0172         { ZD_CR116, 0x40 }, { ZD_CR117, 0xF0 }, { ZD_CR118, 0xF0 },
0173         { ZD_CR119, 0x16 },
0174         /* no TX continuation */
0175         { ZD_CR122, 0x00 },
0176         /* { ZD_CR122, 0xff }, */
0177         { ZD_CR127, 0x03 }, { ZD_CR131, 0x08 }, { ZD_CR138, 0x28 },
0178         { ZD_CR148, 0x44 }, { ZD_CR150, 0x10 }, { ZD_CR169, 0xBB },
0179         { ZD_CR170, 0xBB },
0180     };
0181 
0182     static const u32 rv[] = {
0183         0x000007,  /* REG0(CFG1) */
0184         0x07dd43,  /* REG1(IFPLL1) */
0185         0x080959,  /* REG2(IFPLL2) */
0186         0x0e6666,
0187         0x116a57,  /* REG4 */
0188         0x17dd43,  /* REG5 */
0189         0x1819f9,  /* REG6 */
0190         0x1e6666,
0191         0x214554,
0192         0x25e7fa,
0193         0x27fffa,
0194         /* The Zydas driver somehow forgets to set this value. It's
0195          * only set for Japan. We are using internal power control
0196          * for now.
0197          */
0198         0x294128, /* internal power */
0199         /* 0x28252c, */ /* External control TX power */
0200         /* ZD_CR31_CCK, ZD_CR51_6-36M, ZD_CR52_48M, ZD_CR53_54M */
0201         0x2c0000,
0202         0x300000,
0203         0x340000,  /* REG13(0xD) */
0204         0x381e0f,  /* REG14(0xE) */
0205         /* Bogus, RF2959's data sheet doesn't know register 27, which is
0206          * actually referenced here. The commented 0x11 is 17.
0207          */
0208         0x6c180f,  /* REG27(0x11) */
0209     };
0210 
0211     r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
0212     if (r)
0213         return r;
0214 
0215     return zd_rfwritev_locked(chip, rv, ARRAY_SIZE(rv), RF_RV_BITS);
0216 }
0217 
0218 static int rf2959_set_channel(struct zd_rf *rf, u8 channel)
0219 {
0220     int i, r;
0221     const u32 *rv = rf2959_table[channel-1];
0222     struct zd_chip *chip = zd_rf_to_chip(rf);
0223 
0224     for (i = 0; i < 2; i++) {
0225         r = zd_rfwrite_locked(chip, rv[i], RF_RV_BITS);
0226         if (r)
0227             return r;
0228     }
0229     return 0;
0230 }
0231 
0232 static int rf2959_switch_radio_on(struct zd_rf *rf)
0233 {
0234     static const struct zd_ioreq16 ioreqs[] = {
0235         { ZD_CR10, 0x89 },
0236         { ZD_CR11, 0x00 },
0237     };
0238     struct zd_chip *chip = zd_rf_to_chip(rf);
0239 
0240     return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
0241 }
0242 
0243 static int rf2959_switch_radio_off(struct zd_rf *rf)
0244 {
0245     static const struct zd_ioreq16 ioreqs[] = {
0246         { ZD_CR10, 0x15 },
0247         { ZD_CR11, 0x81 },
0248     };
0249     struct zd_chip *chip = zd_rf_to_chip(rf);
0250 
0251     return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
0252 }
0253 
0254 int zd_rf_init_rf2959(struct zd_rf *rf)
0255 {
0256     struct zd_chip *chip = zd_rf_to_chip(rf);
0257 
0258     if (zd_chip_is_zd1211b(chip)) {
0259         dev_err(zd_chip_dev(chip),
0260                "RF2959 is currently not supported for ZD1211B"
0261                " devices\n");
0262         return -ENODEV;
0263     }
0264     rf->init_hw = rf2959_init_hw;
0265     rf->set_channel = rf2959_set_channel;
0266     rf->switch_radio_on = rf2959_switch_radio_on;
0267     rf->switch_radio_off = rf2959_switch_radio_off;
0268     return 0;
0269 }
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