0001
0002
0003
0004
0005
0006
0007
0008 #ifndef _ZD_MAC_H
0009 #define _ZD_MAC_H
0010
0011 #include <linux/kernel.h>
0012 #include <net/mac80211.h>
0013
0014 #include "zd_chip.h"
0015
0016 struct zd_ctrlset {
0017 u8 modulation;
0018 __le16 tx_length;
0019 u8 control;
0020
0021 __le16 packet_length;
0022 __le16 current_length;
0023 u8 service;
0024 __le16 next_frame_length;
0025 } __packed;
0026
0027 #define ZD_CS_RESERVED_SIZE 25
0028
0029
0030
0031
0032
0033
0034
0035
0036 #define ZD_PURE_RATE_MASK 0x0f
0037 #define ZD_MODULATION_TYPE_MASK 0x10
0038 #define ZD_RATE_MASK (ZD_PURE_RATE_MASK|ZD_MODULATION_TYPE_MASK)
0039 #define ZD_PURE_RATE(modulation) ((modulation) & ZD_PURE_RATE_MASK)
0040 #define ZD_MODULATION_TYPE(modulation) ((modulation) & ZD_MODULATION_TYPE_MASK)
0041 #define ZD_RATE(modulation) ((modulation) & ZD_RATE_MASK)
0042
0043
0044
0045
0046
0047 #define ZD_CCK 0x00
0048 #define ZD_OFDM 0x10
0049
0050
0051
0052
0053
0054 #define ZD_CCK_RATE_1M (ZD_CCK|0x00)
0055 #define ZD_CCK_RATE_2M (ZD_CCK|0x01)
0056 #define ZD_CCK_RATE_5_5M (ZD_CCK|0x02)
0057 #define ZD_CCK_RATE_11M (ZD_CCK|0x03)
0058 #define ZD_OFDM_RATE_6M (ZD_OFDM|ZD_OFDM_PLCP_RATE_6M)
0059 #define ZD_OFDM_RATE_9M (ZD_OFDM|ZD_OFDM_PLCP_RATE_9M)
0060 #define ZD_OFDM_RATE_12M (ZD_OFDM|ZD_OFDM_PLCP_RATE_12M)
0061 #define ZD_OFDM_RATE_18M (ZD_OFDM|ZD_OFDM_PLCP_RATE_18M)
0062 #define ZD_OFDM_RATE_24M (ZD_OFDM|ZD_OFDM_PLCP_RATE_24M)
0063 #define ZD_OFDM_RATE_36M (ZD_OFDM|ZD_OFDM_PLCP_RATE_36M)
0064 #define ZD_OFDM_RATE_48M (ZD_OFDM|ZD_OFDM_PLCP_RATE_48M)
0065 #define ZD_OFDM_RATE_54M (ZD_OFDM|ZD_OFDM_PLCP_RATE_54M)
0066
0067
0068
0069
0070 #define ZD_CCK_PREA_LONG 0x00
0071 #define ZD_CCK_PREA_SHORT 0x20
0072 #define ZD_OFDM_MODE_11G 0x00
0073 #define ZD_OFDM_MODE_11A 0x20
0074
0075
0076 #define ZD_CS_NEED_RANDOM_BACKOFF 0x01
0077 #define ZD_CS_NO_ACK 0x02
0078
0079 #define ZD_CS_FRAME_TYPE_MASK 0x0c
0080 #define ZD_CS_DATA_FRAME 0x00
0081 #define ZD_CS_PS_POLL_FRAME 0x04
0082 #define ZD_CS_MANAGEMENT_FRAME 0x08
0083 #define ZD_CS_NO_SEQUENCE_CTL_FRAME 0x0c
0084
0085 #define ZD_CS_WAKE_DESTINATION 0x10
0086 #define ZD_CS_RTS 0x20
0087 #define ZD_CS_ENCRYPT 0x40
0088 #define ZD_CS_SELF_CTS 0x80
0089
0090
0091 #define ZD_PLCP_HEADER_SIZE 5
0092
0093 struct rx_length_info {
0094 __le16 length[3];
0095 __le16 tag;
0096 } __packed;
0097
0098 #define RX_LENGTH_INFO_TAG 0x697e
0099
0100 struct rx_status {
0101 u8 signal_quality_cck;
0102
0103 u8 signal_strength;
0104 u8 signal_quality_ofdm;
0105 u8 decryption_type;
0106 u8 frame_status;
0107 } __packed;
0108
0109
0110 #define ZD_RX_NO_WEP 0
0111 #define ZD_RX_WEP64 1
0112 #define ZD_RX_TKIP 2
0113 #define ZD_RX_AES 4
0114 #define ZD_RX_WEP128 5
0115 #define ZD_RX_WEP256 6
0116
0117
0118 #define ZD_RX_FRAME_MODULATION_MASK 0x01
0119 #define ZD_RX_CCK 0x00
0120 #define ZD_RX_OFDM 0x01
0121
0122 #define ZD_RX_TIMEOUT_ERROR 0x02
0123 #define ZD_RX_FIFO_OVERRUN_ERROR 0x04
0124 #define ZD_RX_DECRYPTION_ERROR 0x08
0125 #define ZD_RX_CRC32_ERROR 0x10
0126 #define ZD_RX_NO_ADDR1_MATCH_ERROR 0x20
0127 #define ZD_RX_CRC16_ERROR 0x40
0128 #define ZD_RX_ERROR 0x80
0129
0130 struct tx_retry_rate {
0131 int count;
0132 int rate[10];
0133 };
0134
0135 struct tx_status {
0136 u8 type;
0137 u8 id;
0138 u8 rate;
0139 u8 pad;
0140 u8 mac[ETH_ALEN];
0141 u8 retry;
0142 u8 failure;
0143 } __packed;
0144
0145 enum mac_flags {
0146 MAC_FIXED_CHANNEL = 0x01,
0147 };
0148
0149 struct housekeeping {
0150 struct delayed_work link_led_work;
0151 };
0152
0153 struct beacon {
0154 struct delayed_work watchdog_work;
0155 struct sk_buff *cur_beacon;
0156 unsigned long last_update;
0157 u16 interval;
0158 u8 period;
0159 };
0160
0161 enum zd_device_flags {
0162 ZD_DEVICE_RUNNING,
0163 };
0164
0165 #define ZD_MAC_STATS_BUFFER_SIZE 16
0166
0167 #define ZD_MAC_MAX_ACK_WAITERS 50
0168
0169 struct zd_mac {
0170 struct zd_chip chip;
0171 spinlock_t lock;
0172 spinlock_t intr_lock;
0173 struct ieee80211_hw *hw;
0174 struct ieee80211_vif *vif;
0175 struct housekeeping housekeeping;
0176 struct beacon beacon;
0177 struct work_struct set_rts_cts_work;
0178 struct work_struct process_intr;
0179 struct zd_mc_hash multicast_hash;
0180 u8 intr_buffer[USB_MAX_EP_INT_BUFFER];
0181 u8 regdomain;
0182 u8 default_regdomain;
0183 u8 channel;
0184 int type;
0185 int associated;
0186 unsigned long flags;
0187 struct sk_buff_head ack_wait_queue;
0188 struct ieee80211_channel channels[14];
0189 struct ieee80211_rate rates[12];
0190 struct ieee80211_supported_band band;
0191
0192
0193 unsigned int short_preamble:1;
0194
0195
0196 unsigned int pass_failed_fcs:1;
0197
0198
0199 unsigned int pass_ctrl:1;
0200
0201
0202 unsigned int ack_pending:1;
0203
0204
0205 int ack_signal;
0206 };
0207
0208 #define ZD_REGDOMAIN_FCC 0x10
0209 #define ZD_REGDOMAIN_IC 0x20
0210 #define ZD_REGDOMAIN_ETSI 0x30
0211 #define ZD_REGDOMAIN_SPAIN 0x31
0212 #define ZD_REGDOMAIN_FRANCE 0x32
0213 #define ZD_REGDOMAIN_JAPAN_2 0x40
0214 #define ZD_REGDOMAIN_JAPAN 0x41
0215 #define ZD_REGDOMAIN_JAPAN_3 0x49
0216
0217 enum {
0218 MIN_CHANNEL24 = 1,
0219 MAX_CHANNEL24 = 14,
0220 };
0221
0222 #define ZD_PLCP_SERVICE_LENGTH_EXTENSION 0x80
0223
0224 struct ofdm_plcp_header {
0225 u8 prefix[3];
0226 __le16 service;
0227 } __packed;
0228
0229 static inline u8 zd_ofdm_plcp_header_rate(const struct ofdm_plcp_header *header)
0230 {
0231 return header->prefix[0] & 0xf;
0232 }
0233
0234
0235
0236
0237
0238
0239
0240 #define ZD_OFDM_PLCP_RATE_6M 0xb
0241 #define ZD_OFDM_PLCP_RATE_9M 0xf
0242 #define ZD_OFDM_PLCP_RATE_12M 0xa
0243 #define ZD_OFDM_PLCP_RATE_18M 0xe
0244 #define ZD_OFDM_PLCP_RATE_24M 0x9
0245 #define ZD_OFDM_PLCP_RATE_36M 0xd
0246 #define ZD_OFDM_PLCP_RATE_48M 0x8
0247 #define ZD_OFDM_PLCP_RATE_54M 0xc
0248
0249 struct cck_plcp_header {
0250 u8 signal;
0251 u8 service;
0252 __le16 length;
0253 __le16 crc16;
0254 } __packed;
0255
0256 static inline u8 zd_cck_plcp_header_signal(const struct cck_plcp_header *header)
0257 {
0258 return header->signal;
0259 }
0260
0261
0262
0263
0264
0265
0266
0267
0268 #define ZD_CCK_PLCP_SIGNAL_1M 0x0a
0269 #define ZD_CCK_PLCP_SIGNAL_2M 0x14
0270 #define ZD_CCK_PLCP_SIGNAL_5M5 0x37
0271 #define ZD_CCK_PLCP_SIGNAL_11M 0x6e
0272
0273 static inline struct zd_mac *zd_hw_mac(struct ieee80211_hw *hw)
0274 {
0275 return hw->priv;
0276 }
0277
0278 static inline struct zd_mac *zd_chip_to_mac(struct zd_chip *chip)
0279 {
0280 return container_of(chip, struct zd_mac, chip);
0281 }
0282
0283 static inline struct zd_mac *zd_usb_to_mac(struct zd_usb *usb)
0284 {
0285 return zd_chip_to_mac(zd_usb_to_chip(usb));
0286 }
0287
0288 static inline u8 *zd_mac_get_perm_addr(struct zd_mac *mac)
0289 {
0290 return mac->hw->wiphy->perm_addr;
0291 }
0292
0293 #define zd_mac_dev(mac) (zd_chip_dev(&(mac)->chip))
0294
0295 struct ieee80211_hw *zd_mac_alloc_hw(struct usb_interface *intf);
0296 void zd_mac_clear(struct zd_mac *mac);
0297
0298 int zd_mac_preinit_hw(struct ieee80211_hw *hw);
0299 int zd_mac_init_hw(struct ieee80211_hw *hw);
0300
0301 int zd_mac_rx(struct ieee80211_hw *hw, const u8 *buffer, unsigned int length);
0302 void zd_mac_tx_failed(struct urb *urb);
0303 void zd_mac_tx_to_dev(struct sk_buff *skb, int error);
0304
0305 int zd_op_start(struct ieee80211_hw *hw);
0306 void zd_op_stop(struct ieee80211_hw *hw);
0307 int zd_restore_settings(struct zd_mac *mac);
0308
0309 #ifdef DEBUG
0310 void zd_dump_rx_status(const struct rx_status *status);
0311 #else
0312 #define zd_dump_rx_status(status)
0313 #endif
0314
0315 #endif