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0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /* ZD1211 USB-WLAN driver for Linux
0003  *
0004  * Copyright (C) 2005-2007 Ulrich Kunitz <kune@deine-taler.de>
0005  * Copyright (C) 2006-2007 Daniel Drake <dsd@gentoo.org>
0006  */
0007 
0008 #ifndef _ZD_CHIP_H
0009 #define _ZD_CHIP_H
0010 
0011 #include <net/mac80211.h>
0012 
0013 #include "zd_rf.h"
0014 #include "zd_usb.h"
0015 
0016 /* Header for the Media Access Controller (MAC) and the Baseband Processor
0017  * (BBP). It appears that the ZD1211 wraps the old ZD1205 with USB glue and
0018  * adds a processor for handling the USB protocol.
0019  */
0020 
0021 /* Address space */
0022 enum {
0023     /* CONTROL REGISTERS */
0024     CR_START            = 0x9000,
0025 
0026 
0027     /* FIRMWARE */
0028     FW_START            = 0xee00,
0029 
0030 
0031     /* EEPROM */
0032     E2P_START           = 0xf800,
0033     E2P_LEN             = 0x800,
0034 
0035     /* EEPROM layout */
0036     E2P_LOAD_CODE_LEN       = 0xe,      /* base 0xf800 */
0037     E2P_LOAD_VECT_LEN       = 0x9,      /* base 0xf80e */
0038     /* E2P_DATA indexes into this */
0039     E2P_DATA_LEN            = 0x7e,     /* base 0xf817 */
0040     E2P_BOOT_CODE_LEN       = 0x760,    /* base 0xf895 */
0041     E2P_INTR_VECT_LEN       = 0xb,      /* base 0xfff5 */
0042 
0043     /* Some precomputed offsets into the EEPROM */
0044     E2P_DATA_OFFSET         = E2P_LOAD_CODE_LEN + E2P_LOAD_VECT_LEN,
0045     E2P_BOOT_CODE_OFFSET        = E2P_DATA_OFFSET + E2P_DATA_LEN,
0046 };
0047 
0048 #define CTL_REG(offset) ((zd_addr_t)(CR_START + (offset)))
0049 #define E2P_DATA(offset) ((zd_addr_t)(E2P_START + E2P_DATA_OFFSET + (offset)))
0050 #define FWRAW_DATA(offset) ((zd_addr_t)(FW_START + (offset)))
0051 
0052 /* 8-bit hardware registers */
0053 #define ZD_CR0   CTL_REG(0x0000)
0054 #define ZD_CR1   CTL_REG(0x0004)
0055 #define ZD_CR2   CTL_REG(0x0008)
0056 #define ZD_CR3   CTL_REG(0x000C)
0057 
0058 #define ZD_CR5   CTL_REG(0x0010)
0059 /*  bit 5: if set short preamble used
0060  *  bit 6: filter band - Japan channel 14 on, else off
0061  */
0062 #define ZD_CR6   CTL_REG(0x0014)
0063 #define ZD_CR7   CTL_REG(0x0018)
0064 #define ZD_CR8   CTL_REG(0x001C)
0065 
0066 #define ZD_CR4   CTL_REG(0x0020)
0067 
0068 #define ZD_CR9   CTL_REG(0x0024)
0069 /*  bit 2: antenna switch (together with ZD_CR10) */
0070 #define ZD_CR10  CTL_REG(0x0028)
0071 /*  bit 1: antenna switch (together with ZD_CR9)
0072  *  RF2959 controls with ZD_CR11 radion on and off
0073  */
0074 #define ZD_CR11  CTL_REG(0x002C)
0075 /*  bit 6:  TX power control for OFDM
0076  *  RF2959 controls with ZD_CR10 radio on and off
0077  */
0078 #define ZD_CR12  CTL_REG(0x0030)
0079 #define ZD_CR13  CTL_REG(0x0034)
0080 #define ZD_CR14  CTL_REG(0x0038)
0081 #define ZD_CR15  CTL_REG(0x003C)
0082 #define ZD_CR16  CTL_REG(0x0040)
0083 #define ZD_CR17  CTL_REG(0x0044)
0084 #define ZD_CR18  CTL_REG(0x0048)
0085 #define ZD_CR19  CTL_REG(0x004C)
0086 #define ZD_CR20  CTL_REG(0x0050)
0087 #define ZD_CR21  CTL_REG(0x0054)
0088 #define ZD_CR22  CTL_REG(0x0058)
0089 #define ZD_CR23  CTL_REG(0x005C)
0090 #define ZD_CR24  CTL_REG(0x0060)    /* CCA threshold */
0091 #define ZD_CR25  CTL_REG(0x0064)
0092 #define ZD_CR26  CTL_REG(0x0068)
0093 #define ZD_CR27  CTL_REG(0x006C)
0094 #define ZD_CR28  CTL_REG(0x0070)
0095 #define ZD_CR29  CTL_REG(0x0074)
0096 #define ZD_CR30  CTL_REG(0x0078)
0097 #define ZD_CR31  CTL_REG(0x007C)    /* TX power control for RF in
0098                      * CCK mode
0099                      */
0100 #define ZD_CR32  CTL_REG(0x0080)
0101 #define ZD_CR33  CTL_REG(0x0084)
0102 #define ZD_CR34  CTL_REG(0x0088)
0103 #define ZD_CR35  CTL_REG(0x008C)
0104 #define ZD_CR36  CTL_REG(0x0090)
0105 #define ZD_CR37  CTL_REG(0x0094)
0106 #define ZD_CR38  CTL_REG(0x0098)
0107 #define ZD_CR39  CTL_REG(0x009C)
0108 #define ZD_CR40  CTL_REG(0x00A0)
0109 #define ZD_CR41  CTL_REG(0x00A4)
0110 #define ZD_CR42  CTL_REG(0x00A8)
0111 #define ZD_CR43  CTL_REG(0x00AC)
0112 #define ZD_CR44  CTL_REG(0x00B0)
0113 #define ZD_CR45  CTL_REG(0x00B4)
0114 #define ZD_CR46  CTL_REG(0x00B8)
0115 #define ZD_CR47  CTL_REG(0x00BC)    /* CCK baseband gain
0116                      * (patch value might be in EEPROM)
0117                      */
0118 #define ZD_CR48  CTL_REG(0x00C0)
0119 #define ZD_CR49  CTL_REG(0x00C4)
0120 #define ZD_CR50  CTL_REG(0x00C8)
0121 #define ZD_CR51  CTL_REG(0x00CC)    /* TX power control for RF in
0122                      * 6-36M modes
0123                      */
0124 #define ZD_CR52  CTL_REG(0x00D0)    /* TX power control for RF in
0125                      * 48M mode
0126                      */
0127 #define ZD_CR53  CTL_REG(0x00D4)    /* TX power control for RF in
0128                      * 54M mode
0129                      */
0130 #define ZD_CR54  CTL_REG(0x00D8)
0131 #define ZD_CR55  CTL_REG(0x00DC)
0132 #define ZD_CR56  CTL_REG(0x00E0)
0133 #define ZD_CR57  CTL_REG(0x00E4)
0134 #define ZD_CR58  CTL_REG(0x00E8)
0135 #define ZD_CR59  CTL_REG(0x00EC)
0136 #define ZD_CR60  CTL_REG(0x00F0)
0137 #define ZD_CR61  CTL_REG(0x00F4)
0138 #define ZD_CR62  CTL_REG(0x00F8)
0139 #define ZD_CR63  CTL_REG(0x00FC)
0140 #define ZD_CR64  CTL_REG(0x0100)
0141 #define ZD_CR65  CTL_REG(0x0104) /* OFDM 54M calibration */
0142 #define ZD_CR66  CTL_REG(0x0108) /* OFDM 48M calibration */
0143 #define ZD_CR67  CTL_REG(0x010C) /* OFDM 36M calibration */
0144 #define ZD_CR68  CTL_REG(0x0110) /* CCK calibration */
0145 #define ZD_CR69  CTL_REG(0x0114)
0146 #define ZD_CR70  CTL_REG(0x0118)
0147 #define ZD_CR71  CTL_REG(0x011C)
0148 #define ZD_CR72  CTL_REG(0x0120)
0149 #define ZD_CR73  CTL_REG(0x0124)
0150 #define ZD_CR74  CTL_REG(0x0128)
0151 #define ZD_CR75  CTL_REG(0x012C)
0152 #define ZD_CR76  CTL_REG(0x0130)
0153 #define ZD_CR77  CTL_REG(0x0134)
0154 #define ZD_CR78  CTL_REG(0x0138)
0155 #define ZD_CR79  CTL_REG(0x013C)
0156 #define ZD_CR80  CTL_REG(0x0140)
0157 #define ZD_CR81  CTL_REG(0x0144)
0158 #define ZD_CR82  CTL_REG(0x0148)
0159 #define ZD_CR83  CTL_REG(0x014C)
0160 #define ZD_CR84  CTL_REG(0x0150)
0161 #define ZD_CR85  CTL_REG(0x0154)
0162 #define ZD_CR86  CTL_REG(0x0158)
0163 #define ZD_CR87  CTL_REG(0x015C)
0164 #define ZD_CR88  CTL_REG(0x0160)
0165 #define ZD_CR89  CTL_REG(0x0164)
0166 #define ZD_CR90  CTL_REG(0x0168)
0167 #define ZD_CR91  CTL_REG(0x016C)
0168 #define ZD_CR92  CTL_REG(0x0170)
0169 #define ZD_CR93  CTL_REG(0x0174)
0170 #define ZD_CR94  CTL_REG(0x0178)
0171 #define ZD_CR95  CTL_REG(0x017C)
0172 #define ZD_CR96  CTL_REG(0x0180)
0173 #define ZD_CR97  CTL_REG(0x0184)
0174 #define ZD_CR98  CTL_REG(0x0188)
0175 #define ZD_CR99  CTL_REG(0x018C)
0176 #define ZD_CR100 CTL_REG(0x0190)
0177 #define ZD_CR101 CTL_REG(0x0194)
0178 #define ZD_CR102 CTL_REG(0x0198)
0179 #define ZD_CR103 CTL_REG(0x019C)
0180 #define ZD_CR104 CTL_REG(0x01A0)
0181 #define ZD_CR105 CTL_REG(0x01A4)
0182 #define ZD_CR106 CTL_REG(0x01A8)
0183 #define ZD_CR107 CTL_REG(0x01AC)
0184 #define ZD_CR108 CTL_REG(0x01B0)
0185 #define ZD_CR109 CTL_REG(0x01B4)
0186 #define ZD_CR110 CTL_REG(0x01B8)
0187 #define ZD_CR111 CTL_REG(0x01BC)
0188 #define ZD_CR112 CTL_REG(0x01C0)
0189 #define ZD_CR113 CTL_REG(0x01C4)
0190 #define ZD_CR114 CTL_REG(0x01C8)
0191 #define ZD_CR115 CTL_REG(0x01CC)
0192 #define ZD_CR116 CTL_REG(0x01D0)
0193 #define ZD_CR117 CTL_REG(0x01D4)
0194 #define ZD_CR118 CTL_REG(0x01D8)
0195 #define ZD_CR119 CTL_REG(0x01DC)
0196 #define ZD_CR120 CTL_REG(0x01E0)
0197 #define ZD_CR121 CTL_REG(0x01E4)
0198 #define ZD_CR122 CTL_REG(0x01E8)
0199 #define ZD_CR123 CTL_REG(0x01EC)
0200 #define ZD_CR124 CTL_REG(0x01F0)
0201 #define ZD_CR125 CTL_REG(0x01F4)
0202 #define ZD_CR126 CTL_REG(0x01F8)
0203 #define ZD_CR127 CTL_REG(0x01FC)
0204 #define ZD_CR128 CTL_REG(0x0200)
0205 #define ZD_CR129 CTL_REG(0x0204)
0206 #define ZD_CR130 CTL_REG(0x0208)
0207 #define ZD_CR131 CTL_REG(0x020C)
0208 #define ZD_CR132 CTL_REG(0x0210)
0209 #define ZD_CR133 CTL_REG(0x0214)
0210 #define ZD_CR134 CTL_REG(0x0218)
0211 #define ZD_CR135 CTL_REG(0x021C)
0212 #define ZD_CR136 CTL_REG(0x0220)
0213 #define ZD_CR137 CTL_REG(0x0224)
0214 #define ZD_CR138 CTL_REG(0x0228)
0215 #define ZD_CR139 CTL_REG(0x022C)
0216 #define ZD_CR140 CTL_REG(0x0230)
0217 #define ZD_CR141 CTL_REG(0x0234)
0218 #define ZD_CR142 CTL_REG(0x0238)
0219 #define ZD_CR143 CTL_REG(0x023C)
0220 #define ZD_CR144 CTL_REG(0x0240)
0221 #define ZD_CR145 CTL_REG(0x0244)
0222 #define ZD_CR146 CTL_REG(0x0248)
0223 #define ZD_CR147 CTL_REG(0x024C)
0224 #define ZD_CR148 CTL_REG(0x0250)
0225 #define ZD_CR149 CTL_REG(0x0254)
0226 #define ZD_CR150 CTL_REG(0x0258)
0227 #define ZD_CR151 CTL_REG(0x025C)
0228 #define ZD_CR152 CTL_REG(0x0260)
0229 #define ZD_CR153 CTL_REG(0x0264)
0230 #define ZD_CR154 CTL_REG(0x0268)
0231 #define ZD_CR155 CTL_REG(0x026C)
0232 #define ZD_CR156 CTL_REG(0x0270)
0233 #define ZD_CR157 CTL_REG(0x0274)
0234 #define ZD_CR158 CTL_REG(0x0278)
0235 #define ZD_CR159 CTL_REG(0x027C)
0236 #define ZD_CR160 CTL_REG(0x0280)
0237 #define ZD_CR161 CTL_REG(0x0284)
0238 #define ZD_CR162 CTL_REG(0x0288)
0239 #define ZD_CR163 CTL_REG(0x028C)
0240 #define ZD_CR164 CTL_REG(0x0290)
0241 #define ZD_CR165 CTL_REG(0x0294)
0242 #define ZD_CR166 CTL_REG(0x0298)
0243 #define ZD_CR167 CTL_REG(0x029C)
0244 #define ZD_CR168 CTL_REG(0x02A0)
0245 #define ZD_CR169 CTL_REG(0x02A4)
0246 #define ZD_CR170 CTL_REG(0x02A8)
0247 #define ZD_CR171 CTL_REG(0x02AC)
0248 #define ZD_CR172 CTL_REG(0x02B0)
0249 #define ZD_CR173 CTL_REG(0x02B4)
0250 #define ZD_CR174 CTL_REG(0x02B8)
0251 #define ZD_CR175 CTL_REG(0x02BC)
0252 #define ZD_CR176 CTL_REG(0x02C0)
0253 #define ZD_CR177 CTL_REG(0x02C4)
0254 #define ZD_CR178 CTL_REG(0x02C8)
0255 #define ZD_CR179 CTL_REG(0x02CC)
0256 #define ZD_CR180 CTL_REG(0x02D0)
0257 #define ZD_CR181 CTL_REG(0x02D4)
0258 #define ZD_CR182 CTL_REG(0x02D8)
0259 #define ZD_CR183 CTL_REG(0x02DC)
0260 #define ZD_CR184 CTL_REG(0x02E0)
0261 #define ZD_CR185 CTL_REG(0x02E4)
0262 #define ZD_CR186 CTL_REG(0x02E8)
0263 #define ZD_CR187 CTL_REG(0x02EC)
0264 #define ZD_CR188 CTL_REG(0x02F0)
0265 #define ZD_CR189 CTL_REG(0x02F4)
0266 #define ZD_CR190 CTL_REG(0x02F8)
0267 #define ZD_CR191 CTL_REG(0x02FC)
0268 #define ZD_CR192 CTL_REG(0x0300)
0269 #define ZD_CR193 CTL_REG(0x0304)
0270 #define ZD_CR194 CTL_REG(0x0308)
0271 #define ZD_CR195 CTL_REG(0x030C)
0272 #define ZD_CR196 CTL_REG(0x0310)
0273 #define ZD_CR197 CTL_REG(0x0314)
0274 #define ZD_CR198 CTL_REG(0x0318)
0275 #define ZD_CR199 CTL_REG(0x031C)
0276 #define ZD_CR200 CTL_REG(0x0320)
0277 #define ZD_CR201 CTL_REG(0x0324)
0278 #define ZD_CR202 CTL_REG(0x0328)
0279 #define ZD_CR203 CTL_REG(0x032C)    /* I2C bus template value & flash
0280                      * control
0281                      */
0282 #define ZD_CR204 CTL_REG(0x0330)
0283 #define ZD_CR205 CTL_REG(0x0334)
0284 #define ZD_CR206 CTL_REG(0x0338)
0285 #define ZD_CR207 CTL_REG(0x033C)
0286 #define ZD_CR208 CTL_REG(0x0340)
0287 #define ZD_CR209 CTL_REG(0x0344)
0288 #define ZD_CR210 CTL_REG(0x0348)
0289 #define ZD_CR211 CTL_REG(0x034C)
0290 #define ZD_CR212 CTL_REG(0x0350)
0291 #define ZD_CR213 CTL_REG(0x0354)
0292 #define ZD_CR214 CTL_REG(0x0358)
0293 #define ZD_CR215 CTL_REG(0x035C)
0294 #define ZD_CR216 CTL_REG(0x0360)
0295 #define ZD_CR217 CTL_REG(0x0364)
0296 #define ZD_CR218 CTL_REG(0x0368)
0297 #define ZD_CR219 CTL_REG(0x036C)
0298 #define ZD_CR220 CTL_REG(0x0370)
0299 #define ZD_CR221 CTL_REG(0x0374)
0300 #define ZD_CR222 CTL_REG(0x0378)
0301 #define ZD_CR223 CTL_REG(0x037C)
0302 #define ZD_CR224 CTL_REG(0x0380)
0303 #define ZD_CR225 CTL_REG(0x0384)
0304 #define ZD_CR226 CTL_REG(0x0388)
0305 #define ZD_CR227 CTL_REG(0x038C)
0306 #define ZD_CR228 CTL_REG(0x0390)
0307 #define ZD_CR229 CTL_REG(0x0394)
0308 #define ZD_CR230 CTL_REG(0x0398)
0309 #define ZD_CR231 CTL_REG(0x039C)
0310 #define ZD_CR232 CTL_REG(0x03A0)
0311 #define ZD_CR233 CTL_REG(0x03A4)
0312 #define ZD_CR234 CTL_REG(0x03A8)
0313 #define ZD_CR235 CTL_REG(0x03AC)
0314 #define ZD_CR236 CTL_REG(0x03B0)
0315 
0316 #define ZD_CR240 CTL_REG(0x03C0)
0317 /*             bit 7: host-controlled RF register writes
0318  * ZD_CR241-ZD_CR245: for hardware controlled writing of RF bits, not needed for
0319  *                    USB
0320  */
0321 #define ZD_CR241 CTL_REG(0x03C4)
0322 #define ZD_CR242 CTL_REG(0x03C8)
0323 #define ZD_CR243 CTL_REG(0x03CC)
0324 #define ZD_CR244 CTL_REG(0x03D0)
0325 #define ZD_CR245 CTL_REG(0x03D4)
0326 
0327 #define ZD_CR251 CTL_REG(0x03EC)    /* only used for activation and
0328                      * deactivation of Airoha RFs AL2230
0329                      * and AL7230B
0330                      */
0331 #define ZD_CR252 CTL_REG(0x03F0)
0332 #define ZD_CR253 CTL_REG(0x03F4)
0333 #define ZD_CR254 CTL_REG(0x03F8)
0334 #define ZD_CR255 CTL_REG(0x03FC)
0335 
0336 #define CR_MAX_PHY_REG 255
0337 
0338 /* Taken from the ZYDAS driver, not all of them are relevant for the ZD1211
0339  * driver.
0340  */
0341 
0342 #define CR_RF_IF_CLK            CTL_REG(0x0400)
0343 #define CR_RF_IF_DATA           CTL_REG(0x0404)
0344 #define CR_PE1_PE2          CTL_REG(0x0408)
0345 #define CR_PE2_DLY          CTL_REG(0x040C)
0346 #define CR_LE1              CTL_REG(0x0410)
0347 #define CR_LE2              CTL_REG(0x0414)
0348 /* Seems to enable/disable GPI (General Purpose IO?) */
0349 #define CR_GPI_EN           CTL_REG(0x0418)
0350 #define CR_RADIO_PD         CTL_REG(0x042C)
0351 #define CR_RF2948_PD            CTL_REG(0x042C)
0352 #define CR_ENABLE_PS_MANUAL_AGC     CTL_REG(0x043C)
0353 #define CR_CONFIG_PHILIPS       CTL_REG(0x0440)
0354 #define CR_SA2400_SER_AP        CTL_REG(0x0444)
0355 #define CR_I2C_WRITE            CTL_REG(0x0444)
0356 #define CR_SA2400_SER_RP        CTL_REG(0x0448)
0357 #define CR_RADIO_PE         CTL_REG(0x0458)
0358 #define CR_RST_BUS_MASTER       CTL_REG(0x045C)
0359 #define CR_RFCFG            CTL_REG(0x0464)
0360 #define CR_HSTSCHG          CTL_REG(0x046C)
0361 #define CR_PHY_ON           CTL_REG(0x0474)
0362 #define CR_RX_DELAY         CTL_REG(0x0478)
0363 #define CR_RX_PE_DELAY          CTL_REG(0x047C)
0364 #define CR_GPIO_1           CTL_REG(0x0490)
0365 #define CR_GPIO_2           CTL_REG(0x0494)
0366 #define CR_EncryBufMux          CTL_REG(0x04A8)
0367 #define CR_PS_CTRL          CTL_REG(0x0500)
0368 #define CR_ADDA_PWR_DWN         CTL_REG(0x0504)
0369 #define CR_ADDA_MBIAS_WARMTIME      CTL_REG(0x0508)
0370 #define CR_MAC_PS_STATE         CTL_REG(0x050C)
0371 
0372 #define CR_INTERRUPT            CTL_REG(0x0510)
0373 #define INT_TX_COMPLETE         (1 <<  0)
0374 #define INT_RX_COMPLETE         (1 <<  1)
0375 #define INT_RETRY_FAIL          (1 <<  2)
0376 #define INT_WAKEUP          (1 <<  3)
0377 #define INT_DTIM_NOTIFY         (1 <<  5)
0378 #define INT_CFG_NEXT_BCN        (1 <<  6)
0379 #define INT_BUS_ABORT           (1 <<  7)
0380 #define INT_TX_FIFO_READY       (1 <<  8)
0381 #define INT_UART            (1 <<  9)
0382 #define INT_TX_COMPLETE_EN      (1 << 16)
0383 #define INT_RX_COMPLETE_EN      (1 << 17)
0384 #define INT_RETRY_FAIL_EN       (1 << 18)
0385 #define INT_WAKEUP_EN           (1 << 19)
0386 #define INT_DTIM_NOTIFY_EN      (1 << 21)
0387 #define INT_CFG_NEXT_BCN_EN     (1 << 22)
0388 #define INT_BUS_ABORT_EN        (1 << 23)
0389 #define INT_TX_FIFO_READY_EN        (1 << 24)
0390 #define INT_UART_EN         (1 << 25)
0391 
0392 #define CR_TSF_LOW_PART         CTL_REG(0x0514)
0393 #define CR_TSF_HIGH_PART        CTL_REG(0x0518)
0394 
0395 /* Following three values are in time units (1024us)
0396  * Following condition must be met:
0397  * atim < tbtt < bcn
0398  */
0399 #define CR_ATIM_WND_PERIOD      CTL_REG(0x051C)
0400 #define CR_BCN_INTERVAL         CTL_REG(0x0520)
0401 #define CR_PRE_TBTT         CTL_REG(0x0524)
0402 /* in units of TU(1024us) */
0403 
0404 /* for UART support */
0405 #define CR_UART_RBR_THR_DLL     CTL_REG(0x0540)
0406 #define CR_UART_DLM_IER         CTL_REG(0x0544)
0407 #define CR_UART_IIR_FCR         CTL_REG(0x0548)
0408 #define CR_UART_LCR         CTL_REG(0x054c)
0409 #define CR_UART_MCR         CTL_REG(0x0550)
0410 #define CR_UART_LSR         CTL_REG(0x0554)
0411 #define CR_UART_MSR         CTL_REG(0x0558)
0412 #define CR_UART_ECR         CTL_REG(0x055c)
0413 #define CR_UART_STATUS          CTL_REG(0x0560)
0414 
0415 #define CR_PCI_TX_ADDR_P1       CTL_REG(0x0600)
0416 #define CR_PCI_TX_AddR_P2       CTL_REG(0x0604)
0417 #define CR_PCI_RX_AddR_P1       CTL_REG(0x0608)
0418 #define CR_PCI_RX_AddR_P2       CTL_REG(0x060C)
0419 
0420 /* must be overwritten if custom MAC address will be used */
0421 #define CR_MAC_ADDR_P1          CTL_REG(0x0610)
0422 #define CR_MAC_ADDR_P2          CTL_REG(0x0614)
0423 #define CR_BSSID_P1         CTL_REG(0x0618)
0424 #define CR_BSSID_P2         CTL_REG(0x061C)
0425 #define CR_BCN_PLCP_CFG         CTL_REG(0x0620)
0426 
0427 /* Group hash table for filtering incoming packets.
0428  *
0429  * The group hash table is 64 bit large and split over two parts. The first
0430  * part is the lower part. The upper 6 bits of the last byte of the target
0431  * address are used as index. Packets are received if the hash table bit is
0432  * set. This is used for multicast handling, but for broadcasts (address
0433  * ff:ff:ff:ff:ff:ff) the highest bit in the second table must also be set.
0434  */
0435 #define CR_GROUP_HASH_P1        CTL_REG(0x0624)
0436 #define CR_GROUP_HASH_P2        CTL_REG(0x0628)
0437 
0438 #define CR_RX_TIMEOUT           CTL_REG(0x062C)
0439 
0440 /* Basic rates supported by the BSS. When producing ACK or CTS messages, the
0441  * device will use a rate in this table that is less than or equal to the rate
0442  * of the incoming frame which prompted the response. */
0443 #define CR_BASIC_RATE_TBL       CTL_REG(0x0630)
0444 #define CR_RATE_1M  (1 <<  0)   /* 802.11b */
0445 #define CR_RATE_2M  (1 <<  1)   /* 802.11b */
0446 #define CR_RATE_5_5M    (1 <<  2)   /* 802.11b */
0447 #define CR_RATE_11M (1 <<  3)   /* 802.11b */
0448 #define CR_RATE_6M      (1 <<  8)   /* 802.11g */
0449 #define CR_RATE_9M      (1 <<  9)   /* 802.11g */
0450 #define CR_RATE_12M (1 << 10)   /* 802.11g */
0451 #define CR_RATE_18M (1 << 11)   /* 802.11g */
0452 #define CR_RATE_24M     (1 << 12)   /* 802.11g */
0453 #define CR_RATE_36M     (1 << 13)   /* 802.11g */
0454 #define CR_RATE_48M     (1 << 14)   /* 802.11g */
0455 #define CR_RATE_54M     (1 << 15)   /* 802.11g */
0456 #define CR_RATES_80211G 0xff00
0457 #define CR_RATES_80211B 0x000f
0458 
0459 /* Mandatory rates required in the BSS. When producing ACK or CTS messages, if
0460  * the device could not find an appropriate rate in CR_BASIC_RATE_TBL, it will
0461  * look for a rate in this table that is less than or equal to the rate of
0462  * the incoming frame. */
0463 #define CR_MANDATORY_RATE_TBL       CTL_REG(0x0634)
0464 #define CR_RTS_CTS_RATE         CTL_REG(0x0638)
0465 
0466 /* These are all bit indexes in CR_RTS_CTS_RATE, so remember to shift. */
0467 #define RTSCTS_SH_RTS_RATE      0
0468 #define RTSCTS_SH_EXP_CTS_RATE      4
0469 #define RTSCTS_SH_RTS_MOD_TYPE      8
0470 #define RTSCTS_SH_RTS_PMB_TYPE      9
0471 #define RTSCTS_SH_CTS_RATE      16
0472 #define RTSCTS_SH_CTS_MOD_TYPE      24
0473 #define RTSCTS_SH_CTS_PMB_TYPE      25
0474 
0475 #define CR_WEP_PROTECT          CTL_REG(0x063C)
0476 #define CR_RX_THRESHOLD         CTL_REG(0x0640)
0477 
0478 /* register for controlling the LEDS */
0479 #define CR_LED              CTL_REG(0x0644)
0480 /* masks for controlling LEDs */
0481 #define LED1                (1 <<  8)
0482 #define LED2                (1 <<  9)
0483 #define LED_SW              (1 << 10)
0484 
0485 /* Seems to indicate that the configuration is over.
0486  */
0487 #define CR_AFTER_PNP            CTL_REG(0x0648)
0488 #define CR_ACK_TIME_80211       CTL_REG(0x0658)
0489 
0490 #define CR_RX_OFFSET            CTL_REG(0x065c)
0491 
0492 #define CR_BCN_LENGTH           CTL_REG(0x0664)
0493 #define CR_PHY_DELAY            CTL_REG(0x066C)
0494 #define CR_BCN_FIFO         CTL_REG(0x0670)
0495 #define CR_SNIFFER_ON           CTL_REG(0x0674)
0496 
0497 #define CR_ENCRYPTION_TYPE      CTL_REG(0x0678)
0498 #define NO_WEP              0
0499 #define WEP64               1
0500 #define WEP128              5
0501 #define WEP256              6
0502 #define ENC_SNIFFER         8
0503 
0504 #define CR_ZD1211_RETRY_MAX     CTL_REG(0x067C)
0505 
0506 #define CR_REG1             CTL_REG(0x0680)
0507 /* Setting the bit UNLOCK_PHY_REGS disallows the write access to physical
0508  * registers, so one could argue it is a LOCK bit. But calling it
0509  * LOCK_PHY_REGS makes it confusing.
0510  */
0511 #define UNLOCK_PHY_REGS         (1 << 7)
0512 
0513 #define CR_DEVICE_STATE         CTL_REG(0x0684)
0514 #define CR_UNDERRUN_CNT         CTL_REG(0x0688)
0515 
0516 #define CR_RX_FILTER            CTL_REG(0x068c)
0517 #define RX_FILTER_ASSOC_REQUEST     (1 <<  0)
0518 #define RX_FILTER_ASSOC_RESPONSE    (1 <<  1)
0519 #define RX_FILTER_REASSOC_REQUEST   (1 <<  2)
0520 #define RX_FILTER_REASSOC_RESPONSE  (1 <<  3)
0521 #define RX_FILTER_PROBE_REQUEST     (1 <<  4)
0522 #define RX_FILTER_PROBE_RESPONSE    (1 <<  5)
0523 /* bits 6 and 7 reserved */
0524 #define RX_FILTER_BEACON        (1 <<  8)
0525 #define RX_FILTER_ATIM          (1 <<  9)
0526 #define RX_FILTER_DISASSOC      (1 << 10)
0527 #define RX_FILTER_AUTH          (1 << 11)
0528 #define RX_FILTER_DEAUTH        (1 << 12)
0529 #define RX_FILTER_PSPOLL        (1 << 26)
0530 #define RX_FILTER_RTS           (1 << 27)
0531 #define RX_FILTER_CTS           (1 << 28)
0532 #define RX_FILTER_ACK           (1 << 29)
0533 #define RX_FILTER_CFEND         (1 << 30)
0534 #define RX_FILTER_CFACK         (1 << 31)
0535 
0536 /* Enable bits for all frames you are interested in. */
0537 #define STA_RX_FILTER   (RX_FILTER_ASSOC_REQUEST | RX_FILTER_ASSOC_RESPONSE | \
0538     RX_FILTER_REASSOC_REQUEST | RX_FILTER_REASSOC_RESPONSE | \
0539     RX_FILTER_PROBE_REQUEST | RX_FILTER_PROBE_RESPONSE | \
0540     (0x3 << 6) /* vendor driver sets these reserved bits */ | \
0541     RX_FILTER_BEACON | RX_FILTER_ATIM | RX_FILTER_DISASSOC | \
0542     RX_FILTER_AUTH | RX_FILTER_DEAUTH | \
0543     (0x7 << 13) /* vendor driver sets these reserved bits */ | \
0544     RX_FILTER_PSPOLL | RX_FILTER_ACK) /* 0x2400ffff */
0545 
0546 #define RX_FILTER_CTRL (RX_FILTER_RTS | RX_FILTER_CTS | \
0547     RX_FILTER_CFEND | RX_FILTER_CFACK)
0548 
0549 #define BCN_MODE_AP         0x1000000
0550 #define BCN_MODE_IBSS           0x2000000
0551 
0552 /* Monitor mode sets filter to 0xfffff */
0553 
0554 #define CR_ACK_TIMEOUT_EXT      CTL_REG(0x0690)
0555 #define CR_BCN_FIFO_SEMAPHORE       CTL_REG(0x0694)
0556 
0557 #define CR_IFS_VALUE            CTL_REG(0x0698)
0558 #define IFS_VALUE_DIFS_SH       0
0559 #define IFS_VALUE_EIFS_SH       12
0560 #define IFS_VALUE_SIFS_SH       24
0561 #define IFS_VALUE_DEFAULT       ((  50 << IFS_VALUE_DIFS_SH) | \
0562                      (1148 << IFS_VALUE_EIFS_SH) | \
0563                      (  10 << IFS_VALUE_SIFS_SH))
0564 
0565 #define CR_RX_TIME_OUT          CTL_REG(0x069C)
0566 #define CR_TOTAL_RX_FRM         CTL_REG(0x06A0)
0567 #define CR_CRC32_CNT            CTL_REG(0x06A4)
0568 #define CR_CRC16_CNT            CTL_REG(0x06A8)
0569 #define CR_DECRYPTION_ERR_UNI       CTL_REG(0x06AC)
0570 #define CR_RX_FIFO_OVERRUN      CTL_REG(0x06B0)
0571 
0572 #define CR_DECRYPTION_ERR_MUL       CTL_REG(0x06BC)
0573 
0574 #define CR_NAV_CNT          CTL_REG(0x06C4)
0575 #define CR_NAV_CCA          CTL_REG(0x06C8)
0576 #define CR_RETRY_CNT            CTL_REG(0x06CC)
0577 
0578 #define CR_READ_TCB_ADDR        CTL_REG(0x06E8)
0579 #define CR_READ_RFD_ADDR        CTL_REG(0x06EC)
0580 #define CR_CWMIN_CWMAX          CTL_REG(0x06F0)
0581 #define CR_TOTAL_TX_FRM         CTL_REG(0x06F4)
0582 
0583 /* CAM: Continuous Access Mode (power management) */
0584 #define CR_CAM_MODE         CTL_REG(0x0700)
0585 #define MODE_IBSS           0x0
0586 #define MODE_AP             0x1
0587 #define MODE_STA            0x2
0588 #define MODE_AP_WDS         0x3
0589 
0590 #define CR_CAM_ROLL_TB_LOW      CTL_REG(0x0704)
0591 #define CR_CAM_ROLL_TB_HIGH     CTL_REG(0x0708)
0592 #define CR_CAM_ADDRESS          CTL_REG(0x070C)
0593 #define CR_CAM_DATA         CTL_REG(0x0710)
0594 
0595 #define CR_ROMDIR           CTL_REG(0x0714)
0596 
0597 #define CR_DECRY_ERR_FLG_LOW        CTL_REG(0x0714)
0598 #define CR_DECRY_ERR_FLG_HIGH       CTL_REG(0x0718)
0599 
0600 #define CR_WEPKEY0          CTL_REG(0x0720)
0601 #define CR_WEPKEY1          CTL_REG(0x0724)
0602 #define CR_WEPKEY2          CTL_REG(0x0728)
0603 #define CR_WEPKEY3          CTL_REG(0x072C)
0604 #define CR_WEPKEY4          CTL_REG(0x0730)
0605 #define CR_WEPKEY5          CTL_REG(0x0734)
0606 #define CR_WEPKEY6          CTL_REG(0x0738)
0607 #define CR_WEPKEY7          CTL_REG(0x073C)
0608 #define CR_WEPKEY8          CTL_REG(0x0740)
0609 #define CR_WEPKEY9          CTL_REG(0x0744)
0610 #define CR_WEPKEY10         CTL_REG(0x0748)
0611 #define CR_WEPKEY11         CTL_REG(0x074C)
0612 #define CR_WEPKEY12         CTL_REG(0x0750)
0613 #define CR_WEPKEY13         CTL_REG(0x0754)
0614 #define CR_WEPKEY14         CTL_REG(0x0758)
0615 #define CR_WEPKEY15         CTL_REG(0x075c)
0616 #define CR_TKIP_MODE            CTL_REG(0x0760)
0617 
0618 #define CR_EEPROM_PROTECT0      CTL_REG(0x0758)
0619 #define CR_EEPROM_PROTECT1      CTL_REG(0x075C)
0620 
0621 #define CR_DBG_FIFO_RD          CTL_REG(0x0800)
0622 #define CR_DBG_SELECT           CTL_REG(0x0804)
0623 #define CR_FIFO_Length          CTL_REG(0x0808)
0624 
0625 
0626 #define CR_RSSI_MGC         CTL_REG(0x0810)
0627 
0628 #define CR_PON              CTL_REG(0x0818)
0629 #define CR_RX_ON            CTL_REG(0x081C)
0630 #define CR_TX_ON            CTL_REG(0x0820)
0631 #define CR_CHIP_EN          CTL_REG(0x0824)
0632 #define CR_LO_SW            CTL_REG(0x0828)
0633 #define CR_TXRX_SW          CTL_REG(0x082C)
0634 #define CR_S_MD             CTL_REG(0x0830)
0635 
0636 #define CR_USB_DEBUG_PORT       CTL_REG(0x0888)
0637 #define CR_ZD1211B_CWIN_MAX_MIN_AC0 CTL_REG(0x0b00)
0638 #define CR_ZD1211B_CWIN_MAX_MIN_AC1 CTL_REG(0x0b04)
0639 #define CR_ZD1211B_CWIN_MAX_MIN_AC2 CTL_REG(0x0b08)
0640 #define CR_ZD1211B_CWIN_MAX_MIN_AC3 CTL_REG(0x0b0c)
0641 #define CR_ZD1211B_AIFS_CTL1        CTL_REG(0x0b10)
0642 #define CR_ZD1211B_AIFS_CTL2        CTL_REG(0x0b14)
0643 #define CR_ZD1211B_TXOP         CTL_REG(0x0b20)
0644 #define CR_ZD1211B_RETRY_MAX        CTL_REG(0x0b28)
0645 
0646 /* Value for CR_ZD1211_RETRY_MAX & CR_ZD1211B_RETRY_MAX. Vendor driver uses 2,
0647  * we use 0. The first rate is tried (count+2), then all next rates are tried
0648  * twice, until 1 Mbits is tried. */
0649 #define ZD1211_RETRY_COUNT      0
0650 #define ZD1211B_RETRY_COUNT \
0651     (ZD1211_RETRY_COUNT <<  0)| \
0652     (ZD1211_RETRY_COUNT <<  8)| \
0653     (ZD1211_RETRY_COUNT << 16)| \
0654     (ZD1211_RETRY_COUNT << 24)
0655 
0656 /* Used to detect PLL lock */
0657 #define UW2453_INTR_REG         ((zd_addr_t)0x85c1)
0658 
0659 #define CWIN_SIZE           0x007f043f
0660 
0661 
0662 #define HWINT_ENABLED           \
0663     (INT_TX_COMPLETE_EN|        \
0664      INT_RX_COMPLETE_EN|        \
0665      INT_RETRY_FAIL_EN|     \
0666      INT_WAKEUP_EN|         \
0667      INT_CFG_NEXT_BCN_EN)
0668 
0669 #define HWINT_DISABLED          0
0670 
0671 #define E2P_PWR_INT_GUARD       8
0672 #define E2P_CHANNEL_COUNT       14
0673 
0674 /* If you compare this addresses with the ZYDAS orignal driver, please notify
0675  * that we use word mapping for the EEPROM.
0676  */
0677 
0678 /*
0679  * Upper 16 bit contains the regulatory domain.
0680  */
0681 #define E2P_SUBID       E2P_DATA(0x00)
0682 #define E2P_POD         E2P_DATA(0x02)
0683 #define E2P_MAC_ADDR_P1     E2P_DATA(0x04)
0684 #define E2P_MAC_ADDR_P2     E2P_DATA(0x06)
0685 #define E2P_PWR_CAL_VALUE1  E2P_DATA(0x08)
0686 #define E2P_PWR_CAL_VALUE2  E2P_DATA(0x0a)
0687 #define E2P_PWR_CAL_VALUE3  E2P_DATA(0x0c)
0688 #define E2P_PWR_CAL_VALUE4      E2P_DATA(0x0e)
0689 #define E2P_PWR_INT_VALUE1  E2P_DATA(0x10)
0690 #define E2P_PWR_INT_VALUE2  E2P_DATA(0x12)
0691 #define E2P_PWR_INT_VALUE3  E2P_DATA(0x14)
0692 #define E2P_PWR_INT_VALUE4  E2P_DATA(0x16)
0693 
0694 /* Contains a bit for each allowed channel. It gives for Europe (ETSI 0x30)
0695  * also only 11 channels. */
0696 #define E2P_ALLOWED_CHANNEL E2P_DATA(0x18)
0697 
0698 #define E2P_DEVICE_VER      E2P_DATA(0x20)
0699 #define E2P_PHY_REG     E2P_DATA(0x25)
0700 #define E2P_36M_CAL_VALUE1  E2P_DATA(0x28)
0701 #define E2P_36M_CAL_VALUE2      E2P_DATA(0x2a)
0702 #define E2P_36M_CAL_VALUE3      E2P_DATA(0x2c)
0703 #define E2P_36M_CAL_VALUE4  E2P_DATA(0x2e)
0704 #define E2P_11A_INT_VALUE1  E2P_DATA(0x30)
0705 #define E2P_11A_INT_VALUE2  E2P_DATA(0x32)
0706 #define E2P_11A_INT_VALUE3  E2P_DATA(0x34)
0707 #define E2P_11A_INT_VALUE4  E2P_DATA(0x36)
0708 #define E2P_48M_CAL_VALUE1  E2P_DATA(0x38)
0709 #define E2P_48M_CAL_VALUE2  E2P_DATA(0x3a)
0710 #define E2P_48M_CAL_VALUE3  E2P_DATA(0x3c)
0711 #define E2P_48M_CAL_VALUE4  E2P_DATA(0x3e)
0712 #define E2P_48M_INT_VALUE1  E2P_DATA(0x40)
0713 #define E2P_48M_INT_VALUE2  E2P_DATA(0x42)
0714 #define E2P_48M_INT_VALUE3  E2P_DATA(0x44)
0715 #define E2P_48M_INT_VALUE4  E2P_DATA(0x46)
0716 #define E2P_54M_CAL_VALUE1  E2P_DATA(0x48)  /* ??? */
0717 #define E2P_54M_CAL_VALUE2  E2P_DATA(0x4a)
0718 #define E2P_54M_CAL_VALUE3  E2P_DATA(0x4c)
0719 #define E2P_54M_CAL_VALUE4  E2P_DATA(0x4e)
0720 #define E2P_54M_INT_VALUE1  E2P_DATA(0x50)
0721 #define E2P_54M_INT_VALUE2  E2P_DATA(0x52)
0722 #define E2P_54M_INT_VALUE3  E2P_DATA(0x54)
0723 #define E2P_54M_INT_VALUE4  E2P_DATA(0x56)
0724 
0725 /* This word contains the base address of the FW_REG_ registers below */
0726 #define FWRAW_REGS_ADDR     FWRAW_DATA(0x1d)
0727 
0728 /* All 16 bit values, offset from the address in FWRAW_REGS_ADDR */
0729 enum {
0730     FW_REG_FIRMWARE_VER = 0,
0731     /* non-zero if USB high speed connection */
0732     FW_REG_USB_SPEED    = 1,
0733     FW_REG_FIX_TX_RATE  = 2,
0734     /* Seems to be able to control LEDs over the firmware */
0735     FW_REG_LED_LINK_STATUS  = 3,
0736     FW_REG_SOFT_RESET   = 4,
0737     FW_REG_FLASH_CHK    = 5,
0738 };
0739 
0740 /* Values for FW_LINK_STATUS */
0741 #define FW_LINK_OFF     0x0
0742 #define FW_LINK_TX      0x1
0743 /* 0x2 - link led on? */
0744 
0745 enum {
0746     /* indices for ofdm_cal_values */
0747     OFDM_36M_INDEX = 0,
0748     OFDM_48M_INDEX = 1,
0749     OFDM_54M_INDEX = 2,
0750 };
0751 
0752 struct zd_chip {
0753     struct zd_usb usb;
0754     struct zd_rf rf;
0755     struct mutex mutex;
0756     /* Base address of FW_REG_ registers */
0757     zd_addr_t fw_regs_base;
0758     /* EepSetPoint in the vendor driver */
0759     u8 pwr_cal_values[E2P_CHANNEL_COUNT];
0760     /* integration values in the vendor driver */
0761     u8 pwr_int_values[E2P_CHANNEL_COUNT];
0762     /* SetPointOFDM in the vendor driver */
0763     u8 ofdm_cal_values[3][E2P_CHANNEL_COUNT];
0764     u16 link_led;
0765     unsigned int pa_type:4,
0766         patch_cck_gain:1, patch_cr157:1, patch_6m_band_edge:1,
0767         new_phy_layout:1, al2230s_bit:1,
0768         supports_tx_led:1;
0769 };
0770 
0771 static inline struct zd_chip *zd_usb_to_chip(struct zd_usb *usb)
0772 {
0773     return container_of(usb, struct zd_chip, usb);
0774 }
0775 
0776 static inline struct zd_chip *zd_rf_to_chip(struct zd_rf *rf)
0777 {
0778     return container_of(rf, struct zd_chip, rf);
0779 }
0780 
0781 #define zd_chip_dev(chip) (&(chip)->usb.intf->dev)
0782 
0783 void zd_chip_init(struct zd_chip *chip,
0784              struct ieee80211_hw *hw,
0785              struct usb_interface *intf);
0786 void zd_chip_clear(struct zd_chip *chip);
0787 int zd_chip_read_mac_addr_fw(struct zd_chip *chip, u8 *addr);
0788 int zd_chip_init_hw(struct zd_chip *chip);
0789 int zd_chip_reset(struct zd_chip *chip);
0790 
0791 static inline int zd_chip_is_zd1211b(struct zd_chip *chip)
0792 {
0793     return chip->usb.is_zd1211b;
0794 }
0795 
0796 static inline int zd_ioread16v_locked(struct zd_chip *chip, u16 *values,
0797                                   const zd_addr_t *addresses,
0798                       unsigned int count)
0799 {
0800     ZD_ASSERT(mutex_is_locked(&chip->mutex));
0801     return zd_usb_ioread16v(&chip->usb, values, addresses, count);
0802 }
0803 
0804 static inline int zd_ioread16_locked(struct zd_chip *chip, u16 *value,
0805                                  const zd_addr_t addr)
0806 {
0807     ZD_ASSERT(mutex_is_locked(&chip->mutex));
0808     return zd_usb_ioread16(&chip->usb, value, addr);
0809 }
0810 
0811 int zd_ioread32v_locked(struct zd_chip *chip, u32 *values,
0812                     const zd_addr_t *addresses, unsigned int count);
0813 
0814 static inline int zd_ioread32_locked(struct zd_chip *chip, u32 *value,
0815                                  const zd_addr_t addr)
0816 {
0817     return zd_ioread32v_locked(chip, value, &addr, 1);
0818 }
0819 
0820 static inline int zd_iowrite16_locked(struct zd_chip *chip, u16 value,
0821                                   zd_addr_t addr)
0822 {
0823     struct zd_ioreq16 ioreq;
0824 
0825     ZD_ASSERT(mutex_is_locked(&chip->mutex));
0826     ioreq.addr = addr;
0827     ioreq.value = value;
0828 
0829     return zd_usb_iowrite16v(&chip->usb, &ioreq, 1);
0830 }
0831 
0832 int zd_iowrite16a_locked(struct zd_chip *chip,
0833                          const struct zd_ioreq16 *ioreqs, unsigned int count);
0834 
0835 int _zd_iowrite32v_locked(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs,
0836               unsigned int count);
0837 
0838 static inline int zd_iowrite32_locked(struct zd_chip *chip, u32 value,
0839                                   zd_addr_t addr)
0840 {
0841     struct zd_ioreq32 ioreq;
0842 
0843     ioreq.addr = addr;
0844     ioreq.value = value;
0845 
0846     return _zd_iowrite32v_locked(chip, &ioreq, 1);
0847 }
0848 
0849 int zd_iowrite32a_locked(struct zd_chip *chip,
0850                      const struct zd_ioreq32 *ioreqs, unsigned int count);
0851 
0852 static inline int zd_rfwrite_locked(struct zd_chip *chip, u32 value, u8 bits)
0853 {
0854     ZD_ASSERT(mutex_is_locked(&chip->mutex));
0855     return zd_usb_rfwrite(&chip->usb, value, bits);
0856 }
0857 
0858 int zd_rfwrite_cr_locked(struct zd_chip *chip, u32 value);
0859 
0860 int zd_rfwritev_locked(struct zd_chip *chip,
0861                    const u32* values, unsigned int count, u8 bits);
0862 int zd_rfwritev_cr_locked(struct zd_chip *chip,
0863                       const u32* values, unsigned int count);
0864 
0865 /* Locking functions for reading and writing registers.
0866  * The different parameters are intentional.
0867  */
0868 int zd_ioread16(struct zd_chip *chip, zd_addr_t addr, u16 *value);
0869 int zd_iowrite16(struct zd_chip *chip, zd_addr_t addr, u16 value);
0870 int zd_ioread32(struct zd_chip *chip, zd_addr_t addr, u32 *value);
0871 int zd_iowrite32(struct zd_chip *chip, zd_addr_t addr, u32 value);
0872 int zd_ioread32v(struct zd_chip *chip, const zd_addr_t *addresses,
0873               u32 *values, unsigned int count);
0874 int zd_iowrite32a(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs,
0875                unsigned int count);
0876 
0877 int zd_chip_set_channel(struct zd_chip *chip, u8 channel);
0878 static inline u8 _zd_chip_get_channel(struct zd_chip *chip)
0879 {
0880     return chip->rf.channel;
0881 }
0882 u8  zd_chip_get_channel(struct zd_chip *chip);
0883 int zd_read_regdomain(struct zd_chip *chip, u8 *regdomain);
0884 int zd_write_mac_addr(struct zd_chip *chip, const u8 *mac_addr);
0885 int zd_write_bssid(struct zd_chip *chip, const u8 *bssid);
0886 int zd_chip_switch_radio_on(struct zd_chip *chip);
0887 int zd_chip_switch_radio_off(struct zd_chip *chip);
0888 int zd_chip_enable_int(struct zd_chip *chip);
0889 void zd_chip_disable_int(struct zd_chip *chip);
0890 int zd_chip_enable_rxtx(struct zd_chip *chip);
0891 void zd_chip_disable_rxtx(struct zd_chip *chip);
0892 int zd_chip_enable_hwint(struct zd_chip *chip);
0893 int zd_chip_disable_hwint(struct zd_chip *chip);
0894 int zd_chip_generic_patch_6m_band(struct zd_chip *chip, int channel);
0895 int zd_chip_set_rts_cts_rate_locked(struct zd_chip *chip, int preamble);
0896 
0897 static inline int zd_get_encryption_type(struct zd_chip *chip, u32 *type)
0898 {
0899     return zd_ioread32(chip, CR_ENCRYPTION_TYPE, type);
0900 }
0901 
0902 static inline int zd_set_encryption_type(struct zd_chip *chip, u32 type)
0903 {
0904     return zd_iowrite32(chip, CR_ENCRYPTION_TYPE, type);
0905 }
0906 
0907 static inline int zd_chip_get_basic_rates(struct zd_chip *chip, u16 *cr_rates)
0908 {
0909     return zd_ioread16(chip, CR_BASIC_RATE_TBL, cr_rates);
0910 }
0911 
0912 int zd_chip_set_basic_rates(struct zd_chip *chip, u16 cr_rates);
0913 
0914 int zd_chip_lock_phy_regs(struct zd_chip *chip);
0915 int zd_chip_unlock_phy_regs(struct zd_chip *chip);
0916 
0917 enum led_status {
0918     ZD_LED_OFF = 0,
0919     ZD_LED_SCANNING = 1,
0920     ZD_LED_ASSOCIATED = 2,
0921 };
0922 
0923 int zd_chip_control_leds(struct zd_chip *chip, enum led_status status);
0924 
0925 int zd_set_beacon_interval(struct zd_chip *chip, u16 interval, u8 dtim_period,
0926                int type);
0927 
0928 static inline int zd_get_beacon_interval(struct zd_chip *chip, u32 *interval)
0929 {
0930     return zd_ioread32(chip, CR_BCN_INTERVAL, interval);
0931 }
0932 
0933 struct rx_status;
0934 
0935 u8 zd_rx_rate(const void *rx_frame, const struct rx_status *status);
0936 
0937 struct zd_mc_hash {
0938     u32 low;
0939     u32 high;
0940 };
0941 
0942 static inline void zd_mc_clear(struct zd_mc_hash *hash)
0943 {
0944     hash->low = 0;
0945     /* The interfaces must always received broadcasts.
0946      * The hash of the broadcast address ff:ff:ff:ff:ff:ff is 63.
0947      */
0948     hash->high = 0x80000000;
0949 }
0950 
0951 static inline void zd_mc_add_all(struct zd_mc_hash *hash)
0952 {
0953     hash->low = hash->high = 0xffffffff;
0954 }
0955 
0956 static inline void zd_mc_add_addr(struct zd_mc_hash *hash, u8 *addr)
0957 {
0958     unsigned int i = addr[5] >> 2;
0959     if (i < 32) {
0960         hash->low |= 1 << i;
0961     } else {
0962         hash->high |= 1 << (i-32);
0963     }
0964 }
0965 
0966 int zd_chip_set_multicast_hash(struct zd_chip *chip,
0967                            struct zd_mc_hash *hash);
0968 
0969 u64 zd_chip_get_tsf(struct zd_chip *chip);
0970 
0971 #endif /* _ZD_CHIP_H */
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