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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /* ZD1211 USB-WLAN driver for Linux
0003  *
0004  * Copyright (C) 2005-2007 Ulrich Kunitz <kune@deine-taler.de>
0005  * Copyright (C) 2006-2007 Daniel Drake <dsd@gentoo.org>
0006  */
0007 
0008 /* This file implements all the hardware specific functions for the ZD1211
0009  * and ZD1211B chips. Support for the ZD1211B was possible after Timothy
0010  * Legge sent me a ZD1211B device. Thank you Tim. -- Uli
0011  */
0012 
0013 #include <linux/kernel.h>
0014 #include <linux/errno.h>
0015 #include <linux/slab.h>
0016 
0017 #include "zd_def.h"
0018 #include "zd_chip.h"
0019 #include "zd_mac.h"
0020 #include "zd_rf.h"
0021 
0022 void zd_chip_init(struct zd_chip *chip,
0023              struct ieee80211_hw *hw,
0024          struct usb_interface *intf)
0025 {
0026     memset(chip, 0, sizeof(*chip));
0027     mutex_init(&chip->mutex);
0028     zd_usb_init(&chip->usb, hw, intf);
0029     zd_rf_init(&chip->rf);
0030 }
0031 
0032 void zd_chip_clear(struct zd_chip *chip)
0033 {
0034     ZD_ASSERT(!mutex_is_locked(&chip->mutex));
0035     zd_usb_clear(&chip->usb);
0036     zd_rf_clear(&chip->rf);
0037     mutex_destroy(&chip->mutex);
0038     ZD_MEMCLEAR(chip, sizeof(*chip));
0039 }
0040 
0041 static int scnprint_mac_oui(struct zd_chip *chip, char *buffer, size_t size)
0042 {
0043     u8 *addr = zd_mac_get_perm_addr(zd_chip_to_mac(chip));
0044     return scnprintf(buffer, size, "%3phD", addr);
0045 }
0046 
0047 /* Prints an identifier line, which will support debugging. */
0048 static int scnprint_id(struct zd_chip *chip, char *buffer, size_t size)
0049 {
0050     int i = 0;
0051 
0052     i = scnprintf(buffer, size, "zd1211%s chip ",
0053               zd_chip_is_zd1211b(chip) ? "b" : "");
0054     i += zd_usb_scnprint_id(&chip->usb, buffer+i, size-i);
0055     i += scnprintf(buffer+i, size-i, " ");
0056     i += scnprint_mac_oui(chip, buffer+i, size-i);
0057     i += scnprintf(buffer+i, size-i, " ");
0058     i += zd_rf_scnprint_id(&chip->rf, buffer+i, size-i);
0059     i += scnprintf(buffer+i, size-i, " pa%1x %c%c%c%c%c", chip->pa_type,
0060         chip->patch_cck_gain ? 'g' : '-',
0061         chip->patch_cr157 ? '7' : '-',
0062         chip->patch_6m_band_edge ? '6' : '-',
0063         chip->new_phy_layout ? 'N' : '-',
0064         chip->al2230s_bit ? 'S' : '-');
0065     return i;
0066 }
0067 
0068 static void print_id(struct zd_chip *chip)
0069 {
0070     char buffer[80];
0071 
0072     scnprint_id(chip, buffer, sizeof(buffer));
0073     buffer[sizeof(buffer)-1] = 0;
0074     dev_info(zd_chip_dev(chip), "%s\n", buffer);
0075 }
0076 
0077 static zd_addr_t inc_addr(zd_addr_t addr)
0078 {
0079     u16 a = (u16)addr;
0080     /* Control registers use byte addressing, but everything else uses word
0081      * addressing. */
0082     if ((a & 0xf000) == CR_START)
0083         a += 2;
0084     else
0085         a += 1;
0086     return (zd_addr_t)a;
0087 }
0088 
0089 /* Read a variable number of 32-bit values. Parameter count is not allowed to
0090  * exceed USB_MAX_IOREAD32_COUNT.
0091  */
0092 int zd_ioread32v_locked(struct zd_chip *chip, u32 *values, const zd_addr_t *addr,
0093          unsigned int count)
0094 {
0095     int r;
0096     int i;
0097     zd_addr_t a16[USB_MAX_IOREAD32_COUNT * 2];
0098     u16 v16[USB_MAX_IOREAD32_COUNT * 2];
0099     unsigned int count16;
0100 
0101     if (count > USB_MAX_IOREAD32_COUNT)
0102         return -EINVAL;
0103 
0104     /* Use stack for values and addresses. */
0105     count16 = 2 * count;
0106     BUG_ON(count16 * sizeof(zd_addr_t) > sizeof(a16));
0107     BUG_ON(count16 * sizeof(u16) > sizeof(v16));
0108 
0109     for (i = 0; i < count; i++) {
0110         int j = 2*i;
0111         /* We read the high word always first. */
0112         a16[j] = inc_addr(addr[i]);
0113         a16[j+1] = addr[i];
0114     }
0115 
0116     r = zd_ioread16v_locked(chip, v16, a16, count16);
0117     if (r) {
0118         dev_dbg_f(zd_chip_dev(chip),
0119               "error: %s. Error number %d\n", __func__, r);
0120         return r;
0121     }
0122 
0123     for (i = 0; i < count; i++) {
0124         int j = 2*i;
0125         values[i] = (v16[j] << 16) | v16[j+1];
0126     }
0127 
0128     return 0;
0129 }
0130 
0131 static int _zd_iowrite32v_async_locked(struct zd_chip *chip,
0132                        const struct zd_ioreq32 *ioreqs,
0133                        unsigned int count)
0134 {
0135     int i, j, r;
0136     struct zd_ioreq16 ioreqs16[USB_MAX_IOWRITE32_COUNT * 2];
0137     unsigned int count16;
0138 
0139     /* Use stack for values and addresses. */
0140 
0141     ZD_ASSERT(mutex_is_locked(&chip->mutex));
0142 
0143     if (count == 0)
0144         return 0;
0145     if (count > USB_MAX_IOWRITE32_COUNT)
0146         return -EINVAL;
0147 
0148     count16 = 2 * count;
0149     BUG_ON(count16 * sizeof(struct zd_ioreq16) > sizeof(ioreqs16));
0150 
0151     for (i = 0; i < count; i++) {
0152         j = 2*i;
0153         /* We write the high word always first. */
0154         ioreqs16[j].value   = ioreqs[i].value >> 16;
0155         ioreqs16[j].addr    = inc_addr(ioreqs[i].addr);
0156         ioreqs16[j+1].value = ioreqs[i].value;
0157         ioreqs16[j+1].addr  = ioreqs[i].addr;
0158     }
0159 
0160     r = zd_usb_iowrite16v_async(&chip->usb, ioreqs16, count16);
0161 #ifdef DEBUG
0162     if (r) {
0163         dev_dbg_f(zd_chip_dev(chip),
0164               "error %d in zd_usb_write16v\n", r);
0165     }
0166 #endif /* DEBUG */
0167     return r;
0168 }
0169 
0170 int _zd_iowrite32v_locked(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs,
0171               unsigned int count)
0172 {
0173     int r;
0174 
0175     zd_usb_iowrite16v_async_start(&chip->usb);
0176     r = _zd_iowrite32v_async_locked(chip, ioreqs, count);
0177     if (r) {
0178         zd_usb_iowrite16v_async_end(&chip->usb, 0);
0179         return r;
0180     }
0181     return zd_usb_iowrite16v_async_end(&chip->usb, 50 /* ms */);
0182 }
0183 
0184 int zd_iowrite16a_locked(struct zd_chip *chip,
0185                   const struct zd_ioreq16 *ioreqs, unsigned int count)
0186 {
0187     int r;
0188     unsigned int i, j, t, max;
0189 
0190     ZD_ASSERT(mutex_is_locked(&chip->mutex));
0191     zd_usb_iowrite16v_async_start(&chip->usb);
0192 
0193     for (i = 0; i < count; i += j + t) {
0194         t = 0;
0195         max = count-i;
0196         if (max > USB_MAX_IOWRITE16_COUNT)
0197             max = USB_MAX_IOWRITE16_COUNT;
0198         for (j = 0; j < max; j++) {
0199             if (!ioreqs[i+j].addr) {
0200                 t = 1;
0201                 break;
0202             }
0203         }
0204 
0205         r = zd_usb_iowrite16v_async(&chip->usb, &ioreqs[i], j);
0206         if (r) {
0207             zd_usb_iowrite16v_async_end(&chip->usb, 0);
0208             dev_dbg_f(zd_chip_dev(chip),
0209                   "error zd_usb_iowrite16v. Error number %d\n",
0210                   r);
0211             return r;
0212         }
0213     }
0214 
0215     return zd_usb_iowrite16v_async_end(&chip->usb, 50 /* ms */);
0216 }
0217 
0218 /* Writes a variable number of 32 bit registers. The functions will split
0219  * that in several USB requests. A split can be forced by inserting an IO
0220  * request with an zero address field.
0221  */
0222 int zd_iowrite32a_locked(struct zd_chip *chip,
0223               const struct zd_ioreq32 *ioreqs, unsigned int count)
0224 {
0225     int r;
0226     unsigned int i, j, t, max;
0227 
0228     zd_usb_iowrite16v_async_start(&chip->usb);
0229 
0230     for (i = 0; i < count; i += j + t) {
0231         t = 0;
0232         max = count-i;
0233         if (max > USB_MAX_IOWRITE32_COUNT)
0234             max = USB_MAX_IOWRITE32_COUNT;
0235         for (j = 0; j < max; j++) {
0236             if (!ioreqs[i+j].addr) {
0237                 t = 1;
0238                 break;
0239             }
0240         }
0241 
0242         r = _zd_iowrite32v_async_locked(chip, &ioreqs[i], j);
0243         if (r) {
0244             zd_usb_iowrite16v_async_end(&chip->usb, 0);
0245             dev_dbg_f(zd_chip_dev(chip),
0246                 "error _%s. Error number %d\n", __func__,
0247                 r);
0248             return r;
0249         }
0250     }
0251 
0252     return zd_usb_iowrite16v_async_end(&chip->usb, 50 /* ms */);
0253 }
0254 
0255 int zd_ioread16(struct zd_chip *chip, zd_addr_t addr, u16 *value)
0256 {
0257     int r;
0258 
0259     mutex_lock(&chip->mutex);
0260     r = zd_ioread16_locked(chip, value, addr);
0261     mutex_unlock(&chip->mutex);
0262     return r;
0263 }
0264 
0265 int zd_ioread32(struct zd_chip *chip, zd_addr_t addr, u32 *value)
0266 {
0267     int r;
0268 
0269     mutex_lock(&chip->mutex);
0270     r = zd_ioread32_locked(chip, value, addr);
0271     mutex_unlock(&chip->mutex);
0272     return r;
0273 }
0274 
0275 int zd_iowrite16(struct zd_chip *chip, zd_addr_t addr, u16 value)
0276 {
0277     int r;
0278 
0279     mutex_lock(&chip->mutex);
0280     r = zd_iowrite16_locked(chip, value, addr);
0281     mutex_unlock(&chip->mutex);
0282     return r;
0283 }
0284 
0285 int zd_iowrite32(struct zd_chip *chip, zd_addr_t addr, u32 value)
0286 {
0287     int r;
0288 
0289     mutex_lock(&chip->mutex);
0290     r = zd_iowrite32_locked(chip, value, addr);
0291     mutex_unlock(&chip->mutex);
0292     return r;
0293 }
0294 
0295 int zd_ioread32v(struct zd_chip *chip, const zd_addr_t *addresses,
0296               u32 *values, unsigned int count)
0297 {
0298     int r;
0299 
0300     mutex_lock(&chip->mutex);
0301     r = zd_ioread32v_locked(chip, values, addresses, count);
0302     mutex_unlock(&chip->mutex);
0303     return r;
0304 }
0305 
0306 int zd_iowrite32a(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs,
0307               unsigned int count)
0308 {
0309     int r;
0310 
0311     mutex_lock(&chip->mutex);
0312     r = zd_iowrite32a_locked(chip, ioreqs, count);
0313     mutex_unlock(&chip->mutex);
0314     return r;
0315 }
0316 
0317 static int read_pod(struct zd_chip *chip, u8 *rf_type)
0318 {
0319     int r;
0320     u32 value;
0321 
0322     ZD_ASSERT(mutex_is_locked(&chip->mutex));
0323     r = zd_ioread32_locked(chip, &value, E2P_POD);
0324     if (r)
0325         goto error;
0326     dev_dbg_f(zd_chip_dev(chip), "E2P_POD %#010x\n", value);
0327 
0328     /* FIXME: AL2230 handling (Bit 7 in POD) */
0329     *rf_type = value & 0x0f;
0330     chip->pa_type = (value >> 16) & 0x0f;
0331     chip->patch_cck_gain = (value >> 8) & 0x1;
0332     chip->patch_cr157 = (value >> 13) & 0x1;
0333     chip->patch_6m_band_edge = (value >> 21) & 0x1;
0334     chip->new_phy_layout = (value >> 31) & 0x1;
0335     chip->al2230s_bit = (value >> 7) & 0x1;
0336     chip->link_led = ((value >> 4) & 1) ? LED1 : LED2;
0337     chip->supports_tx_led = 1;
0338     if (value & (1 << 24)) { /* LED scenario */
0339         if (value & (1 << 29))
0340             chip->supports_tx_led = 0;
0341     }
0342 
0343     dev_dbg_f(zd_chip_dev(chip),
0344         "RF %s %#01x PA type %#01x patch CCK %d patch CR157 %d "
0345         "patch 6M %d new PHY %d link LED%d tx led %d\n",
0346         zd_rf_name(*rf_type), *rf_type,
0347         chip->pa_type, chip->patch_cck_gain,
0348         chip->patch_cr157, chip->patch_6m_band_edge,
0349         chip->new_phy_layout,
0350         chip->link_led == LED1 ? 1 : 2,
0351         chip->supports_tx_led);
0352     return 0;
0353 error:
0354     *rf_type = 0;
0355     chip->pa_type = 0;
0356     chip->patch_cck_gain = 0;
0357     chip->patch_cr157 = 0;
0358     chip->patch_6m_band_edge = 0;
0359     chip->new_phy_layout = 0;
0360     return r;
0361 }
0362 
0363 static int zd_write_mac_addr_common(struct zd_chip *chip, const u8 *mac_addr,
0364                     const struct zd_ioreq32 *in_reqs,
0365                     const char *type)
0366 {
0367     int r;
0368     struct zd_ioreq32 reqs[2] = {in_reqs[0], in_reqs[1]};
0369 
0370     if (mac_addr) {
0371         reqs[0].value = (mac_addr[3] << 24)
0372                   | (mac_addr[2] << 16)
0373                   | (mac_addr[1] <<  8)
0374                   |  mac_addr[0];
0375         reqs[1].value = (mac_addr[5] <<  8)
0376                   |  mac_addr[4];
0377         dev_dbg_f(zd_chip_dev(chip), "%s addr %pM\n", type, mac_addr);
0378     } else {
0379         dev_dbg_f(zd_chip_dev(chip), "set NULL %s\n", type);
0380     }
0381 
0382     mutex_lock(&chip->mutex);
0383     r = zd_iowrite32a_locked(chip, reqs, ARRAY_SIZE(reqs));
0384     mutex_unlock(&chip->mutex);
0385     return r;
0386 }
0387 
0388 /* MAC address: if custom mac addresses are to be used CR_MAC_ADDR_P1 and
0389  *              CR_MAC_ADDR_P2 must be overwritten
0390  */
0391 int zd_write_mac_addr(struct zd_chip *chip, const u8 *mac_addr)
0392 {
0393     static const struct zd_ioreq32 reqs[2] = {
0394         [0] = { .addr = CR_MAC_ADDR_P1 },
0395         [1] = { .addr = CR_MAC_ADDR_P2 },
0396     };
0397 
0398     return zd_write_mac_addr_common(chip, mac_addr, reqs, "mac");
0399 }
0400 
0401 int zd_write_bssid(struct zd_chip *chip, const u8 *bssid)
0402 {
0403     static const struct zd_ioreq32 reqs[2] = {
0404         [0] = { .addr = CR_BSSID_P1 },
0405         [1] = { .addr = CR_BSSID_P2 },
0406     };
0407 
0408     return zd_write_mac_addr_common(chip, bssid, reqs, "bssid");
0409 }
0410 
0411 int zd_read_regdomain(struct zd_chip *chip, u8 *regdomain)
0412 {
0413     int r;
0414     u32 value;
0415 
0416     mutex_lock(&chip->mutex);
0417     r = zd_ioread32_locked(chip, &value, E2P_SUBID);
0418     mutex_unlock(&chip->mutex);
0419     if (r)
0420         return r;
0421 
0422     *regdomain = value >> 16;
0423     dev_dbg_f(zd_chip_dev(chip), "regdomain: %#04x\n", *regdomain);
0424 
0425     return 0;
0426 }
0427 
0428 static int read_values(struct zd_chip *chip, u8 *values, size_t count,
0429                    zd_addr_t e2p_addr, u32 guard)
0430 {
0431     int r;
0432     int i;
0433     u32 v;
0434 
0435     ZD_ASSERT(mutex_is_locked(&chip->mutex));
0436     for (i = 0;;) {
0437         r = zd_ioread32_locked(chip, &v,
0438                            (zd_addr_t)((u16)e2p_addr+i/2));
0439         if (r)
0440             return r;
0441         v -= guard;
0442         if (i+4 < count) {
0443             values[i++] = v;
0444             values[i++] = v >>  8;
0445             values[i++] = v >> 16;
0446             values[i++] = v >> 24;
0447             continue;
0448         }
0449         for (;i < count; i++)
0450             values[i] = v >> (8*(i%3));
0451         return 0;
0452     }
0453 }
0454 
0455 static int read_pwr_cal_values(struct zd_chip *chip)
0456 {
0457     return read_values(chip, chip->pwr_cal_values,
0458                 E2P_CHANNEL_COUNT, E2P_PWR_CAL_VALUE1,
0459             0);
0460 }
0461 
0462 static int read_pwr_int_values(struct zd_chip *chip)
0463 {
0464     return read_values(chip, chip->pwr_int_values,
0465                 E2P_CHANNEL_COUNT, E2P_PWR_INT_VALUE1,
0466             E2P_PWR_INT_GUARD);
0467 }
0468 
0469 static int read_ofdm_cal_values(struct zd_chip *chip)
0470 {
0471     int r;
0472     int i;
0473     static const zd_addr_t addresses[] = {
0474         E2P_36M_CAL_VALUE1,
0475         E2P_48M_CAL_VALUE1,
0476         E2P_54M_CAL_VALUE1,
0477     };
0478 
0479     for (i = 0; i < 3; i++) {
0480         r = read_values(chip, chip->ofdm_cal_values[i],
0481                 E2P_CHANNEL_COUNT, addresses[i], 0);
0482         if (r)
0483             return r;
0484     }
0485     return 0;
0486 }
0487 
0488 static int read_cal_int_tables(struct zd_chip *chip)
0489 {
0490     int r;
0491 
0492     r = read_pwr_cal_values(chip);
0493     if (r)
0494         return r;
0495     r = read_pwr_int_values(chip);
0496     if (r)
0497         return r;
0498     r = read_ofdm_cal_values(chip);
0499     if (r)
0500         return r;
0501     return 0;
0502 }
0503 
0504 /* phy means physical registers */
0505 int zd_chip_lock_phy_regs(struct zd_chip *chip)
0506 {
0507     int r;
0508     u32 tmp;
0509 
0510     ZD_ASSERT(mutex_is_locked(&chip->mutex));
0511     r = zd_ioread32_locked(chip, &tmp, CR_REG1);
0512     if (r) {
0513         dev_err(zd_chip_dev(chip), "error ioread32(CR_REG1): %d\n", r);
0514         return r;
0515     }
0516 
0517     tmp &= ~UNLOCK_PHY_REGS;
0518 
0519     r = zd_iowrite32_locked(chip, tmp, CR_REG1);
0520     if (r)
0521         dev_err(zd_chip_dev(chip), "error iowrite32(CR_REG1): %d\n", r);
0522     return r;
0523 }
0524 
0525 int zd_chip_unlock_phy_regs(struct zd_chip *chip)
0526 {
0527     int r;
0528     u32 tmp;
0529 
0530     ZD_ASSERT(mutex_is_locked(&chip->mutex));
0531     r = zd_ioread32_locked(chip, &tmp, CR_REG1);
0532     if (r) {
0533         dev_err(zd_chip_dev(chip),
0534             "error ioread32(CR_REG1): %d\n", r);
0535         return r;
0536     }
0537 
0538     tmp |= UNLOCK_PHY_REGS;
0539 
0540     r = zd_iowrite32_locked(chip, tmp, CR_REG1);
0541     if (r)
0542         dev_err(zd_chip_dev(chip), "error iowrite32(CR_REG1): %d\n", r);
0543     return r;
0544 }
0545 
0546 /* ZD_CR157 can be optionally patched by the EEPROM for original ZD1211 */
0547 static int patch_cr157(struct zd_chip *chip)
0548 {
0549     int r;
0550     u16 value;
0551 
0552     if (!chip->patch_cr157)
0553         return 0;
0554 
0555     r = zd_ioread16_locked(chip, &value, E2P_PHY_REG);
0556     if (r)
0557         return r;
0558 
0559     dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value >> 8);
0560     return zd_iowrite32_locked(chip, value >> 8, ZD_CR157);
0561 }
0562 
0563 /*
0564  * 6M band edge can be optionally overwritten for certain RF's
0565  * Vendor driver says: for FCC regulation, enabled per HWFeature 6M band edge
0566  * bit (for AL2230, AL2230S)
0567  */
0568 static int patch_6m_band_edge(struct zd_chip *chip, u8 channel)
0569 {
0570     ZD_ASSERT(mutex_is_locked(&chip->mutex));
0571     if (!chip->patch_6m_band_edge)
0572         return 0;
0573 
0574     return zd_rf_patch_6m_band_edge(&chip->rf, channel);
0575 }
0576 
0577 /* Generic implementation of 6M band edge patching, used by most RFs via
0578  * zd_rf_generic_patch_6m() */
0579 int zd_chip_generic_patch_6m_band(struct zd_chip *chip, int channel)
0580 {
0581     struct zd_ioreq16 ioreqs[] = {
0582         { ZD_CR128, 0x14 }, { ZD_CR129, 0x12 }, { ZD_CR130, 0x10 },
0583         { ZD_CR47,  0x1e },
0584     };
0585 
0586     /* FIXME: Channel 11 is not the edge for all regulatory domains. */
0587     if (channel == 1 || channel == 11)
0588         ioreqs[0].value = 0x12;
0589 
0590     dev_dbg_f(zd_chip_dev(chip), "patching for channel %d\n", channel);
0591     return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
0592 }
0593 
0594 static int zd1211_hw_reset_phy(struct zd_chip *chip)
0595 {
0596     static const struct zd_ioreq16 ioreqs[] = {
0597         { ZD_CR0,   0x0a }, { ZD_CR1,   0x06 }, { ZD_CR2,   0x26 },
0598         { ZD_CR3,   0x38 }, { ZD_CR4,   0x80 }, { ZD_CR9,   0xa0 },
0599         { ZD_CR10,  0x81 }, { ZD_CR11,  0x00 }, { ZD_CR12,  0x7f },
0600         { ZD_CR13,  0x8c }, { ZD_CR14,  0x80 }, { ZD_CR15,  0x3d },
0601         { ZD_CR16,  0x20 }, { ZD_CR17,  0x1e }, { ZD_CR18,  0x0a },
0602         { ZD_CR19,  0x48 }, { ZD_CR20,  0x0c }, { ZD_CR21,  0x0c },
0603         { ZD_CR22,  0x23 }, { ZD_CR23,  0x90 }, { ZD_CR24,  0x14 },
0604         { ZD_CR25,  0x40 }, { ZD_CR26,  0x10 }, { ZD_CR27,  0x19 },
0605         { ZD_CR28,  0x7f }, { ZD_CR29,  0x80 }, { ZD_CR30,  0x4b },
0606         { ZD_CR31,  0x60 }, { ZD_CR32,  0x43 }, { ZD_CR33,  0x08 },
0607         { ZD_CR34,  0x06 }, { ZD_CR35,  0x0a }, { ZD_CR36,  0x00 },
0608         { ZD_CR37,  0x00 }, { ZD_CR38,  0x38 }, { ZD_CR39,  0x0c },
0609         { ZD_CR40,  0x84 }, { ZD_CR41,  0x2a }, { ZD_CR42,  0x80 },
0610         { ZD_CR43,  0x10 }, { ZD_CR44,  0x12 }, { ZD_CR46,  0xff },
0611         { ZD_CR47,  0x1E }, { ZD_CR48,  0x26 }, { ZD_CR49,  0x5b },
0612         { ZD_CR64,  0xd0 }, { ZD_CR65,  0x04 }, { ZD_CR66,  0x58 },
0613         { ZD_CR67,  0xc9 }, { ZD_CR68,  0x88 }, { ZD_CR69,  0x41 },
0614         { ZD_CR70,  0x23 }, { ZD_CR71,  0x10 }, { ZD_CR72,  0xff },
0615         { ZD_CR73,  0x32 }, { ZD_CR74,  0x30 }, { ZD_CR75,  0x65 },
0616         { ZD_CR76,  0x41 }, { ZD_CR77,  0x1b }, { ZD_CR78,  0x30 },
0617         { ZD_CR79,  0x68 }, { ZD_CR80,  0x64 }, { ZD_CR81,  0x64 },
0618         { ZD_CR82,  0x00 }, { ZD_CR83,  0x00 }, { ZD_CR84,  0x00 },
0619         { ZD_CR85,  0x02 }, { ZD_CR86,  0x00 }, { ZD_CR87,  0x00 },
0620         { ZD_CR88,  0xff }, { ZD_CR89,  0xfc }, { ZD_CR90,  0x00 },
0621         { ZD_CR91,  0x00 }, { ZD_CR92,  0x00 }, { ZD_CR93,  0x08 },
0622         { ZD_CR94,  0x00 }, { ZD_CR95,  0x00 }, { ZD_CR96,  0xff },
0623         { ZD_CR97,  0xe7 }, { ZD_CR98,  0x00 }, { ZD_CR99,  0x00 },
0624         { ZD_CR100, 0x00 }, { ZD_CR101, 0xae }, { ZD_CR102, 0x02 },
0625         { ZD_CR103, 0x00 }, { ZD_CR104, 0x03 }, { ZD_CR105, 0x65 },
0626         { ZD_CR106, 0x04 }, { ZD_CR107, 0x00 }, { ZD_CR108, 0x0a },
0627         { ZD_CR109, 0xaa }, { ZD_CR110, 0xaa }, { ZD_CR111, 0x25 },
0628         { ZD_CR112, 0x25 }, { ZD_CR113, 0x00 }, { ZD_CR119, 0x1e },
0629         { ZD_CR125, 0x90 }, { ZD_CR126, 0x00 }, { ZD_CR127, 0x00 },
0630         { },
0631         { ZD_CR5,   0x00 }, { ZD_CR6,   0x00 }, { ZD_CR7,   0x00 },
0632         { ZD_CR8,   0x00 }, { ZD_CR9,   0x20 }, { ZD_CR12,  0xf0 },
0633         { ZD_CR20,  0x0e }, { ZD_CR21,  0x0e }, { ZD_CR27,  0x10 },
0634         { ZD_CR44,  0x33 }, { ZD_CR47,  0x1E }, { ZD_CR83,  0x24 },
0635         { ZD_CR84,  0x04 }, { ZD_CR85,  0x00 }, { ZD_CR86,  0x0C },
0636         { ZD_CR87,  0x12 }, { ZD_CR88,  0x0C }, { ZD_CR89,  0x00 },
0637         { ZD_CR90,  0x10 }, { ZD_CR91,  0x08 }, { ZD_CR93,  0x00 },
0638         { ZD_CR94,  0x01 }, { ZD_CR95,  0x00 }, { ZD_CR96,  0x50 },
0639         { ZD_CR97,  0x37 }, { ZD_CR98,  0x35 }, { ZD_CR101, 0x13 },
0640         { ZD_CR102, 0x27 }, { ZD_CR103, 0x27 }, { ZD_CR104, 0x18 },
0641         { ZD_CR105, 0x12 }, { ZD_CR109, 0x27 }, { ZD_CR110, 0x27 },
0642         { ZD_CR111, 0x27 }, { ZD_CR112, 0x27 }, { ZD_CR113, 0x27 },
0643         { ZD_CR114, 0x27 }, { ZD_CR115, 0x26 }, { ZD_CR116, 0x24 },
0644         { ZD_CR117, 0xfc }, { ZD_CR118, 0xfa }, { ZD_CR120, 0x4f },
0645         { ZD_CR125, 0xaa }, { ZD_CR127, 0x03 }, { ZD_CR128, 0x14 },
0646         { ZD_CR129, 0x12 }, { ZD_CR130, 0x10 }, { ZD_CR131, 0x0C },
0647         { ZD_CR136, 0xdf }, { ZD_CR137, 0x40 }, { ZD_CR138, 0xa0 },
0648         { ZD_CR139, 0xb0 }, { ZD_CR140, 0x99 }, { ZD_CR141, 0x82 },
0649         { ZD_CR142, 0x54 }, { ZD_CR143, 0x1c }, { ZD_CR144, 0x6c },
0650         { ZD_CR147, 0x07 }, { ZD_CR148, 0x4c }, { ZD_CR149, 0x50 },
0651         { ZD_CR150, 0x0e }, { ZD_CR151, 0x18 }, { ZD_CR160, 0xfe },
0652         { ZD_CR161, 0xee }, { ZD_CR162, 0xaa }, { ZD_CR163, 0xfa },
0653         { ZD_CR164, 0xfa }, { ZD_CR165, 0xea }, { ZD_CR166, 0xbe },
0654         { ZD_CR167, 0xbe }, { ZD_CR168, 0x6a }, { ZD_CR169, 0xba },
0655         { ZD_CR170, 0xba }, { ZD_CR171, 0xba },
0656         /* Note: ZD_CR204 must lead the ZD_CR203 */
0657         { ZD_CR204, 0x7d },
0658         { },
0659         { ZD_CR203, 0x30 },
0660     };
0661 
0662     int r, t;
0663 
0664     dev_dbg_f(zd_chip_dev(chip), "\n");
0665 
0666     r = zd_chip_lock_phy_regs(chip);
0667     if (r)
0668         goto out;
0669 
0670     r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
0671     if (r)
0672         goto unlock;
0673 
0674     r = patch_cr157(chip);
0675 unlock:
0676     t = zd_chip_unlock_phy_regs(chip);
0677     if (t && !r)
0678         r = t;
0679 out:
0680     return r;
0681 }
0682 
0683 static int zd1211b_hw_reset_phy(struct zd_chip *chip)
0684 {
0685     static const struct zd_ioreq16 ioreqs[] = {
0686         { ZD_CR0,   0x14 }, { ZD_CR1,   0x06 }, { ZD_CR2,   0x26 },
0687         { ZD_CR3,   0x38 }, { ZD_CR4,   0x80 }, { ZD_CR9,   0xe0 },
0688         { ZD_CR10,  0x81 },
0689         /* power control { { ZD_CR11,  1 << 6 }, */
0690         { ZD_CR11,  0x00 },
0691         { ZD_CR12,  0xf0 }, { ZD_CR13,  0x8c }, { ZD_CR14,  0x80 },
0692         { ZD_CR15,  0x3d }, { ZD_CR16,  0x20 }, { ZD_CR17,  0x1e },
0693         { ZD_CR18,  0x0a }, { ZD_CR19,  0x48 },
0694         { ZD_CR20,  0x10 }, /* Org:0x0E, ComTrend:RalLink AP */
0695         { ZD_CR21,  0x0e }, { ZD_CR22,  0x23 }, { ZD_CR23,  0x90 },
0696         { ZD_CR24,  0x14 }, { ZD_CR25,  0x40 }, { ZD_CR26,  0x10 },
0697         { ZD_CR27,  0x10 }, { ZD_CR28,  0x7f }, { ZD_CR29,  0x80 },
0698         { ZD_CR30,  0x4b }, /* ASIC/FWT, no jointly decoder */
0699         { ZD_CR31,  0x60 }, { ZD_CR32,  0x43 }, { ZD_CR33,  0x08 },
0700         { ZD_CR34,  0x06 }, { ZD_CR35,  0x0a }, { ZD_CR36,  0x00 },
0701         { ZD_CR37,  0x00 }, { ZD_CR38,  0x38 }, { ZD_CR39,  0x0c },
0702         { ZD_CR40,  0x84 }, { ZD_CR41,  0x2a }, { ZD_CR42,  0x80 },
0703         { ZD_CR43,  0x10 }, { ZD_CR44,  0x33 }, { ZD_CR46,  0xff },
0704         { ZD_CR47,  0x1E }, { ZD_CR48,  0x26 }, { ZD_CR49,  0x5b },
0705         { ZD_CR64,  0xd0 }, { ZD_CR65,  0x04 }, { ZD_CR66,  0x58 },
0706         { ZD_CR67,  0xc9 }, { ZD_CR68,  0x88 }, { ZD_CR69,  0x41 },
0707         { ZD_CR70,  0x23 }, { ZD_CR71,  0x10 }, { ZD_CR72,  0xff },
0708         { ZD_CR73,  0x32 }, { ZD_CR74,  0x30 }, { ZD_CR75,  0x65 },
0709         { ZD_CR76,  0x41 }, { ZD_CR77,  0x1b }, { ZD_CR78,  0x30 },
0710         { ZD_CR79,  0xf0 }, { ZD_CR80,  0x64 }, { ZD_CR81,  0x64 },
0711         { ZD_CR82,  0x00 }, { ZD_CR83,  0x24 }, { ZD_CR84,  0x04 },
0712         { ZD_CR85,  0x00 }, { ZD_CR86,  0x0c }, { ZD_CR87,  0x12 },
0713         { ZD_CR88,  0x0c }, { ZD_CR89,  0x00 }, { ZD_CR90,  0x58 },
0714         { ZD_CR91,  0x04 }, { ZD_CR92,  0x00 }, { ZD_CR93,  0x00 },
0715         { ZD_CR94,  0x01 },
0716         { ZD_CR95,  0x20 }, /* ZD1211B */
0717         { ZD_CR96,  0x50 }, { ZD_CR97,  0x37 }, { ZD_CR98,  0x35 },
0718         { ZD_CR99,  0x00 }, { ZD_CR100, 0x01 }, { ZD_CR101, 0x13 },
0719         { ZD_CR102, 0x27 }, { ZD_CR103, 0x27 }, { ZD_CR104, 0x18 },
0720         { ZD_CR105, 0x12 }, { ZD_CR106, 0x04 }, { ZD_CR107, 0x00 },
0721         { ZD_CR108, 0x0a }, { ZD_CR109, 0x27 }, { ZD_CR110, 0x27 },
0722         { ZD_CR111, 0x27 }, { ZD_CR112, 0x27 }, { ZD_CR113, 0x27 },
0723         { ZD_CR114, 0x27 }, { ZD_CR115, 0x26 }, { ZD_CR116, 0x24 },
0724         { ZD_CR117, 0xfc }, { ZD_CR118, 0xfa }, { ZD_CR119, 0x1e },
0725         { ZD_CR125, 0x90 }, { ZD_CR126, 0x00 }, { ZD_CR127, 0x00 },
0726         { ZD_CR128, 0x14 }, { ZD_CR129, 0x12 }, { ZD_CR130, 0x10 },
0727         { ZD_CR131, 0x0c }, { ZD_CR136, 0xdf }, { ZD_CR137, 0xa0 },
0728         { ZD_CR138, 0xa8 }, { ZD_CR139, 0xb4 }, { ZD_CR140, 0x98 },
0729         { ZD_CR141, 0x82 }, { ZD_CR142, 0x53 }, { ZD_CR143, 0x1c },
0730         { ZD_CR144, 0x6c }, { ZD_CR147, 0x07 }, { ZD_CR148, 0x40 },
0731         { ZD_CR149, 0x40 }, /* Org:0x50 ComTrend:RalLink AP */
0732         { ZD_CR150, 0x14 }, /* Org:0x0E ComTrend:RalLink AP */
0733         { ZD_CR151, 0x18 }, { ZD_CR159, 0x70 }, { ZD_CR160, 0xfe },
0734         { ZD_CR161, 0xee }, { ZD_CR162, 0xaa }, { ZD_CR163, 0xfa },
0735         { ZD_CR164, 0xfa }, { ZD_CR165, 0xea }, { ZD_CR166, 0xbe },
0736         { ZD_CR167, 0xbe }, { ZD_CR168, 0x6a }, { ZD_CR169, 0xba },
0737         { ZD_CR170, 0xba }, { ZD_CR171, 0xba },
0738         /* Note: ZD_CR204 must lead the ZD_CR203 */
0739         { ZD_CR204, 0x7d },
0740         {},
0741         { ZD_CR203, 0x30 },
0742     };
0743 
0744     int r, t;
0745 
0746     dev_dbg_f(zd_chip_dev(chip), "\n");
0747 
0748     r = zd_chip_lock_phy_regs(chip);
0749     if (r)
0750         goto out;
0751 
0752     r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
0753     t = zd_chip_unlock_phy_regs(chip);
0754     if (t && !r)
0755         r = t;
0756 out:
0757     return r;
0758 }
0759 
0760 static int hw_reset_phy(struct zd_chip *chip)
0761 {
0762     return zd_chip_is_zd1211b(chip) ? zd1211b_hw_reset_phy(chip) :
0763                           zd1211_hw_reset_phy(chip);
0764 }
0765 
0766 static int zd1211_hw_init_hmac(struct zd_chip *chip)
0767 {
0768     static const struct zd_ioreq32 ioreqs[] = {
0769         { CR_ZD1211_RETRY_MAX,      ZD1211_RETRY_COUNT },
0770         { CR_RX_THRESHOLD,      0x000c0640 },
0771     };
0772 
0773     dev_dbg_f(zd_chip_dev(chip), "\n");
0774     ZD_ASSERT(mutex_is_locked(&chip->mutex));
0775     return zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
0776 }
0777 
0778 static int zd1211b_hw_init_hmac(struct zd_chip *chip)
0779 {
0780     static const struct zd_ioreq32 ioreqs[] = {
0781         { CR_ZD1211B_RETRY_MAX,     ZD1211B_RETRY_COUNT },
0782         { CR_ZD1211B_CWIN_MAX_MIN_AC0,  0x007f003f },
0783         { CR_ZD1211B_CWIN_MAX_MIN_AC1,  0x007f003f },
0784         { CR_ZD1211B_CWIN_MAX_MIN_AC2,  0x003f001f },
0785         { CR_ZD1211B_CWIN_MAX_MIN_AC3,  0x001f000f },
0786         { CR_ZD1211B_AIFS_CTL1,     0x00280028 },
0787         { CR_ZD1211B_AIFS_CTL2,     0x008C003C },
0788         { CR_ZD1211B_TXOP,      0x01800824 },
0789         { CR_RX_THRESHOLD,      0x000c0eff, },
0790     };
0791 
0792     dev_dbg_f(zd_chip_dev(chip), "\n");
0793     ZD_ASSERT(mutex_is_locked(&chip->mutex));
0794     return zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
0795 }
0796 
0797 static int hw_init_hmac(struct zd_chip *chip)
0798 {
0799     int r;
0800     static const struct zd_ioreq32 ioreqs[] = {
0801         { CR_ACK_TIMEOUT_EXT,       0x20 },
0802         { CR_ADDA_MBIAS_WARMTIME,   0x30000808 },
0803         { CR_SNIFFER_ON,        0 },
0804         { CR_RX_FILTER,         STA_RX_FILTER },
0805         { CR_GROUP_HASH_P1,     0x00 },
0806         { CR_GROUP_HASH_P2,     0x80000000 },
0807         { CR_REG1,          0xa4 },
0808         { CR_ADDA_PWR_DWN,      0x7f },
0809         { CR_BCN_PLCP_CFG,      0x00f00401 },
0810         { CR_PHY_DELAY,         0x00 },
0811         { CR_ACK_TIMEOUT_EXT,       0x80 },
0812         { CR_ADDA_PWR_DWN,      0x00 },
0813         { CR_ACK_TIME_80211,        0x100 },
0814         { CR_RX_PE_DELAY,       0x70 },
0815         { CR_PS_CTRL,           0x10000000 },
0816         { CR_RTS_CTS_RATE,      0x02030203 },
0817         { CR_AFTER_PNP,         0x1 },
0818         { CR_WEP_PROTECT,       0x114 },
0819         { CR_IFS_VALUE,         IFS_VALUE_DEFAULT },
0820         { CR_CAM_MODE,          MODE_AP_WDS},
0821     };
0822 
0823     ZD_ASSERT(mutex_is_locked(&chip->mutex));
0824     r = zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
0825     if (r)
0826         return r;
0827 
0828     return zd_chip_is_zd1211b(chip) ?
0829         zd1211b_hw_init_hmac(chip) : zd1211_hw_init_hmac(chip);
0830 }
0831 
0832 struct aw_pt_bi {
0833     u32 atim_wnd_period;
0834     u32 pre_tbtt;
0835     u32 beacon_interval;
0836 };
0837 
0838 static int get_aw_pt_bi(struct zd_chip *chip, struct aw_pt_bi *s)
0839 {
0840     int r;
0841     static const zd_addr_t aw_pt_bi_addr[] =
0842         { CR_ATIM_WND_PERIOD, CR_PRE_TBTT, CR_BCN_INTERVAL };
0843     u32 values[3];
0844 
0845     r = zd_ioread32v_locked(chip, values, (const zd_addr_t *)aw_pt_bi_addr,
0846                  ARRAY_SIZE(aw_pt_bi_addr));
0847     if (r) {
0848         memset(s, 0, sizeof(*s));
0849         return r;
0850     }
0851 
0852     s->atim_wnd_period = values[0];
0853     s->pre_tbtt = values[1];
0854     s->beacon_interval = values[2];
0855     return 0;
0856 }
0857 
0858 static int set_aw_pt_bi(struct zd_chip *chip, struct aw_pt_bi *s)
0859 {
0860     struct zd_ioreq32 reqs[3];
0861     u16 b_interval = s->beacon_interval & 0xffff;
0862 
0863     if (b_interval <= 5)
0864         b_interval = 5;
0865     if (s->pre_tbtt < 4 || s->pre_tbtt >= b_interval)
0866         s->pre_tbtt = b_interval - 1;
0867     if (s->atim_wnd_period >= s->pre_tbtt)
0868         s->atim_wnd_period = s->pre_tbtt - 1;
0869 
0870     reqs[0].addr = CR_ATIM_WND_PERIOD;
0871     reqs[0].value = s->atim_wnd_period;
0872     reqs[1].addr = CR_PRE_TBTT;
0873     reqs[1].value = s->pre_tbtt;
0874     reqs[2].addr = CR_BCN_INTERVAL;
0875     reqs[2].value = (s->beacon_interval & ~0xffff) | b_interval;
0876 
0877     return zd_iowrite32a_locked(chip, reqs, ARRAY_SIZE(reqs));
0878 }
0879 
0880 
0881 static int set_beacon_interval(struct zd_chip *chip, u16 interval,
0882                    u8 dtim_period, int type)
0883 {
0884     int r;
0885     struct aw_pt_bi s;
0886     u32 b_interval, mode_flag;
0887 
0888     ZD_ASSERT(mutex_is_locked(&chip->mutex));
0889 
0890     if (interval > 0) {
0891         switch (type) {
0892         case NL80211_IFTYPE_ADHOC:
0893         case NL80211_IFTYPE_MESH_POINT:
0894             mode_flag = BCN_MODE_IBSS;
0895             break;
0896         case NL80211_IFTYPE_AP:
0897             mode_flag = BCN_MODE_AP;
0898             break;
0899         default:
0900             mode_flag = 0;
0901             break;
0902         }
0903     } else {
0904         dtim_period = 0;
0905         mode_flag = 0;
0906     }
0907 
0908     b_interval = mode_flag | (dtim_period << 16) | interval;
0909 
0910     r = zd_iowrite32_locked(chip, b_interval, CR_BCN_INTERVAL);
0911     if (r)
0912         return r;
0913     r = get_aw_pt_bi(chip, &s);
0914     if (r)
0915         return r;
0916     return set_aw_pt_bi(chip, &s);
0917 }
0918 
0919 int zd_set_beacon_interval(struct zd_chip *chip, u16 interval, u8 dtim_period,
0920                int type)
0921 {
0922     int r;
0923 
0924     mutex_lock(&chip->mutex);
0925     r = set_beacon_interval(chip, interval, dtim_period, type);
0926     mutex_unlock(&chip->mutex);
0927     return r;
0928 }
0929 
0930 static int hw_init(struct zd_chip *chip)
0931 {
0932     int r;
0933 
0934     dev_dbg_f(zd_chip_dev(chip), "\n");
0935     ZD_ASSERT(mutex_is_locked(&chip->mutex));
0936     r = hw_reset_phy(chip);
0937     if (r)
0938         return r;
0939 
0940     r = hw_init_hmac(chip);
0941     if (r)
0942         return r;
0943 
0944     return set_beacon_interval(chip, 100, 0, NL80211_IFTYPE_UNSPECIFIED);
0945 }
0946 
0947 static zd_addr_t fw_reg_addr(struct zd_chip *chip, u16 offset)
0948 {
0949     return (zd_addr_t)((u16)chip->fw_regs_base + offset);
0950 }
0951 
0952 #ifdef DEBUG
0953 static int dump_cr(struct zd_chip *chip, const zd_addr_t addr,
0954                const char *addr_string)
0955 {
0956     int r;
0957     u32 value;
0958 
0959     r = zd_ioread32_locked(chip, &value, addr);
0960     if (r) {
0961         dev_dbg_f(zd_chip_dev(chip),
0962             "error reading %s. Error number %d\n", addr_string, r);
0963         return r;
0964     }
0965 
0966     dev_dbg_f(zd_chip_dev(chip), "%s %#010x\n",
0967         addr_string, (unsigned int)value);
0968     return 0;
0969 }
0970 
0971 static int test_init(struct zd_chip *chip)
0972 {
0973     int r;
0974 
0975     r = dump_cr(chip, CR_AFTER_PNP, "CR_AFTER_PNP");
0976     if (r)
0977         return r;
0978     r = dump_cr(chip, CR_GPI_EN, "CR_GPI_EN");
0979     if (r)
0980         return r;
0981     return dump_cr(chip, CR_INTERRUPT, "CR_INTERRUPT");
0982 }
0983 
0984 static void dump_fw_registers(struct zd_chip *chip)
0985 {
0986     const zd_addr_t addr[4] = {
0987         fw_reg_addr(chip, FW_REG_FIRMWARE_VER),
0988         fw_reg_addr(chip, FW_REG_USB_SPEED),
0989         fw_reg_addr(chip, FW_REG_FIX_TX_RATE),
0990         fw_reg_addr(chip, FW_REG_LED_LINK_STATUS),
0991     };
0992 
0993     int r;
0994     u16 values[4];
0995 
0996     r = zd_ioread16v_locked(chip, values, (const zd_addr_t*)addr,
0997                  ARRAY_SIZE(addr));
0998     if (r) {
0999         dev_dbg_f(zd_chip_dev(chip), "error %d zd_ioread16v_locked\n",
1000              r);
1001         return;
1002     }
1003 
1004     dev_dbg_f(zd_chip_dev(chip), "FW_FIRMWARE_VER %#06hx\n", values[0]);
1005     dev_dbg_f(zd_chip_dev(chip), "FW_USB_SPEED %#06hx\n", values[1]);
1006     dev_dbg_f(zd_chip_dev(chip), "FW_FIX_TX_RATE %#06hx\n", values[2]);
1007     dev_dbg_f(zd_chip_dev(chip), "FW_LINK_STATUS %#06hx\n", values[3]);
1008 }
1009 #endif /* DEBUG */
1010 
1011 static int print_fw_version(struct zd_chip *chip)
1012 {
1013     struct wiphy *wiphy = zd_chip_to_mac(chip)->hw->wiphy;
1014     int r;
1015     u16 version;
1016 
1017     r = zd_ioread16_locked(chip, &version,
1018         fw_reg_addr(chip, FW_REG_FIRMWARE_VER));
1019     if (r)
1020         return r;
1021 
1022     dev_info(zd_chip_dev(chip),"firmware version %04hx\n", version);
1023 
1024     snprintf(wiphy->fw_version, sizeof(wiphy->fw_version),
1025             "%04hx", version);
1026 
1027     return 0;
1028 }
1029 
1030 static int set_mandatory_rates(struct zd_chip *chip, int gmode)
1031 {
1032     u32 rates;
1033     ZD_ASSERT(mutex_is_locked(&chip->mutex));
1034     /* This sets the mandatory rates, which only depend from the standard
1035      * that the device is supporting. Until further notice we should try
1036      * to support 802.11g also for full speed USB.
1037      */
1038     if (!gmode)
1039         rates = CR_RATE_1M|CR_RATE_2M|CR_RATE_5_5M|CR_RATE_11M;
1040     else
1041         rates = CR_RATE_1M|CR_RATE_2M|CR_RATE_5_5M|CR_RATE_11M|
1042             CR_RATE_6M|CR_RATE_12M|CR_RATE_24M;
1043 
1044     return zd_iowrite32_locked(chip, rates, CR_MANDATORY_RATE_TBL);
1045 }
1046 
1047 int zd_chip_set_rts_cts_rate_locked(struct zd_chip *chip,
1048                     int preamble)
1049 {
1050     u32 value = 0;
1051 
1052     dev_dbg_f(zd_chip_dev(chip), "preamble=%x\n", preamble);
1053     value |= preamble << RTSCTS_SH_RTS_PMB_TYPE;
1054     value |= preamble << RTSCTS_SH_CTS_PMB_TYPE;
1055 
1056     /* We always send 11M RTS/self-CTS messages, like the vendor driver. */
1057     value |= ZD_PURE_RATE(ZD_CCK_RATE_11M) << RTSCTS_SH_RTS_RATE;
1058     value |= ZD_RX_CCK << RTSCTS_SH_RTS_MOD_TYPE;
1059     value |= ZD_PURE_RATE(ZD_CCK_RATE_11M) << RTSCTS_SH_CTS_RATE;
1060     value |= ZD_RX_CCK << RTSCTS_SH_CTS_MOD_TYPE;
1061 
1062     return zd_iowrite32_locked(chip, value, CR_RTS_CTS_RATE);
1063 }
1064 
1065 int zd_chip_enable_hwint(struct zd_chip *chip)
1066 {
1067     int r;
1068 
1069     mutex_lock(&chip->mutex);
1070     r = zd_iowrite32_locked(chip, HWINT_ENABLED, CR_INTERRUPT);
1071     mutex_unlock(&chip->mutex);
1072     return r;
1073 }
1074 
1075 static int disable_hwint(struct zd_chip *chip)
1076 {
1077     return zd_iowrite32_locked(chip, HWINT_DISABLED, CR_INTERRUPT);
1078 }
1079 
1080 int zd_chip_disable_hwint(struct zd_chip *chip)
1081 {
1082     int r;
1083 
1084     mutex_lock(&chip->mutex);
1085     r = disable_hwint(chip);
1086     mutex_unlock(&chip->mutex);
1087     return r;
1088 }
1089 
1090 static int read_fw_regs_offset(struct zd_chip *chip)
1091 {
1092     int r;
1093 
1094     ZD_ASSERT(mutex_is_locked(&chip->mutex));
1095     r = zd_ioread16_locked(chip, (u16*)&chip->fw_regs_base,
1096                        FWRAW_REGS_ADDR);
1097     if (r)
1098         return r;
1099     dev_dbg_f(zd_chip_dev(chip), "fw_regs_base: %#06hx\n",
1100           (u16)chip->fw_regs_base);
1101 
1102     return 0;
1103 }
1104 
1105 /* Read mac address using pre-firmware interface */
1106 int zd_chip_read_mac_addr_fw(struct zd_chip *chip, u8 *addr)
1107 {
1108     dev_dbg_f(zd_chip_dev(chip), "\n");
1109     return zd_usb_read_fw(&chip->usb, E2P_MAC_ADDR_P1, addr,
1110         ETH_ALEN);
1111 }
1112 
1113 int zd_chip_init_hw(struct zd_chip *chip)
1114 {
1115     int r;
1116     u8 rf_type;
1117 
1118     dev_dbg_f(zd_chip_dev(chip), "\n");
1119 
1120     mutex_lock(&chip->mutex);
1121 
1122 #ifdef DEBUG
1123     r = test_init(chip);
1124     if (r)
1125         goto out;
1126 #endif
1127     r = zd_iowrite32_locked(chip, 1, CR_AFTER_PNP);
1128     if (r)
1129         goto out;
1130 
1131     r = read_fw_regs_offset(chip);
1132     if (r)
1133         goto out;
1134 
1135     /* GPI is always disabled, also in the other driver.
1136      */
1137     r = zd_iowrite32_locked(chip, 0, CR_GPI_EN);
1138     if (r)
1139         goto out;
1140     r = zd_iowrite32_locked(chip, CWIN_SIZE, CR_CWMIN_CWMAX);
1141     if (r)
1142         goto out;
1143     /* Currently we support IEEE 802.11g for full and high speed USB.
1144      * It might be discussed, whether we should support pure b mode for
1145      * full speed USB.
1146      */
1147     r = set_mandatory_rates(chip, 1);
1148     if (r)
1149         goto out;
1150     /* Disabling interrupts is certainly a smart thing here.
1151      */
1152     r = disable_hwint(chip);
1153     if (r)
1154         goto out;
1155     r = read_pod(chip, &rf_type);
1156     if (r)
1157         goto out;
1158     r = hw_init(chip);
1159     if (r)
1160         goto out;
1161     r = zd_rf_init_hw(&chip->rf, rf_type);
1162     if (r)
1163         goto out;
1164 
1165     r = print_fw_version(chip);
1166     if (r)
1167         goto out;
1168 
1169 #ifdef DEBUG
1170     dump_fw_registers(chip);
1171     r = test_init(chip);
1172     if (r)
1173         goto out;
1174 #endif /* DEBUG */
1175 
1176     r = read_cal_int_tables(chip);
1177     if (r)
1178         goto out;
1179 
1180     print_id(chip);
1181 out:
1182     mutex_unlock(&chip->mutex);
1183     return r;
1184 }
1185 
1186 static int update_pwr_int(struct zd_chip *chip, u8 channel)
1187 {
1188     u8 value = chip->pwr_int_values[channel - 1];
1189     return zd_iowrite16_locked(chip, value, ZD_CR31);
1190 }
1191 
1192 static int update_pwr_cal(struct zd_chip *chip, u8 channel)
1193 {
1194     u8 value = chip->pwr_cal_values[channel-1];
1195     return zd_iowrite16_locked(chip, value, ZD_CR68);
1196 }
1197 
1198 static int update_ofdm_cal(struct zd_chip *chip, u8 channel)
1199 {
1200     struct zd_ioreq16 ioreqs[3];
1201 
1202     ioreqs[0].addr = ZD_CR67;
1203     ioreqs[0].value = chip->ofdm_cal_values[OFDM_36M_INDEX][channel-1];
1204     ioreqs[1].addr = ZD_CR66;
1205     ioreqs[1].value = chip->ofdm_cal_values[OFDM_48M_INDEX][channel-1];
1206     ioreqs[2].addr = ZD_CR65;
1207     ioreqs[2].value = chip->ofdm_cal_values[OFDM_54M_INDEX][channel-1];
1208 
1209     return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1210 }
1211 
1212 static int update_channel_integration_and_calibration(struct zd_chip *chip,
1213                                                   u8 channel)
1214 {
1215     int r;
1216 
1217     if (!zd_rf_should_update_pwr_int(&chip->rf))
1218         return 0;
1219 
1220     r = update_pwr_int(chip, channel);
1221     if (r)
1222         return r;
1223     if (zd_chip_is_zd1211b(chip)) {
1224         static const struct zd_ioreq16 ioreqs[] = {
1225             { ZD_CR69, 0x28 },
1226             {},
1227             { ZD_CR69, 0x2a },
1228         };
1229 
1230         r = update_ofdm_cal(chip, channel);
1231         if (r)
1232             return r;
1233         r = update_pwr_cal(chip, channel);
1234         if (r)
1235             return r;
1236         r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1237         if (r)
1238             return r;
1239     }
1240 
1241     return 0;
1242 }
1243 
1244 /* The CCK baseband gain can be optionally patched by the EEPROM */
1245 static int patch_cck_gain(struct zd_chip *chip)
1246 {
1247     int r;
1248     u32 value;
1249 
1250     if (!chip->patch_cck_gain || !zd_rf_should_patch_cck_gain(&chip->rf))
1251         return 0;
1252 
1253     ZD_ASSERT(mutex_is_locked(&chip->mutex));
1254     r = zd_ioread32_locked(chip, &value, E2P_PHY_REG);
1255     if (r)
1256         return r;
1257     dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value & 0xff);
1258     return zd_iowrite16_locked(chip, value & 0xff, ZD_CR47);
1259 }
1260 
1261 int zd_chip_set_channel(struct zd_chip *chip, u8 channel)
1262 {
1263     int r, t;
1264 
1265     mutex_lock(&chip->mutex);
1266     r = zd_chip_lock_phy_regs(chip);
1267     if (r)
1268         goto out;
1269     r = zd_rf_set_channel(&chip->rf, channel);
1270     if (r)
1271         goto unlock;
1272     r = update_channel_integration_and_calibration(chip, channel);
1273     if (r)
1274         goto unlock;
1275     r = patch_cck_gain(chip);
1276     if (r)
1277         goto unlock;
1278     r = patch_6m_band_edge(chip, channel);
1279     if (r)
1280         goto unlock;
1281     r = zd_iowrite32_locked(chip, 0, CR_CONFIG_PHILIPS);
1282 unlock:
1283     t = zd_chip_unlock_phy_regs(chip);
1284     if (t && !r)
1285         r = t;
1286 out:
1287     mutex_unlock(&chip->mutex);
1288     return r;
1289 }
1290 
1291 u8 zd_chip_get_channel(struct zd_chip *chip)
1292 {
1293     u8 channel;
1294 
1295     mutex_lock(&chip->mutex);
1296     channel = chip->rf.channel;
1297     mutex_unlock(&chip->mutex);
1298     return channel;
1299 }
1300 
1301 int zd_chip_control_leds(struct zd_chip *chip, enum led_status status)
1302 {
1303     const zd_addr_t a[] = {
1304         fw_reg_addr(chip, FW_REG_LED_LINK_STATUS),
1305         CR_LED,
1306     };
1307 
1308     int r;
1309     u16 v[ARRAY_SIZE(a)];
1310     struct zd_ioreq16 ioreqs[ARRAY_SIZE(a)] = {
1311         [0] = { fw_reg_addr(chip, FW_REG_LED_LINK_STATUS) },
1312         [1] = { CR_LED },
1313     };
1314     u16 other_led;
1315 
1316     mutex_lock(&chip->mutex);
1317     r = zd_ioread16v_locked(chip, v, (const zd_addr_t *)a, ARRAY_SIZE(a));
1318     if (r)
1319         goto out;
1320 
1321     other_led = chip->link_led == LED1 ? LED2 : LED1;
1322 
1323     switch (status) {
1324     case ZD_LED_OFF:
1325         ioreqs[0].value = FW_LINK_OFF;
1326         ioreqs[1].value = v[1] & ~(LED1|LED2);
1327         break;
1328     case ZD_LED_SCANNING:
1329         ioreqs[0].value = FW_LINK_OFF;
1330         ioreqs[1].value = v[1] & ~other_led;
1331         if ((u32)ktime_get_seconds() % 3 == 0) {
1332             ioreqs[1].value &= ~chip->link_led;
1333         } else {
1334             ioreqs[1].value |= chip->link_led;
1335         }
1336         break;
1337     case ZD_LED_ASSOCIATED:
1338         ioreqs[0].value = FW_LINK_TX;
1339         ioreqs[1].value = v[1] & ~other_led;
1340         ioreqs[1].value |= chip->link_led;
1341         break;
1342     default:
1343         r = -EINVAL;
1344         goto out;
1345     }
1346 
1347     if (v[0] != ioreqs[0].value || v[1] != ioreqs[1].value) {
1348         r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1349         if (r)
1350             goto out;
1351     }
1352     r = 0;
1353 out:
1354     mutex_unlock(&chip->mutex);
1355     return r;
1356 }
1357 
1358 int zd_chip_set_basic_rates(struct zd_chip *chip, u16 cr_rates)
1359 {
1360     int r;
1361 
1362     if (cr_rates & ~(CR_RATES_80211B|CR_RATES_80211G))
1363         return -EINVAL;
1364 
1365     mutex_lock(&chip->mutex);
1366     r = zd_iowrite32_locked(chip, cr_rates, CR_BASIC_RATE_TBL);
1367     mutex_unlock(&chip->mutex);
1368     return r;
1369 }
1370 
1371 static inline u8 zd_rate_from_ofdm_plcp_header(const void *rx_frame)
1372 {
1373     return ZD_OFDM | zd_ofdm_plcp_header_rate(rx_frame);
1374 }
1375 
1376 /**
1377  * zd_rx_rate - report zd-rate
1378  * @rx_frame: received frame
1379  * @status: rx_status as given by the device
1380  *
1381  * This function converts the rate as encoded in the received packet to the
1382  * zd-rate, we are using on other places in the driver.
1383  */
1384 u8 zd_rx_rate(const void *rx_frame, const struct rx_status *status)
1385 {
1386     u8 zd_rate;
1387     if (status->frame_status & ZD_RX_OFDM) {
1388         zd_rate = zd_rate_from_ofdm_plcp_header(rx_frame);
1389     } else {
1390         switch (zd_cck_plcp_header_signal(rx_frame)) {
1391         case ZD_CCK_PLCP_SIGNAL_1M:
1392             zd_rate = ZD_CCK_RATE_1M;
1393             break;
1394         case ZD_CCK_PLCP_SIGNAL_2M:
1395             zd_rate = ZD_CCK_RATE_2M;
1396             break;
1397         case ZD_CCK_PLCP_SIGNAL_5M5:
1398             zd_rate = ZD_CCK_RATE_5_5M;
1399             break;
1400         case ZD_CCK_PLCP_SIGNAL_11M:
1401             zd_rate = ZD_CCK_RATE_11M;
1402             break;
1403         default:
1404             zd_rate = 0;
1405         }
1406     }
1407 
1408     return zd_rate;
1409 }
1410 
1411 int zd_chip_switch_radio_on(struct zd_chip *chip)
1412 {
1413     int r;
1414 
1415     mutex_lock(&chip->mutex);
1416     r = zd_switch_radio_on(&chip->rf);
1417     mutex_unlock(&chip->mutex);
1418     return r;
1419 }
1420 
1421 int zd_chip_switch_radio_off(struct zd_chip *chip)
1422 {
1423     int r;
1424 
1425     mutex_lock(&chip->mutex);
1426     r = zd_switch_radio_off(&chip->rf);
1427     mutex_unlock(&chip->mutex);
1428     return r;
1429 }
1430 
1431 int zd_chip_enable_int(struct zd_chip *chip)
1432 {
1433     int r;
1434 
1435     mutex_lock(&chip->mutex);
1436     r = zd_usb_enable_int(&chip->usb);
1437     mutex_unlock(&chip->mutex);
1438     return r;
1439 }
1440 
1441 void zd_chip_disable_int(struct zd_chip *chip)
1442 {
1443     mutex_lock(&chip->mutex);
1444     zd_usb_disable_int(&chip->usb);
1445     mutex_unlock(&chip->mutex);
1446 
1447     /* cancel pending interrupt work */
1448     cancel_work_sync(&zd_chip_to_mac(chip)->process_intr);
1449 }
1450 
1451 int zd_chip_enable_rxtx(struct zd_chip *chip)
1452 {
1453     int r;
1454 
1455     mutex_lock(&chip->mutex);
1456     zd_usb_enable_tx(&chip->usb);
1457     r = zd_usb_enable_rx(&chip->usb);
1458     zd_tx_watchdog_enable(&chip->usb);
1459     mutex_unlock(&chip->mutex);
1460     return r;
1461 }
1462 
1463 void zd_chip_disable_rxtx(struct zd_chip *chip)
1464 {
1465     mutex_lock(&chip->mutex);
1466     zd_tx_watchdog_disable(&chip->usb);
1467     zd_usb_disable_rx(&chip->usb);
1468     zd_usb_disable_tx(&chip->usb);
1469     mutex_unlock(&chip->mutex);
1470 }
1471 
1472 int zd_rfwritev_locked(struct zd_chip *chip,
1473                    const u32* values, unsigned int count, u8 bits)
1474 {
1475     int r;
1476     unsigned int i;
1477 
1478     for (i = 0; i < count; i++) {
1479         r = zd_rfwrite_locked(chip, values[i], bits);
1480         if (r)
1481             return r;
1482     }
1483 
1484     return 0;
1485 }
1486 
1487 /*
1488  * We can optionally program the RF directly through CR regs, if supported by
1489  * the hardware. This is much faster than the older method.
1490  */
1491 int zd_rfwrite_cr_locked(struct zd_chip *chip, u32 value)
1492 {
1493     const struct zd_ioreq16 ioreqs[] = {
1494         { ZD_CR244, (value >> 16) & 0xff },
1495         { ZD_CR243, (value >>  8) & 0xff },
1496         { ZD_CR242,  value        & 0xff },
1497     };
1498     ZD_ASSERT(mutex_is_locked(&chip->mutex));
1499     return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1500 }
1501 
1502 int zd_rfwritev_cr_locked(struct zd_chip *chip,
1503                       const u32 *values, unsigned int count)
1504 {
1505     int r;
1506     unsigned int i;
1507 
1508     for (i = 0; i < count; i++) {
1509         r = zd_rfwrite_cr_locked(chip, values[i]);
1510         if (r)
1511             return r;
1512     }
1513 
1514     return 0;
1515 }
1516 
1517 int zd_chip_set_multicast_hash(struct zd_chip *chip,
1518                            struct zd_mc_hash *hash)
1519 {
1520     const struct zd_ioreq32 ioreqs[] = {
1521         { CR_GROUP_HASH_P1, hash->low },
1522         { CR_GROUP_HASH_P2, hash->high },
1523     };
1524 
1525     return zd_iowrite32a(chip, ioreqs, ARRAY_SIZE(ioreqs));
1526 }
1527 
1528 u64 zd_chip_get_tsf(struct zd_chip *chip)
1529 {
1530     int r;
1531     static const zd_addr_t aw_pt_bi_addr[] =
1532         { CR_TSF_LOW_PART, CR_TSF_HIGH_PART };
1533     u32 values[2];
1534     u64 tsf;
1535 
1536     mutex_lock(&chip->mutex);
1537     r = zd_ioread32v_locked(chip, values, (const zd_addr_t *)aw_pt_bi_addr,
1538                             ARRAY_SIZE(aw_pt_bi_addr));
1539     mutex_unlock(&chip->mutex);
1540     if (r)
1541         return 0;
1542 
1543     tsf = values[1];
1544     tsf = (tsf << 32) | values[0];
1545 
1546     return tsf;
1547 }
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