st/cw1200/hwio.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Low-level API for mac80211 ST-Ericsson CW1200 drivers
0004  *
0005  * Copyright (c) 2010, ST-Ericsson
0006  * Author: Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no>
0007  *
0008  * Based on:
0009  * ST-Ericsson UMAC CW1200 driver which is
0010  * Copyright (c) 2010, ST-Ericsson
0011  * Author: Ajitpal Singh <ajitpal.singh@stericsson.com>
0012  */
0013
0014 #ifndef CW1200_HWIO_H_INCLUDED
0015 #define CW1200_HWIO_H_INCLUDED
0016
0017 /* extern */ struct cw1200_common;
0018
0019 #define CW1200_CUT_11_ID_STR        (0x302E3830)
0020 #define CW1200_CUT_22_ID_STR1       (0x302e3132)
0021 #define CW1200_CUT_22_ID_STR2       (0x32302e30)
0022 #define CW1200_CUT_22_ID_STR3       (0x3335)
0023 #define CW1200_CUT_ID_ADDR      (0xFFF17F90)
0024 #define CW1200_CUT2_ID_ADDR     (0xFFF1FF90)
0025
0026 /* Download control area */
0027 /* boot loader start address in SRAM */
0028 #define DOWNLOAD_BOOT_LOADER_OFFSET (0x00000000)
0029 /* 32K, 0x4000 to 0xDFFF */
0030 #define DOWNLOAD_FIFO_OFFSET        (0x00004000)
0031 /* 32K */
0032 #define DOWNLOAD_FIFO_SIZE      (0x00008000)
0033 /* 128 bytes, 0xFF80 to 0xFFFF */
0034 #define DOWNLOAD_CTRL_OFFSET        (0x0000FF80)
0035 #define DOWNLOAD_CTRL_DATA_DWORDS   (32-6)
0036
0037 struct download_cntl_t {
0038     /* size of whole firmware file (including Cheksum), host init */
0039     u32 image_size;
0040     /* downloading flags */
0041     u32 flags;
0042     /* No. of bytes put into the download, init & updated by host */
0043     u32 put;
0044     /* last traced program counter, last ARM reg_pc */
0045     u32 trace_pc;
0046     /* No. of bytes read from the download, host init, device updates */
0047     u32 get;
0048     /* r0, boot losader status, host init to pending, device updates */
0049     u32 status;
0050     /* Extra debug info, r1 to r14 if status=r0=DOWNLOAD_EXCEPTION */
0051     u32 debug_data[DOWNLOAD_CTRL_DATA_DWORDS];
0052 };
0053
0054 #define DOWNLOAD_IMAGE_SIZE_REG     \
0055     (DOWNLOAD_CTRL_OFFSET + offsetof(struct download_cntl_t, image_size))
0056 #define DOWNLOAD_FLAGS_REG      \
0057     (DOWNLOAD_CTRL_OFFSET + offsetof(struct download_cntl_t, flags))
0058 #define DOWNLOAD_PUT_REG        \
0059     (DOWNLOAD_CTRL_OFFSET + offsetof(struct download_cntl_t, put))
0060 #define DOWNLOAD_TRACE_PC_REG       \
0061     (DOWNLOAD_CTRL_OFFSET + offsetof(struct download_cntl_t, trace_pc))
0062 #define DOWNLOAD_GET_REG        \
0063     (DOWNLOAD_CTRL_OFFSET + offsetof(struct download_cntl_t, get))
0064 #define DOWNLOAD_STATUS_REG     \
0065     (DOWNLOAD_CTRL_OFFSET + offsetof(struct download_cntl_t, status))
0066 #define DOWNLOAD_DEBUG_DATA_REG     \
0067     (DOWNLOAD_CTRL_OFFSET + offsetof(struct download_cntl_t, debug_data))
0068 #define DOWNLOAD_DEBUG_DATA_LEN     (108)
0069
0070 #define DOWNLOAD_BLOCK_SIZE     (1024)
0071
0072 /* For boot loader detection */
0073 #define DOWNLOAD_ARE_YOU_HERE       (0x87654321)
0074 #define DOWNLOAD_I_AM_HERE      (0x12345678)
0075
0076 /* Download error code */
0077 #define DOWNLOAD_PENDING        (0xFFFFFFFF)
0078 #define DOWNLOAD_SUCCESS        (0)
0079 #define DOWNLOAD_EXCEPTION      (1)
0080 #define DOWNLOAD_ERR_MEM_1      (2)
0081 #define DOWNLOAD_ERR_MEM_2      (3)
0082 #define DOWNLOAD_ERR_SOFTWARE       (4)
0083 #define DOWNLOAD_ERR_FILE_SIZE      (5)
0084 #define DOWNLOAD_ERR_CHECKSUM       (6)
0085 #define DOWNLOAD_ERR_OVERFLOW       (7)
0086 #define DOWNLOAD_ERR_IMAGE      (8)
0087 #define DOWNLOAD_ERR_HOST       (9)
0088 #define DOWNLOAD_ERR_ABORT      (10)
0089
0090
0091 #define SYS_BASE_ADDR_SILICON       (0)
0092 #define PAC_BASE_ADDRESS_SILICON    (SYS_BASE_ADDR_SILICON + 0x09000000)
0093 #define PAC_SHARED_MEMORY_SILICON   (PAC_BASE_ADDRESS_SILICON)
0094
0095 #define CW1200_APB(addr)        (PAC_SHARED_MEMORY_SILICON + (addr))
0096
0097 /* Device register definitions */
0098
0099 /* WBF - SPI Register Addresses */
0100 #define ST90TDS_ADDR_ID_BASE        (0x0000)
0101 /* 16/32 bits */
0102 #define ST90TDS_CONFIG_REG_ID       (0x0000)
0103 /* 16/32 bits */
0104 #define ST90TDS_CONTROL_REG_ID      (0x0001)
0105 /* 16 bits, Q mode W/R */
0106 #define ST90TDS_IN_OUT_QUEUE_REG_ID (0x0002)
0107 /* 32 bits, AHB bus R/W */
0108 #define ST90TDS_AHB_DPORT_REG_ID    (0x0003)
0109 /* 16/32 bits */
0110 #define ST90TDS_SRAM_BASE_ADDR_REG_ID   (0x0004)
0111 /* 32 bits, APB bus R/W */
0112 #define ST90TDS_SRAM_DPORT_REG_ID   (0x0005)
0113 /* 32 bits, t_settle/general */
0114 #define ST90TDS_TSET_GEN_R_W_REG_ID (0x0006)
0115 /* 16 bits, Q mode read, no length */
0116 #define ST90TDS_FRAME_OUT_REG_ID    (0x0007)
0117 #define ST90TDS_ADDR_ID_MAX     (ST90TDS_FRAME_OUT_REG_ID)
0118
0119 /* WBF - Control register bit set */
0120 /* next o/p length, bit 11 to 0 */
0121 #define ST90TDS_CONT_NEXT_LEN_MASK  (0x0FFF)
0122 #define ST90TDS_CONT_WUP_BIT        (BIT(12))
0123 #define ST90TDS_CONT_RDY_BIT        (BIT(13))
0124 #define ST90TDS_CONT_IRQ_ENABLE     (BIT(14))
0125 #define ST90TDS_CONT_RDY_ENABLE     (BIT(15))
0126 #define ST90TDS_CONT_IRQ_RDY_ENABLE (BIT(14)|BIT(15))
0127
0128 /* SPI Config register bit set */
0129 #define ST90TDS_CONFIG_FRAME_BIT    (BIT(2))
0130 #define ST90TDS_CONFIG_WORD_MODE_BITS   (BIT(3)|BIT(4))
0131 #define ST90TDS_CONFIG_WORD_MODE_1  (BIT(3))
0132 #define ST90TDS_CONFIG_WORD_MODE_2  (BIT(4))
0133 #define ST90TDS_CONFIG_ERROR_0_BIT  (BIT(5))
0134 #define ST90TDS_CONFIG_ERROR_1_BIT  (BIT(6))
0135 #define ST90TDS_CONFIG_ERROR_2_BIT  (BIT(7))
0136 /* TBD: Sure??? */
0137 #define ST90TDS_CONFIG_CSN_FRAME_BIT    (BIT(7))
0138 #define ST90TDS_CONFIG_ERROR_3_BIT  (BIT(8))
0139 #define ST90TDS_CONFIG_ERROR_4_BIT  (BIT(9))
0140 /* QueueM */
0141 #define ST90TDS_CONFIG_ACCESS_MODE_BIT  (BIT(10))
0142 /* AHB bus */
0143 #define ST90TDS_CONFIG_AHB_PRFETCH_BIT  (BIT(11))
0144 #define ST90TDS_CONFIG_CPU_CLK_DIS_BIT  (BIT(12))
0145 /* APB bus */
0146 #define ST90TDS_CONFIG_PRFETCH_BIT  (BIT(13))
0147 /* cpu reset */
0148 #define ST90TDS_CONFIG_CPU_RESET_BIT    (BIT(14))
0149 #define ST90TDS_CONFIG_CLEAR_INT_BIT    (BIT(15))
0150
0151 /* For CW1200 the IRQ Enable and Ready Bits are in CONFIG register */
0152 #define ST90TDS_CONF_IRQ_ENABLE     (BIT(16))
0153 #define ST90TDS_CONF_RDY_ENABLE     (BIT(17))
0154 #define ST90TDS_CONF_IRQ_RDY_ENABLE (BIT(16)|BIT(17))
0155
0156 int cw1200_data_read(struct cw1200_common *priv,
0157              void *buf, size_t buf_len);
0158 int cw1200_data_write(struct cw1200_common *priv,
0159               const void *buf, size_t buf_len);
0160
0161 int cw1200_reg_read(struct cw1200_common *priv, u16 addr,
0162             void *buf, size_t buf_len);
0163 int cw1200_reg_write(struct cw1200_common *priv, u16 addr,
0164              const void *buf, size_t buf_len);
0165
0166 static inline int cw1200_reg_read_16(struct cw1200_common *priv,
0167                      u16 addr, u16 *val)
0168 {
0169     __le32 tmp;
0170     int i;
0171     i = cw1200_reg_read(priv, addr, &tmp, sizeof(tmp));
0172     *val = le32_to_cpu(tmp) & 0xfffff;
0173     return i;
0174 }
0175
0176 static inline int cw1200_reg_write_16(struct cw1200_common *priv,
0177                       u16 addr, u16 val)
0178 {
0179     __le32 tmp = cpu_to_le32((u32)val);
0180     return cw1200_reg_write(priv, addr, &tmp, sizeof(tmp));
0181 }
0182
0183 static inline int cw1200_reg_read_32(struct cw1200_common *priv,
0184                      u16 addr, u32 *val)
0185 {
0186     __le32 tmp;
0187     int i = cw1200_reg_read(priv, addr, &tmp, sizeof(tmp));
0188     *val = le32_to_cpu(tmp);
0189     return i;
0190 }
0191
0192 static inline int cw1200_reg_write_32(struct cw1200_common *priv,
0193                       u16 addr, u32 val)
0194 {
0195     __le32 tmp = cpu_to_le32(val);
0196     return cw1200_reg_write(priv, addr, &tmp, sizeof(val));
0197 }
0198
0199 int cw1200_indirect_read(struct cw1200_common *priv, u32 addr, void *buf,
0200              size_t buf_len, u32 prefetch, u16 port_addr);
0201 int cw1200_apb_write(struct cw1200_common *priv, u32 addr, const void *buf,
0202              size_t buf_len);
0203
0204 static inline int cw1200_apb_read(struct cw1200_common *priv, u32 addr,
0205                   void *buf, size_t buf_len)
0206 {
0207     return cw1200_indirect_read(priv, addr, buf, buf_len,
0208                     ST90TDS_CONFIG_PRFETCH_BIT,
0209                     ST90TDS_SRAM_DPORT_REG_ID);
0210 }
0211
0212 static inline int cw1200_ahb_read(struct cw1200_common *priv, u32 addr,
0213                   void *buf, size_t buf_len)
0214 {
0215     return cw1200_indirect_read(priv, addr, buf, buf_len,
0216                     ST90TDS_CONFIG_AHB_PRFETCH_BIT,
0217                     ST90TDS_AHB_DPORT_REG_ID);
0218 }
0219
0220 static inline int cw1200_apb_read_32(struct cw1200_common *priv,
0221                      u32 addr, u32 *val)
0222 {
0223     __le32 tmp;
0224     int i = cw1200_apb_read(priv, addr, &tmp, sizeof(tmp));
0225     *val = le32_to_cpu(tmp);
0226     return i;
0227 }
0228
0229 static inline int cw1200_apb_write_32(struct cw1200_common *priv,
0230                       u32 addr, u32 val)
0231 {
0232     __le32 tmp = cpu_to_le32(val);
0233     return cw1200_apb_write(priv, addr, &tmp, sizeof(val));
0234 }
0235 static inline int cw1200_ahb_read_32(struct cw1200_common *priv,
0236                      u32 addr, u32 *val)
0237 {
0238     __le32 tmp;
0239     int i = cw1200_ahb_read(priv, addr, &tmp, sizeof(tmp));
0240     *val = le32_to_cpu(tmp);
0241     return i;
0242 }
0243
0244 #endif /* CW1200_HWIO_H_INCLUDED */