st/cw1200/hwio.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Low-level device IO routines for ST-Ericsson CW1200 drivers
0004  *
0005  * Copyright (c) 2010, ST-Ericsson
0006  * Author: Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no>
0007  *
0008  * Based on:
0009  * ST-Ericsson UMAC CW1200 driver, which is
0010  * Copyright (c) 2010, ST-Ericsson
0011  * Author: Ajitpal Singh <ajitpal.singh@lockless.no>
0012  */
0013
0014 #include <linux/types.h>
0015
0016 #include "cw1200.h"
0017 #include "hwio.h"
0018 #include "hwbus.h"
0019
0020  /* Sdio addr is 4*spi_addr */
0021 #define SPI_REG_ADDR_TO_SDIO(spi_reg_addr) ((spi_reg_addr) << 2)
0022 #define SDIO_ADDR17BIT(buf_id, mpf, rfu, reg_id_ofs) \
0023                 ((((buf_id)    & 0x1F) << 7) \
0024                 | (((mpf)        & 1) << 6) \
0025                 | (((rfu)        & 1) << 5) \
0026                 | (((reg_id_ofs) & 0x1F) << 0))
0027 #define MAX_RETRY       3
0028
0029
0030 static int __cw1200_reg_read(struct cw1200_common *priv, u16 addr,
0031                  void *buf, size_t buf_len, int buf_id)
0032 {
0033     u16 addr_sdio;
0034     u32 sdio_reg_addr_17bit;
0035
0036     /* Check if buffer is aligned to 4 byte boundary */
0037     if (WARN_ON(((unsigned long)buf & 3) && (buf_len > 4))) {
0038         pr_err("buffer is not aligned.\n");
0039         return -EINVAL;
0040     }
0041
0042     /* Convert to SDIO Register Address */
0043     addr_sdio = SPI_REG_ADDR_TO_SDIO(addr);
0044     sdio_reg_addr_17bit = SDIO_ADDR17BIT(buf_id, 0, 0, addr_sdio);
0045
0046     return priv->hwbus_ops->hwbus_memcpy_fromio(priv->hwbus_priv,
0047                           sdio_reg_addr_17bit,
0048                           buf, buf_len);
0049 }
0050
0051 static int __cw1200_reg_write(struct cw1200_common *priv, u16 addr,
0052                 const void *buf, size_t buf_len, int buf_id)
0053 {
0054     u16 addr_sdio;
0055     u32 sdio_reg_addr_17bit;
0056
0057     /* Convert to SDIO Register Address */
0058     addr_sdio = SPI_REG_ADDR_TO_SDIO(addr);
0059     sdio_reg_addr_17bit = SDIO_ADDR17BIT(buf_id, 0, 0, addr_sdio);
0060
0061     return priv->hwbus_ops->hwbus_memcpy_toio(priv->hwbus_priv,
0062                         sdio_reg_addr_17bit,
0063                         buf, buf_len);
0064 }
0065
0066 static inline int __cw1200_reg_read_32(struct cw1200_common *priv,
0067                     u16 addr, u32 *val)
0068 {
0069     __le32 tmp;
0070     int i = __cw1200_reg_read(priv, addr, &tmp, sizeof(tmp), 0);
0071     *val = le32_to_cpu(tmp);
0072     return i;
0073 }
0074
0075 static inline int __cw1200_reg_write_32(struct cw1200_common *priv,
0076                     u16 addr, u32 val)
0077 {
0078     __le32 tmp = cpu_to_le32(val);
0079     return __cw1200_reg_write(priv, addr, &tmp, sizeof(tmp), 0);
0080 }
0081
0082 static inline int __cw1200_reg_read_16(struct cw1200_common *priv,
0083                     u16 addr, u16 *val)
0084 {
0085     __le16 tmp;
0086     int i = __cw1200_reg_read(priv, addr, &tmp, sizeof(tmp), 0);
0087     *val = le16_to_cpu(tmp);
0088     return i;
0089 }
0090
0091 static inline int __cw1200_reg_write_16(struct cw1200_common *priv,
0092                     u16 addr, u16 val)
0093 {
0094     __le16 tmp = cpu_to_le16(val);
0095     return __cw1200_reg_write(priv, addr, &tmp, sizeof(tmp), 0);
0096 }
0097
0098 int cw1200_reg_read(struct cw1200_common *priv, u16 addr, void *buf,
0099             size_t buf_len)
0100 {
0101     int ret;
0102     priv->hwbus_ops->lock(priv->hwbus_priv);
0103     ret = __cw1200_reg_read(priv, addr, buf, buf_len, 0);
0104     priv->hwbus_ops->unlock(priv->hwbus_priv);
0105     return ret;
0106 }
0107
0108 int cw1200_reg_write(struct cw1200_common *priv, u16 addr, const void *buf,
0109             size_t buf_len)
0110 {
0111     int ret;
0112     priv->hwbus_ops->lock(priv->hwbus_priv);
0113     ret = __cw1200_reg_write(priv, addr, buf, buf_len, 0);
0114     priv->hwbus_ops->unlock(priv->hwbus_priv);
0115     return ret;
0116 }
0117
0118 int cw1200_data_read(struct cw1200_common *priv, void *buf, size_t buf_len)
0119 {
0120     int ret, retry = 1;
0121     int buf_id_rx = priv->buf_id_rx;
0122
0123     priv->hwbus_ops->lock(priv->hwbus_priv);
0124
0125     while (retry <= MAX_RETRY) {
0126         ret = __cw1200_reg_read(priv,
0127                     ST90TDS_IN_OUT_QUEUE_REG_ID, buf,
0128                     buf_len, buf_id_rx + 1);
0129         if (!ret) {
0130             buf_id_rx = (buf_id_rx + 1) & 3;
0131             priv->buf_id_rx = buf_id_rx;
0132             break;
0133         } else {
0134             retry++;
0135             mdelay(1);
0136             pr_err("error :[%d]\n", ret);
0137         }
0138     }
0139
0140     priv->hwbus_ops->unlock(priv->hwbus_priv);
0141     return ret;
0142 }
0143
0144 int cw1200_data_write(struct cw1200_common *priv, const void *buf,
0145             size_t buf_len)
0146 {
0147     int ret, retry = 1;
0148     int buf_id_tx = priv->buf_id_tx;
0149
0150     priv->hwbus_ops->lock(priv->hwbus_priv);
0151
0152     while (retry <= MAX_RETRY) {
0153         ret = __cw1200_reg_write(priv,
0154                      ST90TDS_IN_OUT_QUEUE_REG_ID, buf,
0155                      buf_len, buf_id_tx);
0156         if (!ret) {
0157             buf_id_tx = (buf_id_tx + 1) & 31;
0158             priv->buf_id_tx = buf_id_tx;
0159             break;
0160         } else {
0161             retry++;
0162             mdelay(1);
0163             pr_err("error :[%d]\n", ret);
0164         }
0165     }
0166
0167     priv->hwbus_ops->unlock(priv->hwbus_priv);
0168     return ret;
0169 }
0170
0171 int cw1200_indirect_read(struct cw1200_common *priv, u32 addr, void *buf,
0172              size_t buf_len, u32 prefetch, u16 port_addr)
0173 {
0174     u32 val32 = 0;
0175     int i, ret;
0176
0177     if ((buf_len / 2) >= 0x1000) {
0178         pr_err("Can't read more than 0xfff words.\n");
0179         return -EINVAL;
0180     }
0181
0182     priv->hwbus_ops->lock(priv->hwbus_priv);
0183     /* Write address */
0184     ret = __cw1200_reg_write_32(priv, ST90TDS_SRAM_BASE_ADDR_REG_ID, addr);
0185     if (ret < 0) {
0186         pr_err("Can't write address register.\n");
0187         goto out;
0188     }
0189
0190     /* Read CONFIG Register Value - We will read 32 bits */
0191     ret = __cw1200_reg_read_32(priv, ST90TDS_CONFIG_REG_ID, &val32);
0192     if (ret < 0) {
0193         pr_err("Can't read config register.\n");
0194         goto out;
0195     }
0196
0197     /* Set PREFETCH bit */
0198     ret = __cw1200_reg_write_32(priv, ST90TDS_CONFIG_REG_ID,
0199                     val32 | prefetch);
0200     if (ret < 0) {
0201         pr_err("Can't write prefetch bit.\n");
0202         goto out;
0203     }
0204
0205     /* Check for PRE-FETCH bit to be cleared */
0206     for (i = 0; i < 20; i++) {
0207         ret = __cw1200_reg_read_32(priv, ST90TDS_CONFIG_REG_ID, &val32);
0208         if (ret < 0) {
0209             pr_err("Can't check prefetch bit.\n");
0210             goto out;
0211         }
0212         if (!(val32 & prefetch))
0213             break;
0214
0215         mdelay(i);
0216     }
0217
0218     if (val32 & prefetch) {
0219         pr_err("Prefetch bit is not cleared.\n");
0220         goto out;
0221     }
0222
0223     /* Read data port */
0224     ret = __cw1200_reg_read(priv, port_addr, buf, buf_len, 0);
0225     if (ret < 0) {
0226         pr_err("Can't read data port.\n");
0227         goto out;
0228     }
0229
0230 out:
0231     priv->hwbus_ops->unlock(priv->hwbus_priv);
0232     return ret;
0233 }
0234
0235 int cw1200_apb_write(struct cw1200_common *priv, u32 addr, const void *buf,
0236             size_t buf_len)
0237 {
0238     int ret;
0239
0240     if ((buf_len / 2) >= 0x1000) {
0241         pr_err("Can't write more than 0xfff words.\n");
0242         return -EINVAL;
0243     }
0244
0245     priv->hwbus_ops->lock(priv->hwbus_priv);
0246
0247     /* Write address */
0248     ret = __cw1200_reg_write_32(priv, ST90TDS_SRAM_BASE_ADDR_REG_ID, addr);
0249     if (ret < 0) {
0250         pr_err("Can't write address register.\n");
0251         goto out;
0252     }
0253
0254     /* Write data port */
0255     ret = __cw1200_reg_write(priv, ST90TDS_SRAM_DPORT_REG_ID,
0256                     buf, buf_len, 0);
0257     if (ret < 0) {
0258         pr_err("Can't write data port.\n");
0259         goto out;
0260     }
0261
0262 out:
0263     priv->hwbus_ops->unlock(priv->hwbus_priv);
0264     return ret;
0265 }
0266
0267 int __cw1200_irq_enable(struct cw1200_common *priv, int enable)
0268 {
0269     u32 val32;
0270     u16 val16;
0271     int ret;
0272
0273     if (HIF_8601_SILICON == priv->hw_type) {
0274         ret = __cw1200_reg_read_32(priv, ST90TDS_CONFIG_REG_ID, &val32);
0275         if (ret < 0) {
0276             pr_err("Can't read config register.\n");
0277             return ret;
0278         }
0279
0280         if (enable)
0281             val32 |= ST90TDS_CONF_IRQ_RDY_ENABLE;
0282         else
0283             val32 &= ~ST90TDS_CONF_IRQ_RDY_ENABLE;
0284
0285         ret = __cw1200_reg_write_32(priv, ST90TDS_CONFIG_REG_ID, val32);
0286         if (ret < 0) {
0287             pr_err("Can't write config register.\n");
0288             return ret;
0289         }
0290     } else {
0291         ret = __cw1200_reg_read_16(priv, ST90TDS_CONFIG_REG_ID, &val16);
0292         if (ret < 0) {
0293             pr_err("Can't read control register.\n");
0294             return ret;
0295         }
0296
0297         if (enable)
0298             val16 |= ST90TDS_CONT_IRQ_RDY_ENABLE;
0299         else
0300             val16 &= ~ST90TDS_CONT_IRQ_RDY_ENABLE;
0301
0302         ret = __cw1200_reg_write_16(priv, ST90TDS_CONFIG_REG_ID, val16);
0303         if (ret < 0) {
0304             pr_err("Can't write control register.\n");
0305             return ret;
0306         }
0307     }
0308     return 0;
0309 }