st/cw1200/fwio.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Firmware I/O code for mac80211 ST-Ericsson CW1200 drivers
0004  *
0005  * Copyright (c) 2010, ST-Ericsson
0006  * Author: Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no>
0007  *
0008  * Based on:
0009  * ST-Ericsson UMAC CW1200 driver which is
0010  * Copyright (c) 2010, ST-Ericsson
0011  * Author: Ajitpal Singh <ajitpal.singh@stericsson.com>
0012  */
0013
0014 #include <linux/vmalloc.h>
0015 #include <linux/sched.h>
0016 #include <linux/firmware.h>
0017
0018 #include "cw1200.h"
0019 #include "fwio.h"
0020 #include "hwio.h"
0021 #include "hwbus.h"
0022 #include "bh.h"
0023
0024 static int cw1200_get_hw_type(u32 config_reg_val, int *major_revision)
0025 {
0026     int hw_type = -1;
0027     u32 silicon_type = (config_reg_val >> 24) & 0x7;
0028     u32 silicon_vers = (config_reg_val >> 31) & 0x1;
0029
0030     switch (silicon_type) {
0031     case 0x00:
0032         *major_revision = 1;
0033         hw_type = HIF_9000_SILICON_VERSATILE;
0034         break;
0035     case 0x01:
0036     case 0x02: /* CW1x00 */
0037     case 0x04: /* CW1x60 */
0038         *major_revision = silicon_type;
0039         if (silicon_vers)
0040             hw_type = HIF_8601_VERSATILE;
0041         else
0042             hw_type = HIF_8601_SILICON;
0043         break;
0044     default:
0045         break;
0046     }
0047
0048     return hw_type;
0049 }
0050
0051 static int cw1200_load_firmware_cw1200(struct cw1200_common *priv)
0052 {
0053     int ret, block, num_blocks;
0054     unsigned i;
0055     u32 val32;
0056     u32 put = 0, get = 0;
0057     u8 *buf = NULL;
0058     const char *fw_path;
0059     const struct firmware *firmware = NULL;
0060
0061     /* Macroses are local. */
0062 #define APB_WRITE(reg, val) \
0063     do { \
0064         ret = cw1200_apb_write_32(priv, CW1200_APB(reg), (val)); \
0065         if (ret < 0) \
0066             goto exit; \
0067     } while (0)
0068 #define APB_WRITE2(reg, val) \
0069     do { \
0070         ret = cw1200_apb_write_32(priv, CW1200_APB(reg), (val)); \
0071         if (ret < 0) \
0072             goto free_buffer; \
0073     } while (0)
0074 #define APB_READ(reg, val) \
0075     do { \
0076         ret = cw1200_apb_read_32(priv, CW1200_APB(reg), &(val)); \
0077         if (ret < 0) \
0078             goto free_buffer; \
0079     } while (0)
0080 #define REG_WRITE(reg, val) \
0081     do { \
0082         ret = cw1200_reg_write_32(priv, (reg), (val)); \
0083         if (ret < 0) \
0084             goto exit; \
0085     } while (0)
0086 #define REG_READ(reg, val) \
0087     do { \
0088         ret = cw1200_reg_read_32(priv, (reg), &(val)); \
0089         if (ret < 0) \
0090             goto exit; \
0091     } while (0)
0092
0093     switch (priv->hw_revision) {
0094     case CW1200_HW_REV_CUT10:
0095         fw_path = FIRMWARE_CUT10;
0096         if (!priv->sdd_path)
0097             priv->sdd_path = SDD_FILE_10;
0098         break;
0099     case CW1200_HW_REV_CUT11:
0100         fw_path = FIRMWARE_CUT11;
0101         if (!priv->sdd_path)
0102             priv->sdd_path = SDD_FILE_11;
0103         break;
0104     case CW1200_HW_REV_CUT20:
0105         fw_path = FIRMWARE_CUT20;
0106         if (!priv->sdd_path)
0107             priv->sdd_path = SDD_FILE_20;
0108         break;
0109     case CW1200_HW_REV_CUT22:
0110         fw_path = FIRMWARE_CUT22;
0111         if (!priv->sdd_path)
0112             priv->sdd_path = SDD_FILE_22;
0113         break;
0114     case CW1X60_HW_REV:
0115         fw_path = FIRMWARE_CW1X60;
0116         if (!priv->sdd_path)
0117             priv->sdd_path = SDD_FILE_CW1X60;
0118         break;
0119     default:
0120         pr_err("Invalid silicon revision %d.\n", priv->hw_revision);
0121         return -EINVAL;
0122     }
0123
0124     /* Initialize common registers */
0125     APB_WRITE(DOWNLOAD_IMAGE_SIZE_REG, DOWNLOAD_ARE_YOU_HERE);
0126     APB_WRITE(DOWNLOAD_PUT_REG, 0);
0127     APB_WRITE(DOWNLOAD_GET_REG, 0);
0128     APB_WRITE(DOWNLOAD_STATUS_REG, DOWNLOAD_PENDING);
0129     APB_WRITE(DOWNLOAD_FLAGS_REG, 0);
0130
0131     /* Write the NOP Instruction */
0132     REG_WRITE(ST90TDS_SRAM_BASE_ADDR_REG_ID, 0xFFF20000);
0133     REG_WRITE(ST90TDS_AHB_DPORT_REG_ID, 0xEAFFFFFE);
0134
0135     /* Release CPU from RESET */
0136     REG_READ(ST90TDS_CONFIG_REG_ID, val32);
0137     val32 &= ~ST90TDS_CONFIG_CPU_RESET_BIT;
0138     REG_WRITE(ST90TDS_CONFIG_REG_ID, val32);
0139
0140     /* Enable Clock */
0141     val32 &= ~ST90TDS_CONFIG_CPU_CLK_DIS_BIT;
0142     REG_WRITE(ST90TDS_CONFIG_REG_ID, val32);
0143
0144     /* Load a firmware file */
0145     ret = request_firmware(&firmware, fw_path, priv->pdev);
0146     if (ret) {
0147         pr_err("Can't load firmware file %s.\n", fw_path);
0148         goto exit;
0149     }
0150
0151     buf = kmalloc(DOWNLOAD_BLOCK_SIZE, GFP_KERNEL | GFP_DMA);
0152     if (!buf) {
0153         pr_err("Can't allocate firmware load buffer.\n");
0154         ret = -ENOMEM;
0155         goto firmware_release;
0156     }
0157
0158     /* Check if the bootloader is ready */
0159     for (i = 0; i < 100; i += 1 + i / 2) {
0160         APB_READ(DOWNLOAD_IMAGE_SIZE_REG, val32);
0161         if (val32 == DOWNLOAD_I_AM_HERE)
0162             break;
0163         mdelay(i);
0164     } /* End of for loop */
0165
0166     if (val32 != DOWNLOAD_I_AM_HERE) {
0167         pr_err("Bootloader is not ready.\n");
0168         ret = -ETIMEDOUT;
0169         goto free_buffer;
0170     }
0171
0172     /* Calculcate number of download blocks */
0173     num_blocks = (firmware->size - 1) / DOWNLOAD_BLOCK_SIZE + 1;
0174
0175     /* Updating the length in Download Ctrl Area */
0176     val32 = firmware->size; /* Explicit cast from size_t to u32 */
0177     APB_WRITE2(DOWNLOAD_IMAGE_SIZE_REG, val32);
0178
0179     /* Firmware downloading loop */
0180     for (block = 0; block < num_blocks; block++) {
0181         size_t tx_size;
0182         size_t block_size;
0183
0184         /* check the download status */
0185         APB_READ(DOWNLOAD_STATUS_REG, val32);
0186         if (val32 != DOWNLOAD_PENDING) {
0187             pr_err("Bootloader reported error %d.\n", val32);
0188             ret = -EIO;
0189             goto free_buffer;
0190         }
0191
0192         /* loop until put - get <= 24K */
0193         for (i = 0; i < 100; i++) {
0194             APB_READ(DOWNLOAD_GET_REG, get);
0195             if ((put - get) <=
0196                 (DOWNLOAD_FIFO_SIZE - DOWNLOAD_BLOCK_SIZE))
0197                 break;
0198             mdelay(i);
0199         }
0200
0201         if ((put - get) > (DOWNLOAD_FIFO_SIZE - DOWNLOAD_BLOCK_SIZE)) {
0202             pr_err("Timeout waiting for FIFO.\n");
0203             ret = -ETIMEDOUT;
0204             goto free_buffer;
0205         }
0206
0207         /* calculate the block size */
0208         tx_size = block_size = min_t(size_t, firmware->size - put,
0209                     DOWNLOAD_BLOCK_SIZE);
0210
0211         memcpy(buf, &firmware->data[put], block_size);
0212         if (block_size < DOWNLOAD_BLOCK_SIZE) {
0213             memset(&buf[block_size], 0,
0214                    DOWNLOAD_BLOCK_SIZE - block_size);
0215             tx_size = DOWNLOAD_BLOCK_SIZE;
0216         }
0217
0218         /* send the block to sram */
0219         ret = cw1200_apb_write(priv,
0220             CW1200_APB(DOWNLOAD_FIFO_OFFSET +
0221                    (put & (DOWNLOAD_FIFO_SIZE - 1))),
0222             buf, tx_size);
0223         if (ret < 0) {
0224             pr_err("Can't write firmware block @ %d!\n",
0225                    put & (DOWNLOAD_FIFO_SIZE - 1));
0226             goto free_buffer;
0227         }
0228
0229         /* update the put register */
0230         put += block_size;
0231         APB_WRITE2(DOWNLOAD_PUT_REG, put);
0232     } /* End of firmware download loop */
0233
0234     /* Wait for the download completion */
0235     for (i = 0; i < 300; i += 1 + i / 2) {
0236         APB_READ(DOWNLOAD_STATUS_REG, val32);
0237         if (val32 != DOWNLOAD_PENDING)
0238             break;
0239         mdelay(i);
0240     }
0241     if (val32 != DOWNLOAD_SUCCESS) {
0242         pr_err("Wait for download completion failed: 0x%.8X\n", val32);
0243         ret = -ETIMEDOUT;
0244         goto free_buffer;
0245     } else {
0246         pr_info("Firmware download completed.\n");
0247         ret = 0;
0248     }
0249
0250 free_buffer:
0251     kfree(buf);
0252 firmware_release:
0253     release_firmware(firmware);
0254 exit:
0255     return ret;
0256
0257 #undef APB_WRITE
0258 #undef APB_WRITE2
0259 #undef APB_READ
0260 #undef REG_WRITE
0261 #undef REG_READ
0262 }
0263
0264
0265 static int config_reg_read(struct cw1200_common *priv, u32 *val)
0266 {
0267     switch (priv->hw_type) {
0268     case HIF_9000_SILICON_VERSATILE: {
0269         u16 val16;
0270         int ret = cw1200_reg_read_16(priv,
0271                          ST90TDS_CONFIG_REG_ID,
0272                          &val16);
0273         if (ret < 0)
0274             return ret;
0275         *val = val16;
0276         return 0;
0277     }
0278     case HIF_8601_VERSATILE:
0279     case HIF_8601_SILICON:
0280     default:
0281         cw1200_reg_read_32(priv, ST90TDS_CONFIG_REG_ID, val);
0282         break;
0283     }
0284     return 0;
0285 }
0286
0287 static int config_reg_write(struct cw1200_common *priv, u32 val)
0288 {
0289     switch (priv->hw_type) {
0290     case HIF_9000_SILICON_VERSATILE:
0291         return cw1200_reg_write_16(priv,
0292                        ST90TDS_CONFIG_REG_ID,
0293                        (u16)val);
0294     case HIF_8601_VERSATILE:
0295     case HIF_8601_SILICON:
0296     default:
0297         return cw1200_reg_write_32(priv, ST90TDS_CONFIG_REG_ID, val);
0298     }
0299     return 0;
0300 }
0301
0302 int cw1200_load_firmware(struct cw1200_common *priv)
0303 {
0304     int ret;
0305     int i;
0306     u32 val32;
0307     u16 val16;
0308     int major_revision = -1;
0309
0310     /* Read CONFIG Register */
0311     ret = cw1200_reg_read_32(priv, ST90TDS_CONFIG_REG_ID, &val32);
0312     if (ret < 0) {
0313         pr_err("Can't read config register.\n");
0314         goto out;
0315     }
0316
0317     if (val32 == 0 || val32 == 0xffffffff) {
0318         pr_err("Bad config register value (0x%08x)\n", val32);
0319         ret = -EIO;
0320         goto out;
0321     }
0322
0323     ret = cw1200_get_hw_type(val32, &major_revision);
0324     if (ret < 0) {
0325         pr_err("Can't deduce hardware type.\n");
0326         goto out;
0327     }
0328     priv->hw_type = ret;
0329
0330     /* Set DPLL Reg value, and read back to confirm writes work */
0331     ret = cw1200_reg_write_32(priv, ST90TDS_TSET_GEN_R_W_REG_ID,
0332                   cw1200_dpll_from_clk(priv->hw_refclk));
0333     if (ret < 0) {
0334         pr_err("Can't write DPLL register.\n");
0335         goto out;
0336     }
0337
0338     msleep(20);
0339
0340     ret = cw1200_reg_read_32(priv,
0341         ST90TDS_TSET_GEN_R_W_REG_ID, &val32);
0342     if (ret < 0) {
0343         pr_err("Can't read DPLL register.\n");
0344         goto out;
0345     }
0346
0347     if (val32 != cw1200_dpll_from_clk(priv->hw_refclk)) {
0348         pr_err("Unable to initialise DPLL register. Wrote 0x%.8X, Read 0x%.8X.\n",
0349                cw1200_dpll_from_clk(priv->hw_refclk), val32);
0350         ret = -EIO;
0351         goto out;
0352     }
0353
0354     /* Set wakeup bit in device */
0355     ret = cw1200_reg_read_16(priv, ST90TDS_CONTROL_REG_ID, &val16);
0356     if (ret < 0) {
0357         pr_err("set_wakeup: can't read control register.\n");
0358         goto out;
0359     }
0360
0361     ret = cw1200_reg_write_16(priv, ST90TDS_CONTROL_REG_ID,
0362         val16 | ST90TDS_CONT_WUP_BIT);
0363     if (ret < 0) {
0364         pr_err("set_wakeup: can't write control register.\n");
0365         goto out;
0366     }
0367
0368     /* Wait for wakeup */
0369     for (i = 0; i < 300; i += (1 + i / 2)) {
0370         ret = cw1200_reg_read_16(priv,
0371             ST90TDS_CONTROL_REG_ID, &val16);
0372         if (ret < 0) {
0373             pr_err("wait_for_wakeup: can't read control register.\n");
0374             goto out;
0375         }
0376
0377         if (val16 & ST90TDS_CONT_RDY_BIT)
0378             break;
0379
0380         msleep(i);
0381     }
0382
0383     if ((val16 & ST90TDS_CONT_RDY_BIT) == 0) {
0384         pr_err("wait_for_wakeup: device is not responding.\n");
0385         ret = -ETIMEDOUT;
0386         goto out;
0387     }
0388
0389     switch (major_revision) {
0390     case 1:
0391         /* CW1200 Hardware detection logic : Check for CUT1.1 */
0392         ret = cw1200_ahb_read_32(priv, CW1200_CUT_ID_ADDR, &val32);
0393         if (ret) {
0394             pr_err("HW detection: can't read CUT ID.\n");
0395             goto out;
0396         }
0397
0398         switch (val32) {
0399         case CW1200_CUT_11_ID_STR:
0400             pr_info("CW1x00 Cut 1.1 silicon detected.\n");
0401             priv->hw_revision = CW1200_HW_REV_CUT11;
0402             break;
0403         default:
0404             pr_info("CW1x00 Cut 1.0 silicon detected.\n");
0405             priv->hw_revision = CW1200_HW_REV_CUT10;
0406             break;
0407         }
0408
0409         /* According to ST-E, CUT<2.0 has busted BA TID0-3.
0410            Just disable it entirely...
0411         */
0412         priv->ba_rx_tid_mask = 0;
0413         priv->ba_tx_tid_mask = 0;
0414         break;
0415     case 2: {
0416         u32 ar1, ar2, ar3;
0417         ret = cw1200_ahb_read_32(priv, CW1200_CUT2_ID_ADDR, &ar1);
0418         if (ret) {
0419             pr_err("(1) HW detection: can't read CUT ID\n");
0420             goto out;
0421         }
0422         ret = cw1200_ahb_read_32(priv, CW1200_CUT2_ID_ADDR + 4, &ar2);
0423         if (ret) {
0424             pr_err("(2) HW detection: can't read CUT ID.\n");
0425             goto out;
0426         }
0427
0428         ret = cw1200_ahb_read_32(priv, CW1200_CUT2_ID_ADDR + 8, &ar3);
0429         if (ret) {
0430             pr_err("(3) HW detection: can't read CUT ID.\n");
0431             goto out;
0432         }
0433
0434         if (ar1 == CW1200_CUT_22_ID_STR1 &&
0435             ar2 == CW1200_CUT_22_ID_STR2 &&
0436             ar3 == CW1200_CUT_22_ID_STR3) {
0437             pr_info("CW1x00 Cut 2.2 silicon detected.\n");
0438             priv->hw_revision = CW1200_HW_REV_CUT22;
0439         } else {
0440             pr_info("CW1x00 Cut 2.0 silicon detected.\n");
0441             priv->hw_revision = CW1200_HW_REV_CUT20;
0442         }
0443         break;
0444     }
0445     case 4:
0446         pr_info("CW1x60 silicon detected.\n");
0447         priv->hw_revision = CW1X60_HW_REV;
0448         break;
0449     default:
0450         pr_err("Unsupported silicon major revision %d.\n",
0451                major_revision);
0452         ret = -ENOTSUPP;
0453         goto out;
0454     }
0455
0456     /* Checking for access mode */
0457     ret = config_reg_read(priv, &val32);
0458     if (ret < 0) {
0459         pr_err("Can't read config register.\n");
0460         goto out;
0461     }
0462
0463     if (!(val32 & ST90TDS_CONFIG_ACCESS_MODE_BIT)) {
0464         pr_err("Device is already in QUEUE mode!\n");
0465         ret = -EINVAL;
0466         goto out;
0467     }
0468
0469     switch (priv->hw_type)  {
0470     case HIF_8601_SILICON:
0471         if (priv->hw_revision == CW1X60_HW_REV) {
0472             pr_err("Can't handle CW1160/1260 firmware load yet.\n");
0473             ret = -ENOTSUPP;
0474             goto out;
0475         }
0476         ret = cw1200_load_firmware_cw1200(priv);
0477         break;
0478     default:
0479         pr_err("Can't perform firmware load for hw type %d.\n",
0480                priv->hw_type);
0481         ret = -ENOTSUPP;
0482         goto out;
0483     }
0484     if (ret < 0) {
0485         pr_err("Firmware load error.\n");
0486         goto out;
0487     }
0488
0489     /* Enable interrupt signalling */
0490     priv->hwbus_ops->lock(priv->hwbus_priv);
0491     ret = __cw1200_irq_enable(priv, 1);
0492     priv->hwbus_ops->unlock(priv->hwbus_priv);
0493     if (ret < 0)
0494         goto unsubscribe;
0495
0496     /* Configure device for MESSSAGE MODE */
0497     ret = config_reg_read(priv, &val32);
0498     if (ret < 0) {
0499         pr_err("Can't read config register.\n");
0500         goto unsubscribe;
0501     }
0502     ret = config_reg_write(priv, val32 & ~ST90TDS_CONFIG_ACCESS_MODE_BIT);
0503     if (ret < 0) {
0504         pr_err("Can't write config register.\n");
0505         goto unsubscribe;
0506     }
0507
0508     /* Unless we read the CONFIG Register we are
0509      * not able to get an interrupt
0510      */
0511     mdelay(10);
0512     config_reg_read(priv, &val32);
0513
0514 out:
0515     return ret;
0516
0517 unsubscribe:
0518     /* Disable interrupt signalling */
0519     priv->hwbus_ops->lock(priv->hwbus_priv);
0520     ret = __cw1200_irq_enable(priv, 0);
0521     priv->hwbus_ops->unlock(priv->hwbus_priv);
0522     return ret;
0523 }