silabs/wfx/hwio.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Low-level I/O functions.
0004  *
0005  * Copyright (c) 2017-2020, Silicon Laboratories, Inc.
0006  * Copyright (c) 2010, ST-Ericsson
0007  */
0008 #ifndef WFX_HWIO_H
0009 #define WFX_HWIO_H
0010
0011 #include <linux/types.h>
0012
0013 struct wfx_dev;
0014
0015 /* Caution: in the functions below, 'buf' will used with a DMA. So, it must be kmalloc'd (do not use
0016  * stack allocated buffers). In doubt, enable CONFIG_DEBUG_SG to detect badly located buffer.
0017  */
0018 int wfx_data_read(struct wfx_dev *wdev, void *buf, size_t buf_len);
0019 int wfx_data_write(struct wfx_dev *wdev, const void *buf, size_t buf_len);
0020
0021 int wfx_sram_buf_read(struct wfx_dev *wdev, u32 addr, void *buf, size_t len);
0022 int wfx_sram_buf_write(struct wfx_dev *wdev, u32 addr, const void *buf, size_t len);
0023
0024 int wfx_ahb_buf_read(struct wfx_dev *wdev, u32 addr, void *buf, size_t len);
0025 int wfx_ahb_buf_write(struct wfx_dev *wdev, u32 addr, const void *buf, size_t len);
0026
0027 int wfx_sram_reg_read(struct wfx_dev *wdev, u32 addr, u32 *val);
0028 int wfx_sram_reg_write(struct wfx_dev *wdev, u32 addr, u32 val);
0029
0030 int wfx_ahb_reg_read(struct wfx_dev *wdev, u32 addr, u32 *val);
0031 int wfx_ahb_reg_write(struct wfx_dev *wdev, u32 addr, u32 val);
0032
0033 #define CFG_ERR_SPI_FRAME          0x00000001 /* only with SPI */
0034 #define CFG_ERR_SDIO_BUF_MISMATCH  0x00000001 /* only with SDIO */
0035 #define CFG_ERR_BUF_UNDERRUN       0x00000002
0036 #define CFG_ERR_DATA_IN_TOO_LARGE  0x00000004
0037 #define CFG_ERR_HOST_NO_OUT_QUEUE  0x00000008
0038 #define CFG_ERR_BUF_OVERRUN        0x00000010
0039 #define CFG_ERR_DATA_OUT_TOO_LARGE 0x00000020
0040 #define CFG_ERR_HOST_NO_IN_QUEUE   0x00000040
0041 #define CFG_ERR_HOST_CRC_MISS      0x00000080 /* only with SDIO */
0042 #define CFG_SPI_IGNORE_CS          0x00000080 /* only with SPI */
0043 #define CFG_BYTE_ORDER_MASK        0x00000300 /* only writable with SPI */
0044 #define     CFG_BYTE_ORDER_BADC    0x00000000
0045 #define     CFG_BYTE_ORDER_DCBA    0x00000100
0046 #define     CFG_BYTE_ORDER_ABCD    0x00000200 /* SDIO always use this value */
0047 #define CFG_DIRECT_ACCESS_MODE     0x00000400
0048 #define CFG_PREFETCH_AHB           0x00000800
0049 #define CFG_DISABLE_CPU_CLK        0x00001000
0050 #define CFG_PREFETCH_SRAM          0x00002000
0051 #define CFG_CPU_RESET              0x00004000
0052 #define CFG_SDIO_DISABLE_IRQ       0x00008000 /* only with SDIO */
0053 #define CFG_IRQ_ENABLE_DATA        0x00010000
0054 #define CFG_IRQ_ENABLE_WRDY        0x00020000
0055 #define CFG_CLK_RISE_EDGE          0x00040000
0056 #define CFG_SDIO_DISABLE_CRC_CHK   0x00080000 /* only with SDIO */
0057 #define CFG_RESERVED               0x00F00000
0058 #define CFG_DEVICE_ID_MAJOR        0x07000000
0059 #define CFG_DEVICE_ID_RESERVED     0x78000000
0060 #define CFG_DEVICE_ID_TYPE         0x80000000
0061 int wfx_config_reg_read(struct wfx_dev *wdev, u32 *val);
0062 int wfx_config_reg_write(struct wfx_dev *wdev, u32 val);
0063 int wfx_config_reg_write_bits(struct wfx_dev *wdev, u32 mask, u32 val);
0064
0065 #define CTRL_NEXT_LEN_MASK   0x00000FFF
0066 #define CTRL_WLAN_WAKEUP     0x00001000
0067 #define CTRL_WLAN_READY      0x00002000
0068 int wfx_control_reg_read(struct wfx_dev *wdev, u32 *val);
0069 int wfx_control_reg_write(struct wfx_dev *wdev, u32 val);
0070 int wfx_control_reg_write_bits(struct wfx_dev *wdev, u32 mask, u32 val);
0071
0072 #define IGPR_RW          0x80000000
0073 #define IGPR_INDEX       0x7F000000
0074 #define IGPR_VALUE       0x00FFFFFF
0075 int wfx_igpr_reg_read(struct wfx_dev *wdev, int index, u32 *val);
0076 int wfx_igpr_reg_write(struct wfx_dev *wdev, int index, u32 val);
0077
0078 #endif