silabs/wfx/hif_tx_mib.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Implementation of the host-to-chip MIBs of the hardware API.
0004  *
0005  * Copyright (c) 2017-2020, Silicon Laboratories, Inc.
0006  * Copyright (c) 2010, ST-Ericsson
0007  * Copyright (C) 2010, ST-Ericsson SA
0008  */
0009
0010 #include <linux/etherdevice.h>
0011
0012 #include "wfx.h"
0013 #include "hif_tx.h"
0014 #include "hif_tx_mib.h"
0015 #include "hif_api_mib.h"
0016
0017 int wfx_hif_set_output_power(struct wfx_vif *wvif, int val)
0018 {
0019     struct wfx_hif_mib_current_tx_power_level arg = {
0020         .power_level = cpu_to_le32(val * 10),
0021     };
0022
0023     return wfx_hif_write_mib(wvif->wdev, wvif->id, HIF_MIB_ID_CURRENT_TX_POWER_LEVEL,
0024                  &arg, sizeof(arg));
0025 }
0026
0027 int wfx_hif_set_beacon_wakeup_period(struct wfx_vif *wvif,
0028                      unsigned int dtim_interval, unsigned int listen_interval)
0029 {
0030     struct wfx_hif_mib_beacon_wake_up_period arg = {
0031         .wakeup_period_min = dtim_interval,
0032         .receive_dtim = 0,
0033         .wakeup_period_max = listen_interval,
0034     };
0035
0036     if (dtim_interval > 0xFF || listen_interval > 0xFFFF)
0037         return -EINVAL;
0038     return wfx_hif_write_mib(wvif->wdev, wvif->id, HIF_MIB_ID_BEACON_WAKEUP_PERIOD,
0039                  &arg, sizeof(arg));
0040 }
0041
0042 int wfx_hif_set_rcpi_rssi_threshold(struct wfx_vif *wvif, int rssi_thold, int rssi_hyst)
0043 {
0044     struct wfx_hif_mib_rcpi_rssi_threshold arg = {
0045         .rolling_average_count = 8,
0046         .detection = 1,
0047     };
0048
0049     if (!rssi_thold && !rssi_hyst) {
0050         arg.upperthresh = 1;
0051         arg.lowerthresh = 1;
0052     } else {
0053         arg.upper_threshold = rssi_thold + rssi_hyst;
0054         arg.upper_threshold = (arg.upper_threshold + 110) * 2;
0055         arg.lower_threshold = rssi_thold;
0056         arg.lower_threshold = (arg.lower_threshold + 110) * 2;
0057     }
0058
0059     return wfx_hif_write_mib(wvif->wdev, wvif->id, HIF_MIB_ID_RCPI_RSSI_THRESHOLD,
0060                  &arg, sizeof(arg));
0061 }
0062
0063 int wfx_hif_get_counters_table(struct wfx_dev *wdev, int vif_id,
0064                    struct wfx_hif_mib_extended_count_table *arg)
0065 {
0066     if (wfx_api_older_than(wdev, 1, 3)) {
0067         /* extended_count_table is wider than count_table */
0068         memset(arg, 0xFF, sizeof(*arg));
0069         return wfx_hif_read_mib(wdev, vif_id, HIF_MIB_ID_COUNTERS_TABLE,
0070                     arg, sizeof(struct wfx_hif_mib_count_table));
0071     } else {
0072         return wfx_hif_read_mib(wdev, vif_id, HIF_MIB_ID_EXTENDED_COUNTERS_TABLE,
0073                     arg, sizeof(struct wfx_hif_mib_extended_count_table));
0074     }
0075 }
0076
0077 int wfx_hif_set_macaddr(struct wfx_vif *wvif, u8 *mac)
0078 {
0079     struct wfx_hif_mib_mac_address arg = { };
0080
0081     if (mac)
0082         ether_addr_copy(arg.mac_addr, mac);
0083     return wfx_hif_write_mib(wvif->wdev, wvif->id, HIF_MIB_ID_DOT11_MAC_ADDRESS,
0084                  &arg, sizeof(arg));
0085 }
0086
0087 int wfx_hif_set_rx_filter(struct wfx_vif *wvif, bool filter_bssid, bool filter_prbreq)
0088 {
0089     struct wfx_hif_mib_rx_filter arg = { };
0090
0091     if (filter_bssid)
0092         arg.bssid_filter = 1;
0093     if (!filter_prbreq)
0094         arg.fwd_probe_req = 1;
0095     return wfx_hif_write_mib(wvif->wdev, wvif->id, HIF_MIB_ID_RX_FILTER, &arg, sizeof(arg));
0096 }
0097
0098 int wfx_hif_set_beacon_filter_table(struct wfx_vif *wvif, int tbl_len,
0099                     const struct wfx_hif_ie_table_entry *tbl)
0100 {
0101     int ret;
0102     struct wfx_hif_mib_bcn_filter_table *arg;
0103     int buf_len = struct_size(arg, ie_table, tbl_len);
0104
0105     arg = kzalloc(buf_len, GFP_KERNEL);
0106     if (!arg)
0107         return -ENOMEM;
0108     arg->num_of_info_elmts = cpu_to_le32(tbl_len);
0109     memcpy(arg->ie_table, tbl, flex_array_size(arg, ie_table, tbl_len));
0110     ret = wfx_hif_write_mib(wvif->wdev, wvif->id, HIF_MIB_ID_BEACON_FILTER_TABLE,
0111                 arg, buf_len);
0112     kfree(arg);
0113     return ret;
0114 }
0115
0116 int wfx_hif_beacon_filter_control(struct wfx_vif *wvif, int enable, int beacon_count)
0117 {
0118     struct wfx_hif_mib_bcn_filter_enable arg = {
0119         .enable = cpu_to_le32(enable),
0120         .bcn_count = cpu_to_le32(beacon_count),
0121     };
0122     return wfx_hif_write_mib(wvif->wdev, wvif->id, HIF_MIB_ID_BEACON_FILTER_ENABLE,
0123                  &arg, sizeof(arg));
0124 }
0125
0126 int wfx_hif_set_operational_mode(struct wfx_dev *wdev, enum wfx_hif_op_power_mode mode)
0127 {
0128     struct wfx_hif_mib_gl_operational_power_mode arg = {
0129         .power_mode = mode,
0130         .wup_ind_activation = 1,
0131     };
0132
0133     return wfx_hif_write_mib(wdev, -1, HIF_MIB_ID_GL_OPERATIONAL_POWER_MODE,
0134                  &arg, sizeof(arg));
0135 }
0136
0137 int wfx_hif_set_template_frame(struct wfx_vif *wvif, struct sk_buff *skb,
0138                    u8 frame_type, int init_rate)
0139 {
0140     struct wfx_hif_mib_template_frame *arg;
0141
0142     WARN(skb->len > HIF_API_MAX_TEMPLATE_FRAME_SIZE, "frame is too big");
0143     skb_push(skb, 4);
0144     arg = (struct wfx_hif_mib_template_frame *)skb->data;
0145     skb_pull(skb, 4);
0146     arg->init_rate = init_rate;
0147     arg->frame_type = frame_type;
0148     arg->frame_length = cpu_to_le16(skb->len);
0149     return wfx_hif_write_mib(wvif->wdev, wvif->id, HIF_MIB_ID_TEMPLATE_FRAME,
0150                  arg, sizeof(*arg) + skb->len);
0151 }
0152
0153 int wfx_hif_set_mfp(struct wfx_vif *wvif, bool capable, bool required)
0154 {
0155     struct wfx_hif_mib_protected_mgmt_policy arg = { };
0156
0157     WARN(required && !capable, "incoherent arguments");
0158     if (capable) {
0159         arg.pmf_enable = 1;
0160         arg.host_enc_auth_frames = 1;
0161     }
0162     if (!required)
0163         arg.unpmf_allowed = 1;
0164     return wfx_hif_write_mib(wvif->wdev, wvif->id, HIF_MIB_ID_PROTECTED_MGMT_POLICY,
0165                  &arg, sizeof(arg));
0166 }
0167
0168 int wfx_hif_set_block_ack_policy(struct wfx_vif *wvif, u8 tx_tid_policy, u8 rx_tid_policy)
0169 {
0170     struct wfx_hif_mib_block_ack_policy arg = {
0171         .block_ack_tx_tid_policy = tx_tid_policy,
0172         .block_ack_rx_tid_policy = rx_tid_policy,
0173     };
0174
0175     return wfx_hif_write_mib(wvif->wdev, wvif->id, HIF_MIB_ID_BLOCK_ACK_POLICY,
0176                  &arg, sizeof(arg));
0177 }
0178
0179 int wfx_hif_set_association_mode(struct wfx_vif *wvif, int ampdu_density,
0180                  bool greenfield, bool short_preamble)
0181 {
0182     struct wfx_hif_mib_set_association_mode arg = {
0183         .preambtype_use = 1,
0184         .mode = 1,
0185         .spacing = 1,
0186         .short_preamble = short_preamble,
0187         .greenfield = greenfield,
0188         .mpdu_start_spacing = ampdu_density,
0189     };
0190
0191     return wfx_hif_write_mib(wvif->wdev, wvif->id, HIF_MIB_ID_SET_ASSOCIATION_MODE,
0192                  &arg, sizeof(arg));
0193 }
0194
0195 int wfx_hif_set_tx_rate_retry_policy(struct wfx_vif *wvif, int policy_index, u8 *rates)
0196 {
0197     struct wfx_hif_mib_set_tx_rate_retry_policy *arg;
0198     size_t size = struct_size(arg, tx_rate_retry_policy, 1);
0199     int ret;
0200
0201     arg = kzalloc(size, GFP_KERNEL);
0202     if (!arg)
0203         return -ENOMEM;
0204     arg->num_tx_rate_policies = 1;
0205     arg->tx_rate_retry_policy[0].policy_index = policy_index;
0206     arg->tx_rate_retry_policy[0].short_retry_count = 255;
0207     arg->tx_rate_retry_policy[0].long_retry_count = 255;
0208     arg->tx_rate_retry_policy[0].first_rate_sel = 1;
0209     arg->tx_rate_retry_policy[0].terminate = 1;
0210     arg->tx_rate_retry_policy[0].count_init = 1;
0211     memcpy(&arg->tx_rate_retry_policy[0].rates, rates,
0212            sizeof(arg->tx_rate_retry_policy[0].rates));
0213     ret = wfx_hif_write_mib(wvif->wdev, wvif->id, HIF_MIB_ID_SET_TX_RATE_RETRY_POLICY,
0214                 arg, size);
0215     kfree(arg);
0216     return ret;
0217 }
0218
0219 int wfx_hif_keep_alive_period(struct wfx_vif *wvif, int period)
0220 {
0221     struct wfx_hif_mib_keep_alive_period arg = {
0222         .keep_alive_period = cpu_to_le16(period),
0223     };
0224
0225     return wfx_hif_write_mib(wvif->wdev, wvif->id, HIF_MIB_ID_KEEP_ALIVE_PERIOD,
0226                  &arg, sizeof(arg));
0227 };
0228
0229 int wfx_hif_set_arp_ipv4_filter(struct wfx_vif *wvif, int idx, __be32 *addr)
0230 {
0231     struct wfx_hif_mib_arp_ip_addr_table arg = {
0232         .condition_idx = idx,
0233         .arp_enable = HIF_ARP_NS_FILTERING_DISABLE,
0234     };
0235
0236     if (addr) {
0237         /* Caution: type of addr is __be32 */
0238         memcpy(arg.ipv4_address, addr, sizeof(arg.ipv4_address));
0239         arg.arp_enable = HIF_ARP_NS_FILTERING_ENABLE;
0240     }
0241     return wfx_hif_write_mib(wvif->wdev, wvif->id, HIF_MIB_ID_ARP_IP_ADDRESSES_TABLE,
0242                  &arg, sizeof(arg));
0243 }
0244
0245 int wfx_hif_use_multi_tx_conf(struct wfx_dev *wdev, bool enable)
0246 {
0247     struct wfx_hif_mib_gl_set_multi_msg arg = {
0248         .enable_multi_tx_conf = enable,
0249     };
0250
0251     return wfx_hif_write_mib(wdev, -1, HIF_MIB_ID_GL_SET_MULTI_MSG, &arg, sizeof(arg));
0252 }
0253
0254 int wfx_hif_set_uapsd_info(struct wfx_vif *wvif, unsigned long val)
0255 {
0256     struct wfx_hif_mib_set_uapsd_information arg = { };
0257
0258     if (val & BIT(IEEE80211_AC_VO))
0259         arg.trig_voice = 1;
0260     if (val & BIT(IEEE80211_AC_VI))
0261         arg.trig_video = 1;
0262     if (val & BIT(IEEE80211_AC_BE))
0263         arg.trig_be = 1;
0264     if (val & BIT(IEEE80211_AC_BK))
0265         arg.trig_bckgrnd = 1;
0266     return wfx_hif_write_mib(wvif->wdev, wvif->id, HIF_MIB_ID_SET_UAPSD_INFORMATION,
0267                  &arg, sizeof(arg));
0268 }
0269
0270 int wfx_hif_erp_use_protection(struct wfx_vif *wvif, bool enable)
0271 {
0272     struct wfx_hif_mib_non_erp_protection arg = {
0273         .use_cts_to_self = enable,
0274     };
0275
0276     return wfx_hif_write_mib(wvif->wdev, wvif->id, HIF_MIB_ID_NON_ERP_PROTECTION,
0277                  &arg, sizeof(arg));
0278 }
0279
0280 int wfx_hif_slot_time(struct wfx_vif *wvif, int val)
0281 {
0282     struct wfx_hif_mib_slot_time arg = {
0283         .slot_time = cpu_to_le32(val),
0284     };
0285
0286     return wfx_hif_write_mib(wvif->wdev, wvif->id, HIF_MIB_ID_SLOT_TIME, &arg, sizeof(arg));
0287 }
0288
0289 int wfx_hif_wep_default_key_id(struct wfx_vif *wvif, int val)
0290 {
0291     struct wfx_hif_mib_wep_default_key_id arg = {
0292         .wep_default_key_id = val,
0293     };
0294
0295     return wfx_hif_write_mib(wvif->wdev, wvif->id, HIF_MIB_ID_DOT11_WEP_DEFAULT_KEY_ID,
0296                  &arg, sizeof(arg));
0297 }
0298
0299 int wfx_hif_rts_threshold(struct wfx_vif *wvif, int val)
0300 {
0301     struct wfx_hif_mib_dot11_rts_threshold arg = {
0302         .threshold = cpu_to_le32(val >= 0 ? val : 0xFFFF),
0303     };
0304
0305     return wfx_hif_write_mib(wvif->wdev, wvif->id, HIF_MIB_ID_DOT11_RTS_THRESHOLD,
0306                  &arg, sizeof(arg));
0307 }