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0001 /* SPDX-License-Identifier: GPL-2.0-only or Apache-2.0 */
0002 /*
0003  * WF200 hardware interface definitions
0004  *
0005  * Copyright (c) 2018-2020, Silicon Laboratories Inc.
0006  */
0007 
0008 #ifndef WFX_HIF_API_MIB_H
0009 #define WFX_HIF_API_MIB_H
0010 
0011 #include "hif_api_general.h"
0012 
0013 #define HIF_API_IPV4_ADDRESS_SIZE 4
0014 #define HIF_API_IPV6_ADDRESS_SIZE 16
0015 
0016 enum wfx_hif_mib_ids {
0017     HIF_MIB_ID_GL_OPERATIONAL_POWER_MODE        = 0x2000,
0018     HIF_MIB_ID_GL_BLOCK_ACK_INFO                = 0x2001,
0019     HIF_MIB_ID_GL_SET_MULTI_MSG                 = 0x2002,
0020     HIF_MIB_ID_CCA_CONFIG                       = 0x2003,
0021     HIF_MIB_ID_ETHERTYPE_DATAFRAME_CONDITION    = 0x2010,
0022     HIF_MIB_ID_PORT_DATAFRAME_CONDITION         = 0x2011,
0023     HIF_MIB_ID_MAGIC_DATAFRAME_CONDITION        = 0x2012,
0024     HIF_MIB_ID_MAC_ADDR_DATAFRAME_CONDITION     = 0x2013,
0025     HIF_MIB_ID_IPV4_ADDR_DATAFRAME_CONDITION    = 0x2014,
0026     HIF_MIB_ID_IPV6_ADDR_DATAFRAME_CONDITION    = 0x2015,
0027     HIF_MIB_ID_UC_MC_BC_DATAFRAME_CONDITION     = 0x2016,
0028     HIF_MIB_ID_CONFIG_DATA_FILTER               = 0x2017,
0029     HIF_MIB_ID_SET_DATA_FILTERING               = 0x2018,
0030     HIF_MIB_ID_ARP_IP_ADDRESSES_TABLE           = 0x2019,
0031     HIF_MIB_ID_NS_IP_ADDRESSES_TABLE            = 0x201A,
0032     HIF_MIB_ID_RX_FILTER                        = 0x201B,
0033     HIF_MIB_ID_BEACON_FILTER_TABLE              = 0x201C,
0034     HIF_MIB_ID_BEACON_FILTER_ENABLE             = 0x201D,
0035     HIF_MIB_ID_GRP_SEQ_COUNTER                  = 0x2030,
0036     HIF_MIB_ID_TSF_COUNTER                      = 0x2031,
0037     HIF_MIB_ID_STATISTICS_TABLE                 = 0x2032,
0038     HIF_MIB_ID_COUNTERS_TABLE                   = 0x2033,
0039     HIF_MIB_ID_MAX_TX_POWER_LEVEL               = 0x2034,
0040     HIF_MIB_ID_EXTENDED_COUNTERS_TABLE          = 0x2035,
0041     HIF_MIB_ID_DOT11_MAC_ADDRESS                = 0x2040,
0042     HIF_MIB_ID_DOT11_MAX_TRANSMIT_MSDU_LIFETIME = 0x2041,
0043     HIF_MIB_ID_DOT11_MAX_RECEIVE_LIFETIME       = 0x2042,
0044     HIF_MIB_ID_DOT11_WEP_DEFAULT_KEY_ID         = 0x2043,
0045     HIF_MIB_ID_DOT11_RTS_THRESHOLD              = 0x2044,
0046     HIF_MIB_ID_SLOT_TIME                        = 0x2045,
0047     HIF_MIB_ID_CURRENT_TX_POWER_LEVEL           = 0x2046,
0048     HIF_MIB_ID_NON_ERP_PROTECTION               = 0x2047,
0049     HIF_MIB_ID_TEMPLATE_FRAME                   = 0x2048,
0050     HIF_MIB_ID_BEACON_WAKEUP_PERIOD             = 0x2049,
0051     HIF_MIB_ID_RCPI_RSSI_THRESHOLD              = 0x204A,
0052     HIF_MIB_ID_BLOCK_ACK_POLICY                 = 0x204B,
0053     HIF_MIB_ID_OVERRIDE_INTERNAL_TX_RATE        = 0x204C,
0054     HIF_MIB_ID_SET_ASSOCIATION_MODE             = 0x204D,
0055     HIF_MIB_ID_SET_UAPSD_INFORMATION            = 0x204E,
0056     HIF_MIB_ID_SET_TX_RATE_RETRY_POLICY         = 0x204F,
0057     HIF_MIB_ID_PROTECTED_MGMT_POLICY            = 0x2050,
0058     HIF_MIB_ID_SET_HT_PROTECTION                = 0x2051,
0059     HIF_MIB_ID_KEEP_ALIVE_PERIOD                = 0x2052,
0060     HIF_MIB_ID_ARP_KEEP_ALIVE_PERIOD            = 0x2053,
0061     HIF_MIB_ID_INACTIVITY_TIMER                 = 0x2054,
0062     HIF_MIB_ID_INTERFACE_PROTECTION             = 0x2055,
0063     HIF_MIB_ID_BEACON_STATS                     = 0x2056,
0064 };
0065 
0066 enum wfx_hif_op_power_mode {
0067     HIF_OP_POWER_MODE_ACTIVE    = 0x0,
0068     HIF_OP_POWER_MODE_DOZE      = 0x1,
0069     HIF_OP_POWER_MODE_QUIESCENT = 0x2
0070 };
0071 
0072 struct wfx_hif_mib_gl_operational_power_mode {
0073     u8     power_mode:4;
0074     u8     reserved1:3;
0075     u8     wup_ind_activation:1;
0076     u8     reserved2[3];
0077 } __packed;
0078 
0079 struct wfx_hif_mib_gl_set_multi_msg {
0080     u8     enable_multi_tx_conf:1;
0081     u8     reserved1:7;
0082     u8     reserved2[3];
0083 } __packed;
0084 
0085 enum wfx_hif_arp_ns_frame_treatment {
0086     HIF_ARP_NS_FILTERING_DISABLE = 0x0,
0087     HIF_ARP_NS_FILTERING_ENABLE  = 0x1,
0088     HIF_ARP_NS_REPLY_ENABLE      = 0x2
0089 };
0090 
0091 struct wfx_hif_mib_arp_ip_addr_table {
0092     u8     condition_idx;
0093     u8     arp_enable;
0094     u8     reserved[2];
0095     u8     ipv4_address[HIF_API_IPV4_ADDRESS_SIZE];
0096 } __packed;
0097 
0098 struct wfx_hif_mib_rx_filter {
0099     u8     reserved1:1;
0100     u8     bssid_filter:1;
0101     u8     reserved2:1;
0102     u8     fwd_probe_req:1;
0103     u8     keep_alive_filter:1;
0104     u8     reserved3:3;
0105     u8     reserved4[3];
0106 } __packed;
0107 
0108 struct wfx_hif_ie_table_entry {
0109     u8     ie_id;
0110     u8     has_changed:1;
0111     u8     no_longer:1;
0112     u8     has_appeared:1;
0113     u8     reserved:1;
0114     u8     num_match_data:4;
0115     u8     oui[3];
0116     u8     match_data[3];
0117 } __packed;
0118 
0119 struct wfx_hif_mib_bcn_filter_table {
0120     __le32 num_of_info_elmts;
0121     struct wfx_hif_ie_table_entry ie_table[];
0122 } __packed;
0123 
0124 enum wfx_hif_beacon_filter {
0125     HIF_BEACON_FILTER_DISABLE  = 0x0,
0126     HIF_BEACON_FILTER_ENABLE   = 0x1,
0127     HIF_BEACON_FILTER_AUTO_ERP = 0x2
0128 };
0129 
0130 struct wfx_hif_mib_bcn_filter_enable {
0131     __le32 enable;
0132     __le32 bcn_count;
0133 } __packed;
0134 
0135 struct wfx_hif_mib_extended_count_table {
0136     __le32 count_drop_plcp;
0137     __le32 count_drop_fcs;
0138     __le32 count_tx_frames;
0139     __le32 count_rx_frames;
0140     __le32 count_rx_frames_failed;
0141     __le32 count_drop_decryption;
0142     __le32 count_drop_tkip_mic;
0143     __le32 count_drop_no_key;
0144     __le32 count_tx_frames_multicast;
0145     __le32 count_tx_frames_success;
0146     __le32 count_tx_frames_failed;
0147     __le32 count_tx_frames_retried;
0148     __le32 count_tx_frames_multi_retried;
0149     __le32 count_drop_duplicate;
0150     __le32 count_rts_success;
0151     __le32 count_rts_failed;
0152     __le32 count_ack_failed;
0153     __le32 count_rx_frames_multicast;
0154     __le32 count_rx_frames_success;
0155     __le32 count_drop_cmac_icv;
0156     __le32 count_drop_cmac_replay;
0157     __le32 count_drop_ccmp_replay;
0158     __le32 count_drop_bip_mic;
0159     __le32 count_rx_bcn_success;
0160     __le32 count_rx_bcn_miss;
0161     __le32 count_rx_bcn_dtim;
0162     __le32 count_rx_bcn_dtim_aid0_clr;
0163     __le32 count_rx_bcn_dtim_aid0_set;
0164     __le32 reserved[12];
0165 } __packed;
0166 
0167 struct wfx_hif_mib_count_table {
0168     __le32 count_drop_plcp;
0169     __le32 count_drop_fcs;
0170     __le32 count_tx_frames;
0171     __le32 count_rx_frames;
0172     __le32 count_rx_frames_failed;
0173     __le32 count_drop_decryption;
0174     __le32 count_drop_tkip_mic;
0175     __le32 count_drop_no_key;
0176     __le32 count_tx_frames_multicast;
0177     __le32 count_tx_frames_success;
0178     __le32 count_tx_frames_failed;
0179     __le32 count_tx_frames_retried;
0180     __le32 count_tx_frames_multi_retried;
0181     __le32 count_drop_duplicate;
0182     __le32 count_rts_success;
0183     __le32 count_rts_failed;
0184     __le32 count_ack_failed;
0185     __le32 count_rx_frames_multicast;
0186     __le32 count_rx_frames_success;
0187     __le32 count_drop_cmac_icv;
0188     __le32 count_drop_cmac_replay;
0189     __le32 count_drop_ccmp_replay;
0190     __le32 count_drop_bip_mic;
0191 } __packed;
0192 
0193 struct wfx_hif_mib_mac_address {
0194     u8     mac_addr[ETH_ALEN];
0195     __le16 reserved;
0196 } __packed;
0197 
0198 struct wfx_hif_mib_wep_default_key_id {
0199     u8     wep_default_key_id;
0200     u8     reserved[3];
0201 } __packed;
0202 
0203 struct wfx_hif_mib_dot11_rts_threshold {
0204     __le32 threshold;
0205 } __packed;
0206 
0207 struct wfx_hif_mib_slot_time {
0208     __le32 slot_time;
0209 } __packed;
0210 
0211 struct wfx_hif_mib_current_tx_power_level {
0212     __le32 power_level; /* signed value */
0213 } __packed;
0214 
0215 struct wfx_hif_mib_non_erp_protection {
0216     u8     use_cts_to_self:1;
0217     u8     reserved1:7;
0218     u8     reserved2[3];
0219 } __packed;
0220 
0221 enum wfx_hif_tmplt {
0222     HIF_TMPLT_PRBREQ = 0x0,
0223     HIF_TMPLT_BCN    = 0x1,
0224     HIF_TMPLT_NULL   = 0x2,
0225     HIF_TMPLT_QOSNUL = 0x3,
0226     HIF_TMPLT_PSPOLL = 0x4,
0227     HIF_TMPLT_PRBRES = 0x5,
0228     HIF_TMPLT_ARP    = 0x6,
0229     HIF_TMPLT_NA     = 0x7
0230 };
0231 
0232 #define HIF_API_MAX_TEMPLATE_FRAME_SIZE 700
0233 
0234 struct wfx_hif_mib_template_frame {
0235     u8     frame_type;
0236     u8     init_rate:7;
0237     u8     mode:1;
0238     __le16 frame_length;
0239     u8     frame[];
0240 } __packed;
0241 
0242 struct wfx_hif_mib_beacon_wake_up_period {
0243     u8     wakeup_period_min;
0244     u8     receive_dtim:1;
0245     u8     reserved1:7;
0246     u8     wakeup_period_max;
0247     u8     reserved2;
0248 } __packed;
0249 
0250 struct wfx_hif_mib_rcpi_rssi_threshold {
0251     u8     detection:1;
0252     u8     rcpi_rssi:1;
0253     u8     upperthresh:1;
0254     u8     lowerthresh:1;
0255     u8     reserved:4;
0256     u8     lower_threshold;
0257     u8     upper_threshold;
0258     u8     rolling_average_count;
0259 } __packed;
0260 
0261 #define DEFAULT_BA_MAX_RX_BUFFER_SIZE 16
0262 
0263 struct wfx_hif_mib_block_ack_policy {
0264     u8     block_ack_tx_tid_policy;
0265     u8     reserved1;
0266     u8     block_ack_rx_tid_policy;
0267     u8     block_ack_rx_max_buffer_size;
0268 } __packed;
0269 
0270 enum wfx_hif_mpdu_start_spacing {
0271     HIF_MPDU_START_SPACING_NO_RESTRIC = 0x0,
0272     HIF_MPDU_START_SPACING_QUARTER    = 0x1,
0273     HIF_MPDU_START_SPACING_HALF       = 0x2,
0274     HIF_MPDU_START_SPACING_ONE        = 0x3,
0275     HIF_MPDU_START_SPACING_TWO        = 0x4,
0276     HIF_MPDU_START_SPACING_FOUR       = 0x5,
0277     HIF_MPDU_START_SPACING_EIGHT      = 0x6,
0278     HIF_MPDU_START_SPACING_SIXTEEN    = 0x7
0279 };
0280 
0281 struct wfx_hif_mib_set_association_mode {
0282     u8     preambtype_use:1;
0283     u8     mode:1;
0284     u8     rateset:1;
0285     u8     spacing:1;
0286     u8     reserved1:4;
0287     u8     short_preamble:1;
0288     u8     reserved2:7;
0289     u8     greenfield:1;
0290     u8     reserved3:7;
0291     u8     mpdu_start_spacing;
0292     __le32 basic_rate_set;
0293 } __packed;
0294 
0295 struct wfx_hif_mib_set_uapsd_information {
0296     u8     trig_bckgrnd:1;
0297     u8     trig_be:1;
0298     u8     trig_video:1;
0299     u8     trig_voice:1;
0300     u8     reserved1:4;
0301     u8     deliv_bckgrnd:1;
0302     u8     deliv_be:1;
0303     u8     deliv_video:1;
0304     u8     deliv_voice:1;
0305     u8     reserved2:4;
0306     __le16 min_auto_trigger_interval;
0307     __le16 max_auto_trigger_interval;
0308     __le16 auto_trigger_step;
0309 } __packed;
0310 
0311 struct wfx_hif_tx_rate_retry_policy {
0312     u8     policy_index;
0313     u8     short_retry_count;
0314     u8     long_retry_count;
0315     u8     first_rate_sel:2;
0316     u8     terminate:1;
0317     u8     count_init:1;
0318     u8     reserved1:4;
0319     u8     rate_recovery_count;
0320     u8     reserved2[3];
0321     u8     rates[12];
0322 } __packed;
0323 
0324 #define HIF_TX_RETRY_POLICY_MAX     15
0325 #define HIF_TX_RETRY_POLICY_INVALID HIF_TX_RETRY_POLICY_MAX
0326 
0327 struct wfx_hif_mib_set_tx_rate_retry_policy {
0328     u8     num_tx_rate_policies;
0329     u8     reserved[3];
0330     struct wfx_hif_tx_rate_retry_policy tx_rate_retry_policy[];
0331 } __packed;
0332 
0333 struct wfx_hif_mib_protected_mgmt_policy {
0334     u8     pmf_enable:1;
0335     u8     unpmf_allowed:1;
0336     u8     host_enc_auth_frames:1;
0337     u8     reserved1:5;
0338     u8     reserved2[3];
0339 } __packed;
0340 
0341 struct wfx_hif_mib_keep_alive_period {
0342     __le16 keep_alive_period;
0343     u8     reserved[2];
0344 } __packed;
0345 
0346 #endif