silabs/wfx/hif_api_general.h

0001 /* SPDX-License-Identifier: GPL-2.0-only or Apache-2.0 */
0002 /*
0003  * WF200 hardware interface definitions
0004  *
0005  * Copyright (c) 2018-2020, Silicon Laboratories Inc.
0006  */
0007
0008 #ifndef WFX_HIF_API_GENERAL_H
0009 #define WFX_HIF_API_GENERAL_H
0010
0011 #include <linux/types.h>
0012 #include <linux/if_ether.h>
0013
0014 #define HIF_ID_IS_INDICATION      0x80
0015 #define HIF_COUNTER_MAX           7
0016
0017 struct wfx_hif_msg {
0018     __le16 len;
0019     u8     id;
0020     u8     reserved:1;
0021     u8     interface:2;
0022     u8     seqnum:3;
0023     u8     encrypted:2;
0024     u8     body[];
0025 } __packed;
0026
0027 enum wfx_hif_general_requests_ids {
0028     HIF_REQ_ID_CONFIGURATION        = 0x09,
0029     HIF_REQ_ID_CONTROL_GPIO         = 0x26,
0030     HIF_REQ_ID_SET_SL_MAC_KEY       = 0x27,
0031     HIF_REQ_ID_SL_EXCHANGE_PUB_KEYS = 0x28,
0032     HIF_REQ_ID_SL_CONFIGURE         = 0x29,
0033     HIF_REQ_ID_PREVENT_ROLLBACK     = 0x2a,
0034     HIF_REQ_ID_PTA_SETTINGS         = 0x2b,
0035     HIF_REQ_ID_PTA_PRIORITY         = 0x2c,
0036     HIF_REQ_ID_PTA_STATE            = 0x2d,
0037     HIF_REQ_ID_SHUT_DOWN            = 0x32,
0038 };
0039
0040 enum wfx_hif_general_confirmations_ids {
0041     HIF_CNF_ID_CONFIGURATION        = 0x09,
0042     HIF_CNF_ID_CONTROL_GPIO         = 0x26,
0043     HIF_CNF_ID_SET_SL_MAC_KEY       = 0x27,
0044     HIF_CNF_ID_SL_EXCHANGE_PUB_KEYS = 0x28,
0045     HIF_CNF_ID_SL_CONFIGURE         = 0x29,
0046     HIF_CNF_ID_PREVENT_ROLLBACK     = 0x2a,
0047     HIF_CNF_ID_PTA_SETTINGS         = 0x2b,
0048     HIF_CNF_ID_PTA_PRIORITY         = 0x2c,
0049     HIF_CNF_ID_PTA_STATE            = 0x2d,
0050     HIF_CNF_ID_SHUT_DOWN            = 0x32,
0051 };
0052
0053 enum wfx_hif_general_indications_ids {
0054     HIF_IND_ID_EXCEPTION            = 0xe0,
0055     HIF_IND_ID_STARTUP              = 0xe1,
0056     HIF_IND_ID_WAKEUP               = 0xe2,
0057     HIF_IND_ID_GENERIC              = 0xe3,
0058     HIF_IND_ID_ERROR                = 0xe4,
0059     HIF_IND_ID_SL_EXCHANGE_PUB_KEYS = 0xe5
0060 };
0061
0062 #define HIF_STATUS_SUCCESS                         (cpu_to_le32(0x0000))
0063 #define HIF_STATUS_FAIL                            (cpu_to_le32(0x0001))
0064 #define HIF_STATUS_INVALID_PARAMETER               (cpu_to_le32(0x0002))
0065 #define HIF_STATUS_WARNING                         (cpu_to_le32(0x0003))
0066 #define HIF_STATUS_UNKNOWN_REQUEST                 (cpu_to_le32(0x0004))
0067 #define HIF_STATUS_RX_FAIL_DECRYPT                 (cpu_to_le32(0x0010))
0068 #define HIF_STATUS_RX_FAIL_MIC                     (cpu_to_le32(0x0011))
0069 #define HIF_STATUS_RX_FAIL_NO_KEY                  (cpu_to_le32(0x0012))
0070 #define HIF_STATUS_TX_FAIL_RETRIES                 (cpu_to_le32(0x0013))
0071 #define HIF_STATUS_TX_FAIL_TIMEOUT                 (cpu_to_le32(0x0014))
0072 #define HIF_STATUS_TX_FAIL_REQUEUE                 (cpu_to_le32(0x0015))
0073 #define HIF_STATUS_REFUSED                         (cpu_to_le32(0x0016))
0074 #define HIF_STATUS_BUSY                            (cpu_to_le32(0x0017))
0075 #define HIF_STATUS_SLK_SET_KEY_SUCCESS             (cpu_to_le32(0x005A))
0076 #define HIF_STATUS_SLK_SET_KEY_ALREADY_BURNED      (cpu_to_le32(0x006B))
0077 #define HIF_STATUS_SLK_SET_KEY_DISALLOWED_MODE     (cpu_to_le32(0x007C))
0078 #define HIF_STATUS_SLK_SET_KEY_UNKNOWN_MODE        (cpu_to_le32(0x008D))
0079 #define HIF_STATUS_SLK_NEGO_SUCCESS                (cpu_to_le32(0x009E))
0080 #define HIF_STATUS_SLK_NEGO_FAILED                 (cpu_to_le32(0x00AF))
0081 #define HIF_STATUS_ROLLBACK_SUCCESS                (cpu_to_le32(0x1234))
0082 #define HIF_STATUS_ROLLBACK_FAIL                   (cpu_to_le32(0x1256))
0083
0084 enum wfx_hif_api_rate_index {
0085     API_RATE_INDEX_B_1MBPS     = 0,
0086     API_RATE_INDEX_B_2MBPS     = 1,
0087     API_RATE_INDEX_B_5P5MBPS   = 2,
0088     API_RATE_INDEX_B_11MBPS    = 3,
0089     API_RATE_INDEX_PBCC_22MBPS = 4,
0090     API_RATE_INDEX_PBCC_33MBPS = 5,
0091     API_RATE_INDEX_G_6MBPS     = 6,
0092     API_RATE_INDEX_G_9MBPS     = 7,
0093     API_RATE_INDEX_G_12MBPS    = 8,
0094     API_RATE_INDEX_G_18MBPS    = 9,
0095     API_RATE_INDEX_G_24MBPS    = 10,
0096     API_RATE_INDEX_G_36MBPS    = 11,
0097     API_RATE_INDEX_G_48MBPS    = 12,
0098     API_RATE_INDEX_G_54MBPS    = 13,
0099     API_RATE_INDEX_N_6P5MBPS   = 14,
0100     API_RATE_INDEX_N_13MBPS    = 15,
0101     API_RATE_INDEX_N_19P5MBPS  = 16,
0102     API_RATE_INDEX_N_26MBPS    = 17,
0103     API_RATE_INDEX_N_39MBPS    = 18,
0104     API_RATE_INDEX_N_52MBPS    = 19,
0105     API_RATE_INDEX_N_58P5MBPS  = 20,
0106     API_RATE_INDEX_N_65MBPS    = 21,
0107     API_RATE_NUM_ENTRIES       = 22
0108 };
0109
0110 struct wfx_hif_ind_startup {
0111     __le32 status;
0112     __le16 hardware_id;
0113     u8     opn[14];
0114     u8     uid[8];
0115     __le16 num_inp_ch_bufs;
0116     __le16 size_inp_ch_buf;
0117     u8     num_links_ap;
0118     u8     num_interfaces;
0119     u8     mac_addr[2][ETH_ALEN];
0120     u8     api_version_minor;
0121     u8     api_version_major;
0122     u8     link_mode:2;
0123     u8     reserved1:6;
0124     u8     reserved2;
0125     u8     reserved3;
0126     u8     reserved4;
0127     u8     firmware_build;
0128     u8     firmware_minor;
0129     u8     firmware_major;
0130     u8     firmware_type;
0131     u8     disabled_channel_list[2];
0132     u8     region_sel_mode:4;
0133     u8     reserved5:4;
0134     u8     phy1_region:3;
0135     u8     phy0_region:3;
0136     u8     otp_phy_ver:2;
0137     __le32 supported_rate_mask;
0138     u8     firmware_label[128];
0139 } __packed;
0140
0141 struct wfx_hif_ind_wakeup {
0142 } __packed;
0143
0144 struct wfx_hif_req_configuration {
0145     __le16 length;
0146     u8     pds_data[];
0147 } __packed;
0148
0149 struct wfx_hif_cnf_configuration {
0150     __le32 status;
0151 } __packed;
0152
0153 enum wfx_hif_gpio_mode {
0154     HIF_GPIO_MODE_D0       = 0x0,
0155     HIF_GPIO_MODE_D1       = 0x1,
0156     HIF_GPIO_MODE_OD0      = 0x2,
0157     HIF_GPIO_MODE_OD1      = 0x3,
0158     HIF_GPIO_MODE_TRISTATE = 0x4,
0159     HIF_GPIO_MODE_TOGGLE   = 0x5,
0160     HIF_GPIO_MODE_READ     = 0x6
0161 };
0162
0163 struct wfx_hif_req_control_gpio {
0164     u8     gpio_label;
0165     u8     gpio_mode;
0166 } __packed;
0167
0168 struct wfx_hif_cnf_control_gpio {
0169     __le32 status;
0170     __le32 value;
0171 } __packed;
0172
0173 enum wfx_hif_generic_indication_type {
0174     HIF_GENERIC_INDICATION_TYPE_RAW                = 0x0,
0175     HIF_GENERIC_INDICATION_TYPE_STRING             = 0x1,
0176     HIF_GENERIC_INDICATION_TYPE_RX_STATS           = 0x2,
0177     HIF_GENERIC_INDICATION_TYPE_TX_POWER_LOOP_INFO = 0x3,
0178 };
0179
0180 struct wfx_hif_rx_stats {
0181     __le32 nb_rx_frame;
0182     __le32 nb_crc_frame;
0183     __le32 per_total;
0184     __le32 throughput;
0185     __le32 nb_rx_by_rate[API_RATE_NUM_ENTRIES];
0186     __le16 per[API_RATE_NUM_ENTRIES];
0187     __le16 snr[API_RATE_NUM_ENTRIES];  /* signed value */
0188     __le16 rssi[API_RATE_NUM_ENTRIES]; /* signed value */
0189     __le16 cfo[API_RATE_NUM_ENTRIES];  /* signed value */
0190     __le32 date;
0191     __le32 pwr_clk_freq;
0192     u8     is_ext_pwr_clk;
0193     s8     current_temp;
0194 } __packed;
0195
0196 struct wfx_hif_tx_power_loop_info {
0197     __le16 tx_gain_dig;
0198     __le16 tx_gain_pa;
0199     __le16 target_pout; /* signed value */
0200     __le16 p_estimation; /* signed value */
0201     __le16 vpdet;
0202     u8     measurement_index;
0203     u8     reserved;
0204 } __packed;
0205
0206 struct wfx_hif_ind_generic {
0207     __le32 type;
0208     union {
0209         struct wfx_hif_rx_stats rx_stats;
0210         struct wfx_hif_tx_power_loop_info tx_power_loop_info;
0211     } data;
0212 } __packed;
0213
0214 enum wfx_hif_error {
0215     HIF_ERROR_FIRMWARE_ROLLBACK           = 0x00,
0216     HIF_ERROR_FIRMWARE_DEBUG_ENABLED      = 0x01,
0217     HIF_ERROR_SLK_OUTDATED_SESSION_KEY    = 0x02,
0218     HIF_ERROR_SLK_SESSION_KEY             = 0x03,
0219     HIF_ERROR_OOR_VOLTAGE                 = 0x04,
0220     HIF_ERROR_PDS_PAYLOAD                 = 0x05,
0221     HIF_ERROR_OOR_TEMPERATURE             = 0x06,
0222     HIF_ERROR_SLK_REQ_DURING_KEY_EXCHANGE = 0x07,
0223     HIF_ERROR_SLK_MULTI_TX_UNSUPPORTED    = 0x08,
0224     HIF_ERROR_SLK_OVERFLOW                = 0x09,
0225     HIF_ERROR_SLK_DECRYPTION              = 0x0a,
0226     HIF_ERROR_SLK_WRONG_ENCRYPTION_STATE  = 0x0b,
0227     HIF_ERROR_HIF_BUS_FREQUENCY_TOO_LOW   = 0x0c,
0228     HIF_ERROR_HIF_RX_DATA_TOO_LARGE       = 0x0e,
0229     HIF_ERROR_HIF_TX_QUEUE_FULL           = 0x0d,
0230     HIF_ERROR_HIF_BUS                     = 0x0f,
0231     HIF_ERROR_PDS_TESTFEATURE             = 0x10,
0232     HIF_ERROR_SLK_UNCONFIGURED            = 0x11,
0233 };
0234
0235 struct wfx_hif_ind_error {
0236     __le32 type;
0237     u8     data[];
0238 } __packed;
0239
0240 struct wfx_hif_ind_exception {
0241     __le32 type;
0242     u8     data[];
0243 } __packed;
0244
0245 enum wfx_hif_secure_link_state {
0246     SEC_LINK_UNAVAILABLE = 0x0,
0247     SEC_LINK_RESERVED    = 0x1,
0248     SEC_LINK_EVAL        = 0x2,
0249     SEC_LINK_ENFORCED    = 0x3
0250 };
0251
0252 #endif