wireless/rsi/rsi_sdio.h

0001 /*
0002  * @section LICENSE
0003  * Copyright (c) 2014 Redpine Signals Inc.
0004  *
0005  * Permission to use, copy, modify, and/or distribute this software for any
0006  * purpose with or without fee is hereby granted, provided that the above
0007  * copyright notice and this permission notice appear in all copies.
0008  *
0009  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
0010  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
0011  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
0012  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
0013  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
0014  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
0015  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
0016  *
0017  */
0018
0019 #ifndef __RSI_SDIO_INTF__
0020 #define __RSI_SDIO_INTF__
0021
0022 #include <linux/mmc/card.h>
0023 #include <linux/mmc/mmc.h>
0024 #include <linux/mmc/host.h>
0025 #include <linux/mmc/sdio_func.h>
0026 #include <linux/mmc/sdio.h>
0027 #include <linux/mmc/sd.h>
0028 #include <linux/mmc/sdio_ids.h>
0029 #include "rsi_main.h"
0030
0031 enum sdio_interrupt_type {
0032     BUFFER_FULL         = 0x0,
0033     BUFFER_AVAILABLE    = 0x2,
0034     FIRMWARE_ASSERT_IND = 0x3,
0035     MSDU_PACKET_PENDING = 0x4,
0036     UNKNOWN_INT         = 0XE
0037 };
0038
0039 /* Buffer status register related info */
0040 #define PKT_BUFF_SEMI_FULL                      0
0041 #define PKT_BUFF_FULL                           1
0042 #define PKT_MGMT_BUFF_FULL                      2
0043 #define MSDU_PKT_PENDING                        3
0044 #define RECV_NUM_BLOCKS                         4
0045 /* Interrupt Bit Related Macros */
0046 #define PKT_BUFF_AVAILABLE                      1
0047 #define FW_ASSERT_IND                           2
0048
0049 #define RSI_MASTER_REG_BUF_SIZE         12
0050
0051 #define RSI_DEVICE_BUFFER_STATUS_REGISTER       0xf3
0052 #define RSI_FN1_INT_REGISTER                    0xf9
0053 #define RSI_INT_ENABLE_REGISTER         0x04
0054 #define RSI_INT_ENABLE_MASK         0xfc
0055 #define RSI_SD_REQUEST_MASTER                   0x10000
0056
0057 /* FOR SD CARD ONLY */
0058 #define SDIO_RX_NUM_BLOCKS_REG                  0x000F1
0059 #define SDIO_FW_STATUS_REG                      0x000F2
0060 #define SDIO_NXT_RD_DELAY2                      0x000F5
0061 #define SDIO_MASTER_ACCESS_MSBYTE               0x000FA
0062 #define SDIO_MASTER_ACCESS_LSBYTE               0x000FB
0063 #define SDIO_READ_START_LVL                     0x000FC
0064 #define SDIO_READ_FIFO_CTL                      0x000FD
0065 #define SDIO_WRITE_FIFO_CTL                     0x000FE
0066 #define SDIO_WAKEUP_REG             0x000FF
0067 #define SDIO_FUN1_INTR_CLR_REG                  0x0008
0068 #define SDIO_REG_HIGH_SPEED                     0x0013
0069
0070 #define RSI_GET_SDIO_INTERRUPT_TYPE(_I, TYPE)      \
0071     {                      \
0072         TYPE =                             \
0073         (_I & (1 << PKT_BUFF_AVAILABLE)) ? \
0074         BUFFER_AVAILABLE :         \
0075         (_I & (1 << MSDU_PKT_PENDING)) ?   \
0076         MSDU_PACKET_PENDING :              \
0077         (_I & (1 << FW_ASSERT_IND)) ?      \
0078         FIRMWARE_ASSERT_IND : UNKNOWN_INT; \
0079     }
0080
0081 /* common registers in SDIO function1 */
0082 #define TA_SOFT_RESET_REG            0x0004
0083 #define TA_TH0_PC_REG                0x0400
0084 #define TA_HOLD_THREAD_REG           0x0844
0085 #define TA_RELEASE_THREAD_REG        0x0848
0086
0087 #define TA_SOFT_RST_CLR              0
0088 #define TA_SOFT_RST_SET              BIT(0)
0089 #define TA_PC_ZERO                   0
0090 #define TA_HOLD_THREAD_VALUE         0xF
0091 #define TA_RELEASE_THREAD_VALUE      0xF
0092 #define TA_BASE_ADDR                 0x2200
0093 #define MISC_CFG_BASE_ADDR           0x4105
0094
0095 struct receive_info {
0096     bool buffer_full;
0097     bool semi_buffer_full;
0098     bool mgmt_buffer_full;
0099     u32 mgmt_buf_full_counter;
0100     u32 buf_semi_full_counter;
0101     u8 watch_bufferfull_count;
0102     u32 sdio_intr_status_zero;
0103     u32 sdio_int_counter;
0104     u32 total_sdio_msdu_pending_intr;
0105     u32 total_sdio_unknown_intr;
0106     u32 buf_full_counter;
0107     u32 buf_available_counter;
0108 };
0109
0110 struct rsi_91x_sdiodev {
0111     struct sdio_func *pfunction;
0112     struct task_struct *sdio_irq_task;
0113     struct receive_info rx_info;
0114     u32 next_read_delay;
0115     u32 sdio_high_speed_enable;
0116     u8 sdio_clock_speed;
0117     u32 cardcapability;
0118     u8 prev_desc[16];
0119     u16 tx_blk_size;
0120     u8 write_fail;
0121     bool buff_status_updated;
0122     struct rsi_thread rx_thread;
0123     u8 pktbuffer[8192] __aligned(4);
0124 };
0125
0126 int rsi_init_sdio_slave_regs(struct rsi_hw *adapter);
0127 int rsi_sdio_read_register(struct rsi_hw *adapter, u32 addr, u8 *data);
0128 int rsi_sdio_host_intf_read_pkt(struct rsi_hw *adapter, u8 *pkt, u32 length);
0129 int rsi_sdio_write_register(struct rsi_hw *adapter, u8 function,
0130                 u32 addr, u8 *data);
0131 int rsi_sdio_write_register_multiple(struct rsi_hw *adapter, u32 addr,
0132                      u8 *data, u16 count);
0133 int rsi_sdio_master_access_msword(struct rsi_hw *adapter, u16 ms_word);
0134 void rsi_sdio_ack_intr(struct rsi_hw *adapter, u8 int_bit);
0135 int rsi_sdio_determine_event_timeout(struct rsi_hw *adapter);
0136 int rsi_sdio_check_buffer_status(struct rsi_hw *adapter, u8 q_num);
0137 void rsi_sdio_rx_thread(struct rsi_common *common);
0138 #endif