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0017 #ifndef __RSI_MGMT_H__
0018 #define __RSI_MGMT_H__
0019
0020 #include <linux/sort.h>
0021 #include "rsi_boot_params.h"
0022 #include "rsi_main.h"
0023
0024 #define MAX_MGMT_PKT_SIZE 512
0025 #define RSI_NEEDED_HEADROOM 84
0026 #define RSI_RCV_BUFFER_LEN 2000
0027
0028 #define RSI_11B_MODE 0
0029 #define RSI_11G_MODE BIT(7)
0030 #define RETRY_COUNT 8
0031 #define RETRY_LONG 4
0032 #define RETRY_SHORT 7
0033 #define WMM_SHORT_SLOT_TIME 9
0034 #define SIFS_DURATION 16
0035
0036 #define EAPOL4_PACKET_LEN 0x85
0037 #define KEY_TYPE_CLEAR 0
0038 #define RSI_PAIRWISE_KEY 1
0039 #define RSI_GROUP_KEY 2
0040
0041
0042 #define WLAN_MAC_EEPROM_ADDR 40
0043 #define WLAN_MAC_MAGIC_WORD_LEN 0x01
0044 #define WLAN_HOST_MODE_LEN 0x04
0045 #define WLAN_FW_VERSION_LEN 0x08
0046 #define MAGIC_WORD 0x5A
0047 #define WLAN_EEPROM_RFTYPE_ADDR 424
0048
0049
0050 #define RSI_UNICAST_MAGIC_PKT BIT(0)
0051 #define RSI_BROADCAST_MAGICPKT BIT(1)
0052 #define RSI_EAPOL_PKT BIT(2)
0053 #define RSI_DISCONNECT_PKT BIT(3)
0054 #define RSI_HW_BMISS_PKT BIT(4)
0055 #define RSI_INSERT_SEQ_IN_FW BIT(2)
0056
0057 #define WOW_MAX_FILTERS_PER_LIST 16
0058 #define WOW_PATTERN_SIZE 256
0059
0060
0061 #define RSI_RX_DESC_MSG_TYPE_OFFSET 2
0062 #define TA_CONFIRM_TYPE 0x01
0063 #define RX_DOT11_MGMT 0x02
0064 #define TX_STATUS_IND 0x04
0065 #define BEACON_EVENT_IND 0x08
0066 #define EAPOL4_CONFIRM 1
0067 #define PROBEREQ_CONFIRM 2
0068 #define CARD_READY_IND 0x00
0069 #define SLEEP_NOTIFY_IND 0x06
0070 #define RSI_TX_STATUS_TYPE 15
0071 #define RSI_TX_STATUS 12
0072
0073 #define RSI_DELETE_PEER 0x0
0074 #define RSI_ADD_PEER 0x1
0075 #define START_AMPDU_AGGR 0x1
0076 #define STOP_AMPDU_AGGR 0x0
0077 #define INTERNAL_MGMT_PKT 0x99
0078
0079 #define PUT_BBP_RESET 0
0080 #define BBP_REG_WRITE 0
0081 #define RF_RESET_ENABLE BIT(3)
0082 #define RATE_INFO_ENABLE BIT(0)
0083 #define MORE_DATA_PRESENT BIT(1)
0084 #define RSI_BROADCAST_PKT BIT(9)
0085 #define RSI_DESC_REQUIRE_CFM_TO_HOST BIT(2)
0086 #define RSI_ADD_DELTA_TSF_VAP_ID BIT(3)
0087 #define RSI_FETCH_RETRY_CNT_FRM_HST BIT(4)
0088 #define RSI_QOS_ENABLE BIT(12)
0089 #define RSI_REKEY_PURPOSE BIT(13)
0090 #define RSI_ENCRYPT_PKT BIT(15)
0091 #define RSI_SET_PS_ENABLE BIT(12)
0092
0093 #define RSI_CMDDESC_40MHZ BIT(4)
0094 #define RSI_CMDDESC_UPPER_20_ENABLE BIT(5)
0095 #define RSI_CMDDESC_LOWER_20_ENABLE BIT(6)
0096 #define RSI_CMDDESC_FULL_40_ENABLE (BIT(5) | BIT(6))
0097 #define UPPER_20_ENABLE (0x2 << 12)
0098 #define LOWER_20_ENABLE (0x4 << 12)
0099 #define FULL40M_ENABLE 0x6
0100
0101 #define RSI_LMAC_CLOCK_80MHZ 0x1
0102 #define RSI_ENABLE_40MHZ (0x1 << 3)
0103 #define ENABLE_SHORTGI_RATE BIT(9)
0104
0105 #define RX_BA_INDICATION 1
0106 #define RSI_TBL_SZ 40
0107 #define MAX_RETRIES 8
0108 #define RSI_IFTYPE_STATION 0
0109
0110 #define STD_RATE_MCS7 0x07
0111 #define STD_RATE_MCS6 0x06
0112 #define STD_RATE_MCS5 0x05
0113 #define STD_RATE_MCS4 0x04
0114 #define STD_RATE_MCS3 0x03
0115 #define STD_RATE_MCS2 0x02
0116 #define STD_RATE_MCS1 0x01
0117 #define STD_RATE_MCS0 0x00
0118 #define STD_RATE_54 0x6c
0119 #define STD_RATE_48 0x60
0120 #define STD_RATE_36 0x48
0121 #define STD_RATE_24 0x30
0122 #define STD_RATE_18 0x24
0123 #define STD_RATE_12 0x18
0124 #define STD_RATE_11 0x16
0125 #define STD_RATE_09 0x12
0126 #define STD_RATE_06 0x0C
0127 #define STD_RATE_5_5 0x0B
0128 #define STD_RATE_02 0x04
0129 #define STD_RATE_01 0x02
0130
0131 #define RSI_RF_TYPE 1
0132 #define RSI_RATE_00 0x00
0133 #define RSI_RATE_1 0x0
0134 #define RSI_RATE_2 0x2
0135 #define RSI_RATE_5_5 0x4
0136 #define RSI_RATE_11 0x6
0137 #define RSI_RATE_6 0x8b
0138 #define RSI_RATE_9 0x8f
0139 #define RSI_RATE_12 0x8a
0140 #define RSI_RATE_18 0x8e
0141 #define RSI_RATE_24 0x89
0142 #define RSI_RATE_36 0x8d
0143 #define RSI_RATE_48 0x88
0144 #define RSI_RATE_54 0x8c
0145 #define RSI_RATE_MCS0 0x100
0146 #define RSI_RATE_MCS1 0x101
0147 #define RSI_RATE_MCS2 0x102
0148 #define RSI_RATE_MCS3 0x103
0149 #define RSI_RATE_MCS4 0x104
0150 #define RSI_RATE_MCS5 0x105
0151 #define RSI_RATE_MCS6 0x106
0152 #define RSI_RATE_MCS7 0x107
0153 #define RSI_RATE_MCS7_SG 0x307
0154 #define RSI_RATE_AUTO 0xffff
0155
0156 #define BW_20MHZ 0
0157 #define BW_40MHZ 1
0158
0159 #define EP_2GHZ_20MHZ 0
0160 #define EP_2GHZ_40MHZ 1
0161 #define EP_5GHZ_20MHZ 2
0162 #define EP_5GHZ_40MHZ 3
0163
0164 #define SIFS_TX_11N_VALUE 580
0165 #define SIFS_TX_11B_VALUE 346
0166 #define SHORT_SLOT_VALUE 360
0167 #define LONG_SLOT_VALUE 640
0168 #define OFDM_ACK_TOUT_VALUE 2720
0169 #define CCK_ACK_TOUT_VALUE 9440
0170 #define LONG_PREAMBLE 0x0000
0171 #define SHORT_PREAMBLE 0x0001
0172
0173 #define RSI_SUPP_FILTERS (FIF_ALLMULTI | FIF_PROBE_REQ |\
0174 FIF_BCN_PRBRESP_PROMISC)
0175
0176 #define ANTENNA_SEL_INT 0x02
0177 #define ANTENNA_SEL_UFL 0x03
0178 #define ANTENNA_MASK_VALUE 0x00ff
0179 #define ANTENNA_SEL_TYPE 1
0180
0181
0182 #define PROMISCOUS_MODE BIT(0)
0183 #define ALLOW_DATA_ASSOC_PEER BIT(1)
0184 #define ALLOW_MGMT_ASSOC_PEER BIT(2)
0185 #define ALLOW_CTRL_ASSOC_PEER BIT(3)
0186 #define DISALLOW_BEACONS BIT(4)
0187 #define ALLOW_CONN_PEER_MGMT_WHILE_BUF_FULL BIT(5)
0188 #define DISALLOW_BROADCAST_DATA BIT(6)
0189
0190 #define RSI_MPDU_DENSITY 0x8
0191 #define RSI_CHAN_RADAR BIT(7)
0192 #define RSI_BEACON_INTERVAL 200
0193 #define RSI_DTIM_COUNT 2
0194
0195 #define RSI_PS_DISABLE_IND BIT(15)
0196 #define RSI_PS_ENABLE 1
0197 #define RSI_PS_DISABLE 0
0198 #define RSI_DEEP_SLEEP 1
0199 #define RSI_CONNECTED_SLEEP 2
0200 #define RSI_SLEEP_REQUEST 1
0201 #define RSI_WAKEUP_REQUEST 2
0202
0203 #define RSI_IEEE80211_UAPSD_QUEUES \
0204 (IEEE80211_WMM_IE_STA_QOSINFO_AC_VO | \
0205 IEEE80211_WMM_IE_STA_QOSINFO_AC_VI | \
0206 IEEE80211_WMM_IE_STA_QOSINFO_AC_BE | \
0207 IEEE80211_WMM_IE_STA_QOSINFO_AC_BK)
0208
0209 #define RSI_DESC_VAP_ID_MASK 0xC000u
0210 #define RSI_DESC_VAP_ID_OFST 14
0211 #define RSI_DATA_DESC_MAC_BBP_INFO BIT(0)
0212 #define RSI_DATA_DESC_NO_ACK_IND BIT(9)
0213 #define RSI_DATA_DESC_QOS_EN BIT(12)
0214 #define RSI_DATA_DESC_NORMAL_FRAME 0x00
0215 #define RSI_DATA_DESC_DTIM_BEACON_GATED_FRAME BIT(10)
0216 #define RSI_DATA_DESC_BEACON_FRAME BIT(11)
0217 #define RSI_DATA_DESC_DTIM_BEACON (BIT(10) | BIT(11))
0218 #define RSI_DATA_DESC_INSERT_TSF BIT(15)
0219 #define RSI_DATA_DESC_INSERT_SEQ_NO BIT(2)
0220
0221 #ifdef CONFIG_PM
0222 #define RSI_WOW_ANY BIT(1)
0223 #define RSI_WOW_GTK_REKEY BIT(3)
0224 #define RSI_WOW_MAGIC_PKT BIT(4)
0225 #define RSI_WOW_DISCONNECT BIT(5)
0226 #endif
0227
0228 #define RSI_MAX_TX_AGGR_FRMS 8
0229 #define RSI_MAX_RX_AGGR_FRMS 8
0230
0231 #define RSI_MAX_SCAN_SSIDS 16
0232 #define RSI_MAX_SCAN_IE_LEN 256
0233
0234 enum opmode {
0235 RSI_OPMODE_UNSUPPORTED = -1,
0236 RSI_OPMODE_AP = 0,
0237 RSI_OPMODE_STA,
0238 RSI_OPMODE_P2P_GO,
0239 RSI_OPMODE_P2P_CLIENT
0240 };
0241
0242 enum vap_status {
0243 VAP_ADD = 1,
0244 VAP_DELETE = 2,
0245 VAP_UPDATE = 3
0246 };
0247
0248 enum peer_type {
0249 PEER_TYPE_AP,
0250 PEER_TYPE_STA,
0251 };
0252 extern struct ieee80211_rate rsi_rates[12];
0253 extern const u16 rsi_mcsrates[8];
0254
0255 enum sta_notify_events {
0256 STA_CONNECTED = 0,
0257 STA_DISCONNECTED,
0258 STA_TX_ADDBA_DONE,
0259 STA_TX_DELBA,
0260 STA_RX_ADDBA_DONE,
0261 STA_RX_DELBA
0262 };
0263
0264
0265 enum cmd_frame_type {
0266 TX_DOT11_MGMT,
0267 RESET_MAC_REQ,
0268 RADIO_CAPABILITIES,
0269 BB_PROG_VALUES_REQUEST,
0270 RF_PROG_VALUES_REQUEST,
0271 WAKEUP_SLEEP_REQUEST,
0272 SCAN_REQUEST,
0273 TSF_UPDATE,
0274 PEER_NOTIFY,
0275 BLOCK_HW_QUEUE,
0276 SET_KEY_REQ,
0277 AUTO_RATE_IND,
0278 BOOTUP_PARAMS_REQUEST,
0279 VAP_CAPABILITIES,
0280 EEPROM_READ,
0281 EEPROM_WRITE,
0282 GPIO_PIN_CONFIG ,
0283 SET_RX_FILTER,
0284 AMPDU_IND,
0285 STATS_REQUEST_FRAME,
0286 BB_BUF_PROG_VALUES_REQ,
0287 BBP_PROG_IN_TA,
0288 BG_SCAN_PARAMS,
0289 BG_SCAN_PROBE_REQ,
0290 CW_MODE_REQ,
0291 PER_CMD_PKT,
0292 ANT_SEL_FRAME = 0x20,
0293 VAP_DYNAMIC_UPDATE = 0x27,
0294 COMMON_DEV_CONFIG = 0x28,
0295 RADIO_PARAMS_UPDATE = 0x29,
0296 WOWLAN_CONFIG_PARAMS = 0x2B,
0297 FEATURES_ENABLE = 0x33,
0298 WOWLAN_WAKEUP_REASON = 0xc5
0299 };
0300
0301 struct rsi_mac_frame {
0302 __le16 desc_word[8];
0303 } __packed;
0304
0305 #define PWR_SAVE_WAKEUP_IND BIT(0)
0306 #define TCP_CHECK_SUM_OFFLOAD BIT(1)
0307 #define CONFIRM_REQUIRED_TO_HOST BIT(2)
0308 #define ADD_DELTA_TSF BIT(3)
0309 #define FETCH_RETRY_CNT_FROM_HOST_DESC BIT(4)
0310 #define EOSP_INDICATION BIT(5)
0311 #define REQUIRE_TSF_SYNC_CONFIRM BIT(6)
0312 #define ENCAP_MGMT_PKT BIT(7)
0313 #define DESC_IMMEDIATE_WAKEUP BIT(15)
0314
0315 struct rsi_xtended_desc {
0316 u8 confirm_frame_type;
0317 u8 retry_cnt;
0318 u16 reserved;
0319 };
0320
0321 struct rsi_cmd_desc_dword0 {
0322 __le16 len_qno;
0323 u8 frame_type;
0324 u8 misc_flags;
0325 };
0326
0327 struct rsi_cmd_desc_dword1 {
0328 u8 xtend_desc_size;
0329 u8 reserved1;
0330 __le16 reserved2;
0331 };
0332
0333 struct rsi_cmd_desc_dword2 {
0334 __le32 pkt_info;
0335 };
0336
0337 struct rsi_cmd_desc_dword3 {
0338 __le16 token;
0339 u8 qid_tid;
0340 u8 sta_id;
0341 };
0342
0343 struct rsi_cmd_desc {
0344 struct rsi_cmd_desc_dword0 desc_dword0;
0345 struct rsi_cmd_desc_dword1 desc_dword1;
0346 struct rsi_cmd_desc_dword2 desc_dword2;
0347 struct rsi_cmd_desc_dword3 desc_dword3;
0348 };
0349
0350 struct rsi_boot_params {
0351 __le16 desc_word[8];
0352 struct bootup_params bootup_params;
0353 } __packed;
0354
0355 struct rsi_boot_params_9116 {
0356 struct rsi_cmd_desc_dword0 desc_dword0;
0357 struct rsi_cmd_desc_dword1 desc_dword1;
0358 struct rsi_cmd_desc_dword2 desc_dword2;
0359 __le16 reserved;
0360 __le16 umac_clk;
0361 struct bootup_params_9116 bootup_params;
0362 } __packed;
0363
0364 struct rsi_peer_notify {
0365 struct rsi_cmd_desc desc;
0366 u8 mac_addr[6];
0367 __le16 command;
0368 __le16 mpdu_density;
0369 __le16 reserved;
0370 __le32 sta_flags;
0371 } __packed;
0372
0373
0374 #define RSI_AGGR_PARAMS_TID_MASK 0xf
0375 #define RSI_AGGR_PARAMS_START BIT(4)
0376 #define RSI_AGGR_PARAMS_RX_AGGR BIT(5)
0377 struct rsi_aggr_params {
0378 struct rsi_cmd_desc_dword0 desc_dword0;
0379 struct rsi_cmd_desc_dword0 desc_dword1;
0380 __le16 seq_start;
0381 __le16 baw_size;
0382 __le16 token;
0383 u8 aggr_params;
0384 u8 peer_id;
0385 } __packed;
0386
0387 struct rsi_bb_rf_prog {
0388 struct rsi_cmd_desc_dword0 desc_dword0;
0389 __le16 reserved1;
0390 u8 rf_power_mode;
0391 u8 reserved2;
0392 u8 endpoint;
0393 u8 reserved3;
0394 __le16 reserved4;
0395 __le16 reserved5;
0396 __le16 flags;
0397 } __packed;
0398
0399 struct rsi_chan_config {
0400 struct rsi_cmd_desc_dword0 desc_dword0;
0401 struct rsi_cmd_desc_dword1 desc_dword1;
0402 u8 channel_number;
0403 u8 antenna_gain_offset_2g;
0404 u8 antenna_gain_offset_5g;
0405 u8 channel_width;
0406 __le16 tx_power;
0407 u8 region_rftype;
0408 u8 flags;
0409 } __packed;
0410
0411 struct rsi_vap_caps {
0412 struct rsi_cmd_desc_dword0 desc_dword0;
0413 u8 reserved1;
0414 u8 status;
0415 __le16 reserved2;
0416 u8 vif_type;
0417 u8 channel_bw;
0418 __le16 antenna_info;
0419 __le16 token;
0420 u8 radioid_macid;
0421 u8 vap_id;
0422 u8 mac_addr[6];
0423 __le16 keep_alive_period;
0424 u8 bssid[6];
0425 __le16 reserved4;
0426 __le32 flags;
0427 __le16 frag_threshold;
0428 __le16 rts_threshold;
0429 __le32 default_mgmt_rate;
0430 __le16 default_ctrl_rate;
0431 __le16 ctrl_rate_flags;
0432 __le32 default_data_rate;
0433 __le16 beacon_interval;
0434 __le16 dtim_period;
0435 __le16 beacon_miss_threshold;
0436 } __packed;
0437
0438 struct rsi_ant_sel_frame {
0439 struct rsi_cmd_desc_dword0 desc_dword0;
0440 u8 reserved;
0441 u8 sub_frame_type;
0442 __le16 ant_value;
0443 __le32 reserved1;
0444 __le32 reserved2;
0445 } __packed;
0446
0447 struct rsi_dynamic_s {
0448 struct rsi_cmd_desc_dword0 desc_dword0;
0449 struct rsi_cmd_desc_dword1 desc_dword1;
0450 struct rsi_cmd_desc_dword2 desc_dword2;
0451 struct rsi_cmd_desc_dword3 desc_dword3;
0452 struct framebody {
0453 __le16 data_rate;
0454 __le16 mgmt_rate;
0455 __le16 keep_alive_period;
0456 } frame_body;
0457 } __packed;
0458
0459
0460 #define RSI_KEY_TYPE_BROADCAST BIT(1)
0461 #define RSI_WEP_KEY BIT(2)
0462 #define RSI_WEP_KEY_104 BIT(3)
0463 #define RSI_CIPHER_WPA BIT(4)
0464 #define RSI_CIPHER_TKIP BIT(5)
0465 #define RSI_KEY_MODE_AP BIT(7)
0466 #define RSI_PROTECT_DATA_FRAMES BIT(13)
0467 #define RSI_KEY_ID_MASK 0xC0
0468 #define RSI_KEY_ID_OFFSET 14
0469 struct rsi_set_key {
0470 struct rsi_cmd_desc_dword0 desc_dword0;
0471 struct rsi_cmd_desc_dword1 desc_dword1;
0472 __le16 key_desc;
0473 __le32 bpn;
0474 u8 sta_id;
0475 u8 vap_id;
0476 u8 key[4][32];
0477 u8 tx_mic_key[8];
0478 u8 rx_mic_key[8];
0479 } __packed;
0480
0481 struct rsi_auto_rate {
0482 struct rsi_cmd_desc desc;
0483 __le16 failure_limit;
0484 __le16 initial_boundary;
0485 __le16 max_threshold_limt;
0486 __le16 num_supported_rates;
0487 __le16 aarf_rssi;
0488 __le16 moderate_rate_inx;
0489 __le16 collision_tolerance;
0490 __le16 supported_rates[40];
0491 } __packed;
0492
0493 #define QUIET_INFO_VALID BIT(0)
0494 #define QUIET_ENABLE BIT(1)
0495 struct rsi_block_unblock_data {
0496 struct rsi_cmd_desc_dword0 desc_dword0;
0497 u8 xtend_desc_size;
0498 u8 host_quiet_info;
0499 __le16 reserved;
0500 __le16 block_q_bitmap;
0501 __le16 unblock_q_bitmap;
0502 __le16 token;
0503 __le16 flush_q_bitmap;
0504 } __packed;
0505
0506 struct qos_params {
0507 __le16 cont_win_min_q;
0508 __le16 cont_win_max_q;
0509 __le16 aifsn_val_q;
0510 __le16 txop_q;
0511 } __packed;
0512
0513 struct rsi_radio_caps {
0514 struct rsi_cmd_desc_dword0 desc_dword0;
0515 struct rsi_cmd_desc_dword0 desc_dword1;
0516 u8 channel_num;
0517 u8 rf_model;
0518 __le16 ppe_ack_rate;
0519 __le16 mode_11j;
0520 u8 radio_cfg_info;
0521 u8 radio_info;
0522 struct qos_params qos_params[MAX_HW_QUEUES];
0523 u8 num_11n_rates;
0524 u8 num_11ac_rates;
0525 __le16 gcpd_per_rate[20];
0526 __le16 sifs_tx_11n;
0527 __le16 sifs_tx_11b;
0528 __le16 slot_rx_11n;
0529 __le16 ofdm_ack_tout;
0530 __le16 cck_ack_tout;
0531 __le16 preamble_type;
0532 } __packed;
0533
0534
0535 #define RSI_GPIO_MOTION_SENSOR_ULP_WAKEUP BIT(0)
0536 #define RSI_GPIO_SLEEP_IND_FROM_DEVICE BIT(1)
0537 #define RSI_GPIO_2_ULP BIT(2)
0538 #define RSI_GPIO_PUSH_BUTTON_ULP_WAKEUP BIT(3)
0539
0540
0541 #define RSI_GPIO_0_PSPI_CSN_0 BIT(0)
0542 #define RSI_GPIO_1_PSPI_CSN_1 BIT(1)
0543 #define RSI_GPIO_2_HOST_WAKEUP_INTR BIT(2)
0544 #define RSI_GPIO_3_PSPI_DATA_0 BIT(3)
0545 #define RSI_GPIO_4_PSPI_DATA_1 BIT(4)
0546 #define RSI_GPIO_5_PSPI_DATA_2 BIT(5)
0547 #define RSI_GPIO_6_PSPI_DATA_3 BIT(6)
0548 #define RSI_GPIO_7_I2C_SCL BIT(7)
0549 #define RSI_GPIO_8_I2C_SDA BIT(8)
0550 #define RSI_GPIO_9_UART1_RX BIT(9)
0551 #define RSI_GPIO_10_UART1_TX BIT(10)
0552 #define RSI_GPIO_11_UART1_RTS_I2S_CLK BIT(11)
0553 #define RSI_GPIO_12_UART1_CTS_I2S_WS BIT(12)
0554 #define RSI_GPIO_13_DBG_UART_RX_I2S_DIN BIT(13)
0555 #define RSI_GPIO_14_DBG_UART_RX_I2S_DOUT BIT(14)
0556 #define RSI_GPIO_15_LP_WAKEUP_BOOT_BYPASS BIT(15)
0557 #define RSI_GPIO_16_LED_0 BIT(16)
0558 #define RSI_GPIO_17_BTCOEX_WLAN_ACT_EXT_ANT_SEL BIT(17)
0559 #define RSI_GPIO_18_BTCOEX_BT_PRIO_EXT_ANT_SEL BIT(18)
0560 #define RSI_GPIO_19_BTCOEX_BT_ACT_EXT_ON_OFF BIT(19)
0561 #define RSI_GPIO_20_RF_RESET BIT(20)
0562 #define RSI_GPIO_21_SLEEP_IND_FROM_DEVICE BIT(21)
0563
0564 #define RSI_UNUSED_SOC_GPIO_BITMAP (RSI_GPIO_9_UART1_RX | \
0565 RSI_GPIO_10_UART1_TX | \
0566 RSI_GPIO_11_UART1_RTS_I2S_CLK | \
0567 RSI_GPIO_12_UART1_CTS_I2S_WS | \
0568 RSI_GPIO_13_DBG_UART_RX_I2S_DIN | \
0569 RSI_GPIO_14_DBG_UART_RX_I2S_DOUT | \
0570 RSI_GPIO_15_LP_WAKEUP_BOOT_BYPASS | \
0571 RSI_GPIO_17_BTCOEX_WLAN_ACT_EXT_ANT_SEL | \
0572 RSI_GPIO_18_BTCOEX_BT_PRIO_EXT_ANT_SEL | \
0573 RSI_GPIO_19_BTCOEX_BT_ACT_EXT_ON_OFF | \
0574 RSI_GPIO_21_SLEEP_IND_FROM_DEVICE)
0575
0576 #define RSI_UNUSED_ULP_GPIO_BITMAP (RSI_GPIO_MOTION_SENSOR_ULP_WAKEUP | \
0577 RSI_GPIO_SLEEP_IND_FROM_DEVICE | \
0578 RSI_GPIO_2_ULP | \
0579 RSI_GPIO_PUSH_BUTTON_ULP_WAKEUP);
0580 struct rsi_config_vals {
0581 __le16 len_qno;
0582 u8 pkt_type;
0583 u8 misc_flags;
0584 __le16 reserved1[6];
0585 u8 lp_ps_handshake;
0586 u8 ulp_ps_handshake;
0587 u8 sleep_config_params;
0588
0589
0590
0591 u8 unused_ulp_gpio;
0592 __le32 unused_soc_gpio_bitmap;
0593 u8 ext_pa_or_bt_coex_en;
0594 u8 opermode;
0595 u8 wlan_rf_pwr_mode;
0596 u8 bt_rf_pwr_mode;
0597 u8 zigbee_rf_pwr_mode;
0598 u8 driver_mode;
0599 u8 region_code;
0600 u8 antenna_sel_val;
0601 u8 reserved2[16];
0602 } __packed;
0603
0604
0605 #define RSI_EEPROM_HDR_SIZE_OFFSET 8
0606 #define RSI_EEPROM_HDR_SIZE_MASK 0x300
0607 #define RSI_EEPROM_LEN_OFFSET 20
0608 #define RSI_EEPROM_LEN_MASK 0xFFF00000
0609
0610 struct rsi_eeprom_read_frame {
0611 __le16 len_qno;
0612 u8 pkt_type;
0613 u8 misc_flags;
0614 __le32 pkt_info;
0615 __le32 eeprom_offset;
0616 __le16 delay_ms;
0617 __le16 reserved3;
0618 } __packed;
0619
0620 struct rsi_request_ps {
0621 struct rsi_cmd_desc desc;
0622 struct ps_sleep_params ps_sleep;
0623 u8 ps_mimic_support;
0624 u8 ps_uapsd_acs;
0625 u8 ps_uapsd_wakeup_period;
0626 u8 reserved;
0627 __le32 ps_listen_interval;
0628 __le32 ps_dtim_interval_duration;
0629 __le16 ps_num_dtim_intervals;
0630 } __packed;
0631
0632 struct rsi_wowlan_req {
0633 struct rsi_cmd_desc desc;
0634 u8 sourceid[ETH_ALEN];
0635 u16 wow_flags;
0636 u16 host_sleep_status;
0637 } __packed;
0638
0639 #define RSI_START_BGSCAN 1
0640 #define RSI_STOP_BGSCAN 0
0641 #define HOST_BG_SCAN_TRIG BIT(4)
0642 struct rsi_bgscan_config {
0643 struct rsi_cmd_desc_dword0 desc_dword0;
0644 __le64 reserved;
0645 __le32 reserved1;
0646 __le16 bgscan_threshold;
0647 __le16 roam_threshold;
0648 __le16 bgscan_periodicity;
0649 u8 num_bgscan_channels;
0650 u8 two_probe;
0651 __le16 active_scan_duration;
0652 __le16 passive_scan_duration;
0653 __le16 channels2scan[MAX_BGSCAN_CHANNELS_DUAL_BAND];
0654 } __packed;
0655
0656 struct rsi_bgscan_probe {
0657 struct rsi_cmd_desc_dword0 desc_dword0;
0658 __le64 reserved;
0659 __le32 reserved1;
0660 __le16 mgmt_rate;
0661 __le16 flags;
0662 __le16 def_chan;
0663 __le16 channel_scan_time;
0664 __le16 probe_req_length;
0665 } __packed;
0666
0667 #define RSI_DUTY_CYCLING BIT(0)
0668 #define RSI_END_OF_FRAME BIT(1)
0669 #define RSI_SIFS_TX_ENABLE BIT(2)
0670 #define RSI_DPD BIT(3)
0671 struct rsi_wlan_9116_features {
0672 struct rsi_cmd_desc desc;
0673 u8 pll_mode;
0674 u8 rf_type;
0675 u8 wireless_mode;
0676 u8 enable_ppe;
0677 u8 afe_type;
0678 u8 reserved1;
0679 __le16 reserved2;
0680 __le32 feature_enable;
0681 };
0682
0683 static inline u32 rsi_get_queueno(u8 *addr, u16 offset)
0684 {
0685 return (le16_to_cpu(*(__le16 *)&addr[offset]) & 0x7000) >> 12;
0686 }
0687
0688 static inline u32 rsi_get_length(u8 *addr, u16 offset)
0689 {
0690 return (le16_to_cpu(*(__le16 *)&addr[offset])) & 0x0fff;
0691 }
0692
0693 static inline u8 rsi_get_extended_desc(u8 *addr, u16 offset)
0694 {
0695 return le16_to_cpu(*((__le16 *)&addr[offset + 4])) & 0x00ff;
0696 }
0697
0698 static inline u8 rsi_get_rssi(u8 *addr)
0699 {
0700 return *(u8 *)(addr + FRAME_DESC_SZ);
0701 }
0702
0703 static inline u8 rsi_get_channel(u8 *addr)
0704 {
0705 return *(char *)(addr + 15);
0706 }
0707
0708 static inline void rsi_set_len_qno(__le16 *addr, u16 len, u8 qno)
0709 {
0710 *addr = cpu_to_le16(len | ((qno & 7) << 12));
0711 }
0712
0713 int rsi_handle_card_ready(struct rsi_common *common, u8 *msg);
0714 int rsi_mgmt_pkt_recv(struct rsi_common *common, u8 *msg);
0715 int rsi_set_vap_capabilities(struct rsi_common *common, enum opmode mode,
0716 u8 *mac_addr, u8 vap_id, u8 vap_status);
0717 int rsi_send_aggregation_params_frame(struct rsi_common *common, u16 tid,
0718 u16 ssn, u8 buf_size, u8 event,
0719 u8 sta_id);
0720 int rsi_hal_load_key(struct rsi_common *common, u8 *data, u16 key_len,
0721 u8 key_type, u8 key_id, u32 cipher, s16 sta_id,
0722 struct ieee80211_vif *vif);
0723 int rsi_set_channel(struct rsi_common *common,
0724 struct ieee80211_channel *channel);
0725 int rsi_send_vap_dynamic_update(struct rsi_common *common);
0726 int rsi_send_block_unblock_frame(struct rsi_common *common, bool event);
0727 int rsi_hal_send_sta_notify_frame(struct rsi_common *common, enum opmode opmode,
0728 u8 notify_event, const unsigned char *bssid,
0729 u8 qos_enable, u16 aid, u16 sta_id,
0730 struct ieee80211_vif *vif);
0731 void rsi_inform_bss_status(struct rsi_common *common, enum opmode opmode,
0732 u8 status, const u8 *addr, u8 qos_enable, u16 aid,
0733 struct ieee80211_sta *sta, u16 sta_id,
0734 u16 assoc_cap, struct ieee80211_vif *vif);
0735 void rsi_indicate_pkt_to_os(struct rsi_common *common, struct sk_buff *skb);
0736 int rsi_mac80211_attach(struct rsi_common *common);
0737 void rsi_indicate_tx_status(struct rsi_hw *common, struct sk_buff *skb,
0738 int status);
0739 bool rsi_is_cipher_wep(struct rsi_common *common);
0740 void rsi_core_qos_processor(struct rsi_common *common);
0741 void rsi_core_xmit(struct rsi_common *common, struct sk_buff *skb);
0742 int rsi_send_mgmt_pkt(struct rsi_common *common, struct sk_buff *skb);
0743 int rsi_send_data_pkt(struct rsi_common *common, struct sk_buff *skb);
0744 int rsi_band_check(struct rsi_common *common, struct ieee80211_channel *chan);
0745 int rsi_send_rx_filter_frame(struct rsi_common *common, u16 rx_filter_word);
0746 int rsi_send_radio_params_update(struct rsi_common *common);
0747 int rsi_set_antenna(struct rsi_common *common, u8 antenna);
0748 #ifdef CONFIG_PM
0749 int rsi_send_wowlan_request(struct rsi_common *common, u16 flags,
0750 u16 sleep_status);
0751 #endif
0752 int rsi_send_ps_request(struct rsi_hw *adapter, bool enable,
0753 struct ieee80211_vif *vif);
0754 void init_bgscan_params(struct rsi_common *common);
0755 int rsi_send_bgscan_params(struct rsi_common *common, int enable);
0756 int rsi_send_bgscan_probe_req(struct rsi_common *common,
0757 struct ieee80211_vif *vif);
0758 #endif