wireless/rsi/rsi_hal.h

0001 /*
0002  * Copyright (c) 2017 Redpine Signals Inc.
0003  *
0004  * Permission to use, copy, modify, and/or distribute this software for any
0005  * purpose with or without fee is hereby granted, provided that the above
0006  * copyright notice and this permission notice appear in all copies.
0007  *
0008  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
0009  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
0010  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
0011  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
0012  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
0013  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
0014  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
0015  */
0016
0017 #ifndef __RSI_HAL_H__
0018 #define __RSI_HAL_H__
0019
0020 /* Device Operating modes */
0021 #define DEV_OPMODE_WIFI_ALONE       1
0022 #define DEV_OPMODE_BT_ALONE     4
0023 #define DEV_OPMODE_BT_LE_ALONE      8
0024 #define DEV_OPMODE_BT_DUAL      12
0025 #define DEV_OPMODE_STA_BT       5
0026 #define DEV_OPMODE_STA_BT_LE        9
0027 #define DEV_OPMODE_STA_BT_DUAL      13
0028 #define DEV_OPMODE_AP_BT        6
0029 #define DEV_OPMODE_AP_BT_DUAL       14
0030
0031 #define DEV_OPMODE_PARAM_DESC       \
0032     __stringify(DEV_OPMODE_WIFI_ALONE)  "[Wi-Fi alone], "   \
0033     __stringify(DEV_OPMODE_BT_ALONE)    "[BT classic alone], "  \
0034     __stringify(DEV_OPMODE_BT_LE_ALONE) "[BT LE alone], "   \
0035     __stringify(DEV_OPMODE_BT_DUAL)     "[BT classic + BT LE alone], " \
0036     __stringify(DEV_OPMODE_STA_BT)      "[Wi-Fi STA + BT classic], " \
0037     __stringify(DEV_OPMODE_STA_BT_LE)   "[Wi-Fi STA + BT LE], " \
0038     __stringify(DEV_OPMODE_STA_BT_DUAL) "[Wi-Fi STA + BT classic + BT LE], " \
0039     __stringify(DEV_OPMODE_AP_BT)       "[Wi-Fi AP + BT classic], " \
0040     __stringify(DEV_OPMODE_AP_BT_DUAL)  "[Wi-Fi AP + BT classic + BT LE]"
0041
0042 #define FLASH_WRITE_CHUNK_SIZE      (4 * 1024)
0043 #define FLASH_SECTOR_SIZE       (4 * 1024)
0044
0045 #define FLASH_SIZE_ADDR         0x04000016
0046 #define PING_BUFFER_ADDRESS     0x19000
0047 #define PONG_BUFFER_ADDRESS     0x1a000
0048 #define SWBL_REGIN          0x41050034
0049 #define SWBL_REGOUT         0x4105003c
0050 #define PING_WRITE          0x1
0051 #define PONG_WRITE          0x2
0052
0053 #define BL_CMD_TIMEOUT          2000
0054 #define BL_BURN_TIMEOUT         (50 * 1000)
0055
0056 #define REGIN_VALID         0xA
0057 #define REGIN_INPUT         0xA0
0058 #define REGOUT_VALID            0xAB
0059 #define REGOUT_INVALID          (~0xAB)
0060 #define CMD_PASS            0xAA
0061 #define CMD_FAIL            0xCC
0062
0063 #define LOAD_HOSTED_FW          'A'
0064 #define BURN_HOSTED_FW          'B'
0065 #define PING_VALID          'I'
0066 #define PONG_VALID          'O'
0067 #define PING_AVAIL          'I'
0068 #define PONG_AVAIL          'O'
0069 #define EOF_REACHED         'E'
0070 #define CHECK_CRC           'K'
0071 #define POLLING_MODE            'P'
0072 #define CONFIG_AUTO_READ_MODE       'R'
0073 #define JUMP_TO_ZERO_PC         'J'
0074 #define FW_LOADING_SUCCESSFUL       'S'
0075 #define LOADING_INITIATED       '1'
0076
0077 #define RSI_ULP_RESET_REG       0x161
0078 #define RSI_WATCH_DOG_TIMER_1       0x16c
0079 #define RSI_WATCH_DOG_TIMER_2       0x16d
0080 #define RSI_WATCH_DOG_DELAY_TIMER_1     0x16e
0081 #define RSI_WATCH_DOG_DELAY_TIMER_2     0x16f
0082 #define RSI_WATCH_DOG_TIMER_ENABLE      0x170
0083
0084 /* Watchdog timer addresses for 9116 */
0085 #define NWP_AHB_BASE_ADDR       0x41300000
0086 #define NWP_WWD_INTERRUPT_TIMER     (NWP_AHB_BASE_ADDR + 0x300)
0087 #define NWP_WWD_SYSTEM_RESET_TIMER  (NWP_AHB_BASE_ADDR + 0x304)
0088 #define NWP_WWD_WINDOW_TIMER        (NWP_AHB_BASE_ADDR + 0x308)
0089 #define NWP_WWD_TIMER_SETTINGS      (NWP_AHB_BASE_ADDR + 0x30C)
0090 #define NWP_WWD_MODE_AND_RSTART     (NWP_AHB_BASE_ADDR + 0x310)
0091 #define NWP_WWD_RESET_BYPASS        (NWP_AHB_BASE_ADDR + 0x314)
0092 #define NWP_FSM_INTR_MASK_REG       (NWP_AHB_BASE_ADDR + 0x104)
0093
0094 /* Watchdog timer values */
0095 #define NWP_WWD_INT_TIMER_CLKS      5
0096 #define NWP_WWD_SYS_RESET_TIMER_CLKS    4
0097 #define NWP_WWD_TIMER_DISABLE       0xAA0001
0098
0099 #define RSI_ULP_WRITE_0         00
0100 #define RSI_ULP_WRITE_2         02
0101 #define RSI_ULP_WRITE_50        50
0102
0103 #define RSI_RESTART_WDT         BIT(11)
0104 #define RSI_BYPASS_ULP_ON_WDT       BIT(1)
0105
0106 #define RSI_ULP_TIMER_ENABLE        ((0xaa000) | RSI_RESTART_WDT |  \
0107                      RSI_BYPASS_ULP_ON_WDT)
0108 #define RSI_RF_SPI_PROG_REG_BASE_ADDR   0x40080000
0109
0110 #define RSI_GSPI_CTRL_REG0      (RSI_RF_SPI_PROG_REG_BASE_ADDR)
0111 #define RSI_GSPI_CTRL_REG1      (RSI_RF_SPI_PROG_REG_BASE_ADDR + 0x2)
0112 #define RSI_GSPI_DATA_REG0      (RSI_RF_SPI_PROG_REG_BASE_ADDR + 0x4)
0113 #define RSI_GSPI_DATA_REG1      (RSI_RF_SPI_PROG_REG_BASE_ADDR + 0x6)
0114 #define RSI_GSPI_DATA_REG2      (RSI_RF_SPI_PROG_REG_BASE_ADDR + 0x8)
0115
0116 #define RSI_GSPI_CTRL_REG0_VALUE        0x340
0117
0118 #define RSI_GSPI_DMA_MODE           BIT(13)
0119
0120 #define RSI_GSPI_2_ULP          BIT(12)
0121 #define RSI_GSPI_TRIG           BIT(7)
0122 #define RSI_GSPI_READ           BIT(6)
0123 #define RSI_GSPI_RF_SPI_ACTIVE      BIT(8)
0124
0125 /* Boot loader commands */
0126 #define SEND_RPS_FILE           '2'
0127
0128 #define FW_IMAGE_MIN_ADDRESS        (68 * 1024)
0129 #define MAX_FLASH_FILE_SIZE     (400 * 1024) //400K
0130 #define FLASH_START_ADDRESS     16
0131
0132 #define COMMON_HAL_CARD_READY_IND   0x0
0133
0134 #define COMMAN_HAL_WAIT_FOR_CARD_READY  1
0135
0136 #define RSI_DEV_OPMODE_WIFI_ALONE   1
0137 #define RSI_DEV_COEX_MODE_WIFI_ALONE    1
0138
0139 #define BBP_INFO_40MHZ 0x6
0140
0141 #define FW_FLASH_OFFSET         0x820
0142 #define LMAC_VER_OFFSET_9113        (FW_FLASH_OFFSET + 0x200)
0143 #define LMAC_VER_OFFSET_9116        0x22C2
0144 #define MAX_DWORD_ALIGN_BYTES       64
0145 #define RSI_COMMON_REG_SIZE     2
0146 #define RSI_9116_REG_SIZE       4
0147 #define FW_ALIGN_SIZE           4
0148 #define RSI_9116_FW_MAGIC_WORD      0x5aa5
0149
0150 #define MEM_ACCESS_CTRL_FROM_HOST   0x41300000
0151 #define RAM_384K_ACCESS_FROM_TA     (BIT(2) | BIT(3) | BIT(4) | BIT(5) | \
0152                      BIT(20) | BIT(21) | BIT(22) | \
0153                      BIT(23) | BIT(24) | BIT(25))
0154
0155 struct bl_header {
0156     __le32 flags;
0157     __le32 image_no;
0158     __le32 check_sum;
0159     __le32 flash_start_address;
0160     __le32 flash_len;
0161 } __packed;
0162
0163 struct ta_metadata {
0164     char *name;
0165     unsigned int address;
0166 };
0167
0168 #define RSI_BL_CTRL_LEN_MASK            0xFFFFFF
0169 #define RSI_BL_CTRL_SPI_32BIT_MODE      BIT(27)
0170 #define RSI_BL_CTRL_REL_TA_SOFTRESET        BIT(28)
0171 #define RSI_BL_CTRL_START_FROM_ROM_PC       BIT(29)
0172 #define RSI_BL_CTRL_SPI_8BIT_MODE       BIT(30)
0173 #define RSI_BL_CTRL_LAST_ENTRY          BIT(31)
0174 struct bootload_entry {
0175     __le32 control;
0176     __le32 dst_addr;
0177 } __packed;
0178
0179 struct bootload_ds {
0180     __le16 fixed_pattern;
0181     __le16 offset;
0182     __le32 reserved;
0183     struct bootload_entry bl_entry[7];
0184 } __packed;
0185
0186 struct rsi_mgmt_desc {
0187     __le16 len_qno;
0188     u8 frame_type;
0189     u8 misc_flags;
0190     u8 xtend_desc_size;
0191     u8 header_len;
0192     __le16 frame_info;
0193     __le16 rate_info;
0194     __le16 bbp_info;
0195     __le16 seq_ctrl;
0196     u8 reserved2;
0197     u8 sta_id;
0198 } __packed;
0199
0200 struct rsi_data_desc {
0201     __le16 len_qno;
0202     u8 cfm_frame_type;
0203     u8 misc_flags;
0204     u8 xtend_desc_size;
0205     u8 header_len;
0206     __le16 frame_info;
0207     __le16 rate_info;
0208     __le16 bbp_info;
0209     __le16 mac_flags;
0210     u8 qid_tid;
0211     u8 sta_id;
0212 } __packed;
0213
0214 struct rsi_bt_desc {
0215     __le16 len_qno;
0216     __le16 reserved1;
0217     __le32 reserved2;
0218     __le32 reserved3;
0219     __le16 reserved4;
0220     __le16 bt_pkt_type;
0221 } __packed;
0222
0223 int rsi_hal_device_init(struct rsi_hw *adapter);
0224 int rsi_prepare_mgmt_desc(struct rsi_common *common, struct sk_buff *skb);
0225 int rsi_prepare_data_desc(struct rsi_common *common, struct sk_buff *skb);
0226 int rsi_prepare_beacon(struct rsi_common *common, struct sk_buff *skb);
0227 int rsi_send_pkt_to_bus(struct rsi_common *common, struct sk_buff *skb);
0228 int rsi_send_bt_pkt(struct rsi_common *common, struct sk_buff *skb);
0229
0230 #endif