wireless/rsi/rsi_boot_params.h

0001 /*
0002  * Copyright (c) 2014 Redpine Signals Inc.
0003  *
0004  * Permission to use, copy, modify, and/or distribute this software for any
0005  * purpose with or without fee is hereby granted, provided that the above
0006  * copyright notice and this permission notice appear in all copies.
0007  *
0008  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
0009  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
0010  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
0011  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
0012  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
0013  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
0014  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
0015  */
0016
0017 #ifndef __RSI_BOOTPARAMS_HEADER_H__
0018 #define __RSI_BOOTPARAMS_HEADER_H__
0019
0020 #define CRYSTAL_GOOD_TIME                BIT(0)
0021 #define BOOTUP_MODE_INFO                 BIT(1)
0022 #define WIFI_TAPLL_CONFIGS               BIT(5)
0023 #define WIFI_PLL960_CONFIGS              BIT(6)
0024 #define WIFI_AFEPLL_CONFIGS              BIT(7)
0025 #define WIFI_SWITCH_CLK_CONFIGS          BIT(8)
0026
0027 #define TA_PLL_M_VAL_20                  9
0028 #define TA_PLL_N_VAL_20                  0
0029 #define TA_PLL_P_VAL_20                  4
0030
0031 #define PLL960_M_VAL_20                  0x14
0032 #define PLL960_N_VAL_20                  0
0033 #define PLL960_P_VAL_20                  5
0034
0035 #define UMAC_CLK_40MHZ                   80
0036
0037 #define TA_PLL_M_VAL_40                  9
0038 #define TA_PLL_N_VAL_40                  0
0039 #define TA_PLL_P_VAL_40                  4
0040
0041 #define PLL960_M_VAL_40                  0x14
0042 #define PLL960_N_VAL_40                  0
0043 #define PLL960_P_VAL_40                  5
0044
0045 #define UMAC_CLK_20BW \
0046     (((TA_PLL_M_VAL_20 + 1) * 40) / \
0047      ((TA_PLL_N_VAL_20 + 1) * (TA_PLL_P_VAL_20 + 1)))
0048 #define VALID_20 \
0049     (WIFI_TAPLL_CONFIGS | WIFI_PLL960_CONFIGS | WIFI_AFEPLL_CONFIGS | \
0050      WIFI_SWITCH_CLK_CONFIGS | BOOTUP_MODE_INFO | CRYSTAL_GOOD_TIME)
0051 #define UMAC_CLK_40BW   \
0052     (((TA_PLL_M_VAL_40 + 1) * 40) / \
0053      ((TA_PLL_N_VAL_40 + 1) * (TA_PLL_P_VAL_40 + 1)))
0054 #define VALID_40 \
0055     (WIFI_PLL960_CONFIGS | WIFI_AFEPLL_CONFIGS | WIFI_SWITCH_CLK_CONFIGS | \
0056      WIFI_TAPLL_CONFIGS | CRYSTAL_GOOD_TIME | BOOTUP_MODE_INFO)
0057
0058 /* structure to store configs related to TAPLL programming */
0059 struct tapll_info {
0060     __le16 pll_reg_1;
0061     __le16 pll_reg_2;
0062 } __packed;
0063
0064 /* structure to store configs related to PLL960 programming */
0065 struct pll960_info {
0066     __le16 pll_reg_1;
0067     __le16 pll_reg_2;
0068     __le16 pll_reg_3;
0069 } __packed;
0070
0071 /* structure to store configs related to AFEPLL programming */
0072 struct afepll_info {
0073     __le16 pll_reg;
0074 } __packed;
0075
0076 /* structure to store configs related to pll configs */
0077 struct pll_config {
0078     struct tapll_info tapll_info_g;
0079     struct pll960_info pll960_info_g;
0080     struct afepll_info afepll_info_g;
0081 } __packed;
0082
0083 struct pll_config_9116 {
0084     __le16 pll_ctrl_set_reg;
0085     __le16 pll_ctrl_clr_reg;
0086     __le16 pll_modem_conig_reg;
0087     __le16 soc_clk_config_reg;
0088     __le16 adc_dac_strm1_config_reg;
0089     __le16 adc_dac_strm2_config_reg;
0090 } __packed;
0091
0092 /* structure to store configs related to UMAC clk programming */
0093 struct switch_clk {
0094     __le16 switch_clk_info;
0095     /* If switch_bbp_lmac_clk_reg is set then this value will be programmed
0096      * into reg
0097      */
0098     __le16 bbp_lmac_clk_reg_val;
0099     /* if switch_umac_clk is set then this value will be programmed */
0100     __le16 umac_clock_reg_config;
0101     /* if switch_qspi_clk is set then this value will be programmed */
0102     __le16 qspi_uart_clock_reg_config;
0103 } __packed;
0104
0105 #define RSI_SWITCH_TASS_CLK         BIT(0)
0106 #define RSI_SWITCH_QSPI_CLK         BIT(1)
0107 #define RSI_SWITCH_SLP_CLK_2_32         BIT(2)
0108 #define RSI_SWITCH_WLAN_BBP_LMAC_CLK_REG    BIT(3)
0109 #define RSI_SWITCH_ZBBT_BBP_LMAC_CLK_REG    BIT(4)
0110 #define RSI_SWITCH_BBP_LMAC_CLK_REG     BIT(5)
0111 #define RSI_MODEM_CLK_160MHZ            BIT(6)
0112
0113 struct switch_clk_9116 {
0114     __le32 switch_clk_info;
0115     __le32 tass_clock_reg;
0116     __le32 wlan_bbp_lmac_clk_reg_val;
0117     __le32 zbbt_bbp_lmac_clk_reg_val;
0118     __le32 bbp_lmac_clk_en_val;
0119 } __packed;
0120
0121 struct device_clk_info {
0122     struct pll_config pll_config_g;
0123     struct switch_clk switch_clk_g;
0124 } __packed;
0125
0126 struct device_clk_info_9116 {
0127     struct pll_config_9116 pll_config_9116_g;
0128     struct switch_clk_9116 switch_clk_9116_g;
0129 } __packed;
0130
0131 struct bootup_params {
0132     __le16 magic_number;
0133     __le16 crystal_good_time;
0134     __le32 valid;
0135     __le32 reserved_for_valids;
0136     __le16 bootup_mode_info;
0137     /* configuration used for digital loop back */
0138     __le16 digital_loop_back_params;
0139     __le16 rtls_timestamp_en;
0140     __le16 host_spi_intr_cfg;
0141     struct device_clk_info device_clk_info[3];
0142     /* ulp buckboost wait time  */
0143     __le32 buckboost_wakeup_cnt;
0144     /* pmu wakeup wait time & WDT EN info */
0145     __le16 pmu_wakeup_wait;
0146     u8 shutdown_wait_time;
0147     /* Sleep clock source selection */
0148     u8 pmu_slp_clkout_sel;
0149     /* WDT programming values */
0150     __le32 wdt_prog_value;
0151     /* WDT soc reset delay */
0152     __le32 wdt_soc_rst_delay;
0153     /* dcdc modes configs */
0154     __le32 dcdc_operation_mode;
0155     __le32 soc_reset_wait_cnt;
0156     __le32 waiting_time_at_fresh_sleep;
0157     __le32 max_threshold_to_avoid_sleep;
0158     u8 beacon_resedue_alg_en;
0159 } __packed;
0160
0161 struct bootup_params_9116 {
0162     __le16 magic_number;
0163 #define LOADED_TOKEN  0x5AA5   /* Bootup params are installed by host
0164                 * or OTP/FLASH (Bootloader)
0165                 */
0166 #define ROM_TOKEN     0x55AA   /* Bootup params are taken from ROM
0167                 * itself in MCU mode.
0168                 */
0169     __le16 crystal_good_time;
0170     __le32 valid;
0171     __le32 reserved_for_valids;
0172     __le16 bootup_mode_info;
0173 #define BT_COEXIST      BIT(0)
0174 #define BOOTUP_MODE     (BIT(2) | BIT(1))
0175 #define CUR_DEV_MODE_9116   (bootup_params_9116.bootup_mode_info >> 1)
0176     __le16 digital_loop_back_params;
0177     __le16 rtls_timestamp_en;
0178     __le16 host_spi_intr_cfg;
0179     struct device_clk_info_9116 device_clk_info_9116[1];
0180     __le32 buckboost_wakeup_cnt;
0181     __le16 pmu_wakeup_wait;
0182     u8 shutdown_wait_time;
0183     u8 pmu_slp_clkout_sel;
0184     __le32 wdt_prog_value;
0185     __le32 wdt_soc_rst_delay;
0186     __le32 dcdc_operation_mode;
0187     __le32 soc_reset_wait_cnt;
0188     __le32 waiting_time_at_fresh_sleep;
0189     __le32 max_threshold_to_avoid_sleep;
0190     u8 beacon_resedue_alg_en;
0191 } __packed;
0192
0193 #endif