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0018 #include <linux/firmware.h>
0019 #include <net/rsi_91x.h>
0020 #include "rsi_sdio.h"
0021 #include "rsi_common.h"
0022
0023
0024
0025
0026
0027
0028
0029
0030
0031 int rsi_sdio_master_access_msword(struct rsi_hw *adapter, u16 ms_word)
0032 {
0033 u8 byte;
0034 u8 function = 0;
0035 int status = 0;
0036
0037 byte = (u8)(ms_word & 0x00FF);
0038
0039 rsi_dbg(INIT_ZONE,
0040 "%s: MASTER_ACCESS_MSBYTE:0x%x\n", __func__, byte);
0041
0042 status = rsi_sdio_write_register(adapter,
0043 function,
0044 SDIO_MASTER_ACCESS_MSBYTE,
0045 &byte);
0046 if (status) {
0047 rsi_dbg(ERR_ZONE,
0048 "%s: fail to access MASTER_ACCESS_MSBYTE\n",
0049 __func__);
0050 return -1;
0051 }
0052
0053 byte = (u8)(ms_word >> 8);
0054
0055 rsi_dbg(INIT_ZONE, "%s:MASTER_ACCESS_LSBYTE:0x%x\n", __func__, byte);
0056 status = rsi_sdio_write_register(adapter,
0057 function,
0058 SDIO_MASTER_ACCESS_LSBYTE,
0059 &byte);
0060 return status;
0061 }
0062
0063 static void rsi_rx_handler(struct rsi_hw *adapter);
0064
0065 void rsi_sdio_rx_thread(struct rsi_common *common)
0066 {
0067 struct rsi_hw *adapter = common->priv;
0068 struct rsi_91x_sdiodev *sdev = adapter->rsi_dev;
0069
0070 do {
0071 rsi_wait_event(&sdev->rx_thread.event, EVENT_WAIT_FOREVER);
0072 rsi_reset_event(&sdev->rx_thread.event);
0073 rsi_rx_handler(adapter);
0074 } while (!atomic_read(&sdev->rx_thread.thread_done));
0075
0076 rsi_dbg(INFO_ZONE, "%s: Terminated SDIO RX thread\n", __func__);
0077 atomic_inc(&sdev->rx_thread.thread_done);
0078 kthread_complete_and_exit(&sdev->rx_thread.completion, 0);
0079 }
0080
0081
0082
0083
0084
0085
0086
0087
0088 static int rsi_process_pkt(struct rsi_common *common)
0089 {
0090 struct rsi_hw *adapter = common->priv;
0091 struct rsi_91x_sdiodev *dev =
0092 (struct rsi_91x_sdiodev *)adapter->rsi_dev;
0093 u8 num_blks = 0;
0094 u32 rcv_pkt_len = 0;
0095 int status = 0;
0096 u8 value = 0;
0097
0098 num_blks = ((adapter->interrupt_status & 1) |
0099 ((adapter->interrupt_status >> RECV_NUM_BLOCKS) << 1));
0100
0101 if (!num_blks) {
0102 status = rsi_sdio_read_register(adapter,
0103 SDIO_RX_NUM_BLOCKS_REG,
0104 &value);
0105 if (status) {
0106 rsi_dbg(ERR_ZONE,
0107 "%s: Failed to read pkt length from the card:\n",
0108 __func__);
0109 return status;
0110 }
0111 num_blks = value & 0x1f;
0112 }
0113
0114 if (dev->write_fail == 2)
0115 rsi_sdio_ack_intr(common->priv, (1 << MSDU_PKT_PENDING));
0116
0117 if (unlikely(!num_blks)) {
0118 dev->write_fail = 2;
0119 return -1;
0120 }
0121
0122 rcv_pkt_len = (num_blks * 256);
0123
0124 status = rsi_sdio_host_intf_read_pkt(adapter, dev->pktbuffer,
0125 rcv_pkt_len);
0126 if (status) {
0127 rsi_dbg(ERR_ZONE, "%s: Failed to read packet from card\n",
0128 __func__);
0129 return status;
0130 }
0131
0132 status = rsi_read_pkt(common, dev->pktbuffer, rcv_pkt_len);
0133 if (status) {
0134 rsi_dbg(ERR_ZONE, "Failed to read the packet\n");
0135 return status;
0136 }
0137
0138 return 0;
0139 }
0140
0141
0142
0143
0144
0145
0146
0147
0148 int rsi_init_sdio_slave_regs(struct rsi_hw *adapter)
0149 {
0150 struct rsi_91x_sdiodev *dev =
0151 (struct rsi_91x_sdiodev *)adapter->rsi_dev;
0152 u8 function = 0;
0153 u8 byte;
0154 int status = 0;
0155
0156 if (dev->next_read_delay) {
0157 byte = dev->next_read_delay;
0158 status = rsi_sdio_write_register(adapter,
0159 function,
0160 SDIO_NXT_RD_DELAY2,
0161 &byte);
0162 if (status) {
0163 rsi_dbg(ERR_ZONE,
0164 "%s: Failed to write SDIO_NXT_RD_DELAY2\n",
0165 __func__);
0166 return -1;
0167 }
0168 }
0169
0170 if (dev->sdio_high_speed_enable) {
0171 rsi_dbg(INIT_ZONE, "%s: Enabling SDIO High speed\n", __func__);
0172 byte = 0x3;
0173
0174 status = rsi_sdio_write_register(adapter,
0175 function,
0176 SDIO_REG_HIGH_SPEED,
0177 &byte);
0178 if (status) {
0179 rsi_dbg(ERR_ZONE,
0180 "%s: Failed to enable SDIO high speed\n",
0181 __func__);
0182 return -1;
0183 }
0184 }
0185
0186
0187 rsi_dbg(INIT_ZONE, "%s: Initializing SDIO read start level\n", __func__);
0188 byte = 0x24;
0189
0190 status = rsi_sdio_write_register(adapter,
0191 function,
0192 SDIO_READ_START_LVL,
0193 &byte);
0194 if (status) {
0195 rsi_dbg(ERR_ZONE,
0196 "%s: Failed to write SDIO_READ_START_LVL\n", __func__);
0197 return -1;
0198 }
0199
0200 rsi_dbg(INIT_ZONE, "%s: Initializing FIFO ctrl registers\n", __func__);
0201 byte = (128 - 32);
0202
0203 status = rsi_sdio_write_register(adapter,
0204 function,
0205 SDIO_READ_FIFO_CTL,
0206 &byte);
0207 if (status) {
0208 rsi_dbg(ERR_ZONE,
0209 "%s: Failed to write SDIO_READ_FIFO_CTL\n", __func__);
0210 return -1;
0211 }
0212
0213 byte = 32;
0214 status = rsi_sdio_write_register(adapter,
0215 function,
0216 SDIO_WRITE_FIFO_CTL,
0217 &byte);
0218 if (status) {
0219 rsi_dbg(ERR_ZONE,
0220 "%s: Failed to write SDIO_WRITE_FIFO_CTL\n", __func__);
0221 return -1;
0222 }
0223
0224 return 0;
0225 }
0226
0227
0228
0229
0230
0231
0232
0233 static void rsi_rx_handler(struct rsi_hw *adapter)
0234 {
0235 struct rsi_common *common = adapter->priv;
0236 struct rsi_91x_sdiodev *dev =
0237 (struct rsi_91x_sdiodev *)adapter->rsi_dev;
0238 int status;
0239 u8 isr_status = 0;
0240 u8 fw_status = 0;
0241
0242 dev->rx_info.sdio_int_counter++;
0243
0244 do {
0245 mutex_lock(&common->rx_lock);
0246 status = rsi_sdio_read_register(common->priv,
0247 RSI_FN1_INT_REGISTER,
0248 &isr_status);
0249 if (status) {
0250 rsi_dbg(ERR_ZONE,
0251 "%s: Failed to Read Intr Status Register\n",
0252 __func__);
0253 mutex_unlock(&common->rx_lock);
0254 return;
0255 }
0256 adapter->interrupt_status = isr_status;
0257
0258 if (isr_status == 0) {
0259 rsi_set_event(&common->tx_thread.event);
0260 dev->rx_info.sdio_intr_status_zero++;
0261 mutex_unlock(&common->rx_lock);
0262 return;
0263 }
0264
0265 rsi_dbg(ISR_ZONE, "%s: Intr_status = %x %d %d\n",
0266 __func__, isr_status, (1 << MSDU_PKT_PENDING),
0267 (1 << FW_ASSERT_IND));
0268
0269 if (isr_status & BIT(PKT_BUFF_AVAILABLE)) {
0270 status = rsi_sdio_check_buffer_status(adapter, 0);
0271 if (status < 0)
0272 rsi_dbg(ERR_ZONE,
0273 "%s: Failed to check buffer status\n",
0274 __func__);
0275 rsi_sdio_ack_intr(common->priv,
0276 BIT(PKT_BUFF_AVAILABLE));
0277 rsi_set_event(&common->tx_thread.event);
0278
0279 rsi_dbg(ISR_ZONE, "%s: ==> BUFFER_AVAILABLE <==\n",
0280 __func__);
0281 dev->buff_status_updated = true;
0282
0283 isr_status &= ~BIT(PKT_BUFF_AVAILABLE);
0284 }
0285
0286 if (isr_status & BIT(FW_ASSERT_IND)) {
0287 rsi_dbg(ERR_ZONE, "%s: ==> FIRMWARE Assert <==\n",
0288 __func__);
0289 status = rsi_sdio_read_register(common->priv,
0290 SDIO_FW_STATUS_REG,
0291 &fw_status);
0292 if (status) {
0293 rsi_dbg(ERR_ZONE,
0294 "%s: Failed to read f/w reg\n",
0295 __func__);
0296 } else {
0297 rsi_dbg(ERR_ZONE,
0298 "%s: Firmware Status is 0x%x\n",
0299 __func__, fw_status);
0300 rsi_sdio_ack_intr(common->priv,
0301 BIT(FW_ASSERT_IND));
0302 }
0303
0304 common->fsm_state = FSM_CARD_NOT_READY;
0305
0306 isr_status &= ~BIT(FW_ASSERT_IND);
0307 }
0308
0309 if (isr_status & BIT(MSDU_PKT_PENDING)) {
0310 rsi_dbg(ISR_ZONE, "Pkt pending interrupt\n");
0311 dev->rx_info.total_sdio_msdu_pending_intr++;
0312
0313 status = rsi_process_pkt(common);
0314 if (status) {
0315 rsi_dbg(ERR_ZONE, "%s: Failed to read pkt\n",
0316 __func__);
0317 mutex_unlock(&common->rx_lock);
0318 return;
0319 }
0320
0321 isr_status &= ~BIT(MSDU_PKT_PENDING);
0322 }
0323
0324 if (isr_status) {
0325 rsi_sdio_ack_intr(common->priv, isr_status);
0326 dev->rx_info.total_sdio_unknown_intr++;
0327 isr_status = 0;
0328 rsi_dbg(ISR_ZONE, "Unknown Interrupt %x\n",
0329 isr_status);
0330 }
0331
0332 mutex_unlock(&common->rx_lock);
0333 } while (1);
0334 }
0335
0336
0337
0338
0339 int rsi_sdio_check_buffer_status(struct rsi_hw *adapter, u8 q_num)
0340 {
0341 struct rsi_common *common = adapter->priv;
0342 struct rsi_91x_sdiodev *dev =
0343 (struct rsi_91x_sdiodev *)adapter->rsi_dev;
0344 u8 buf_status = 0;
0345 int status = 0;
0346 static int counter = 4;
0347
0348 if (!dev->buff_status_updated && counter) {
0349 counter--;
0350 goto out;
0351 }
0352
0353 dev->buff_status_updated = false;
0354 status = rsi_sdio_read_register(common->priv,
0355 RSI_DEVICE_BUFFER_STATUS_REGISTER,
0356 &buf_status);
0357
0358 if (status) {
0359 rsi_dbg(ERR_ZONE,
0360 "%s: Failed to read status register\n", __func__);
0361 return -1;
0362 }
0363
0364 if (buf_status & (BIT(PKT_MGMT_BUFF_FULL))) {
0365 if (!dev->rx_info.mgmt_buffer_full)
0366 dev->rx_info.mgmt_buf_full_counter++;
0367 dev->rx_info.mgmt_buffer_full = true;
0368 } else {
0369 dev->rx_info.mgmt_buffer_full = false;
0370 }
0371
0372 if (buf_status & (BIT(PKT_BUFF_FULL))) {
0373 if (!dev->rx_info.buffer_full)
0374 dev->rx_info.buf_full_counter++;
0375 dev->rx_info.buffer_full = true;
0376 } else {
0377 dev->rx_info.buffer_full = false;
0378 }
0379
0380 if (buf_status & (BIT(PKT_BUFF_SEMI_FULL))) {
0381 if (!dev->rx_info.semi_buffer_full)
0382 dev->rx_info.buf_semi_full_counter++;
0383 dev->rx_info.semi_buffer_full = true;
0384 } else {
0385 dev->rx_info.semi_buffer_full = false;
0386 }
0387
0388 if (dev->rx_info.mgmt_buffer_full || dev->rx_info.buf_full_counter)
0389 counter = 1;
0390 else
0391 counter = 4;
0392
0393 out:
0394 if ((q_num == MGMT_SOFT_Q) && (dev->rx_info.mgmt_buffer_full))
0395 return QUEUE_FULL;
0396
0397 if ((q_num < MGMT_SOFT_Q) && (dev->rx_info.buffer_full))
0398 return QUEUE_FULL;
0399
0400 return QUEUE_NOT_FULL;
0401 }
0402
0403
0404
0405
0406
0407
0408
0409
0410 int rsi_sdio_determine_event_timeout(struct rsi_hw *adapter)
0411 {
0412 struct rsi_91x_sdiodev *dev =
0413 (struct rsi_91x_sdiodev *)adapter->rsi_dev;
0414
0415
0416 if (dev->rx_info.buffer_full)
0417 return 2;
0418
0419 return EVENT_WAIT_FOREVER;
0420 }