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OSCL-LXR
 
 

     

0001 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
0002 /* Copyright(c) 2020  Realtek Corporation
0003  */
0004 
0005 #ifndef __RTW89_TXRX_H__
0006 #define __RTW89_TXRX_H__
0007 
0008 #include "debug.h"
0009 
0010 #define DATA_RATE_MODE_CTRL_MASK    GENMASK(8, 7)
0011 #define DATA_RATE_NOT_HT_IDX_MASK   GENMASK(3, 0)
0012 #define DATA_RATE_MODE_NON_HT       0x0
0013 #define DATA_RATE_HT_IDX_MASK       GENMASK(4, 0)
0014 #define DATA_RATE_MODE_HT       0x1
0015 #define DATA_RATE_VHT_HE_NSS_MASK   GENMASK(6, 4)
0016 #define DATA_RATE_VHT_HE_IDX_MASK   GENMASK(3, 0)
0017 #define DATA_RATE_MODE_VHT      0x2
0018 #define DATA_RATE_MODE_HE       0x3
0019 #define GET_DATA_RATE_MODE(r)       FIELD_GET(DATA_RATE_MODE_CTRL_MASK, r)
0020 #define GET_DATA_RATE_NOT_HT_IDX(r) FIELD_GET(DATA_RATE_NOT_HT_IDX_MASK, r)
0021 #define GET_DATA_RATE_HT_IDX(r)     FIELD_GET(DATA_RATE_HT_IDX_MASK, r)
0022 #define GET_DATA_RATE_VHT_HE_IDX(r) FIELD_GET(DATA_RATE_VHT_HE_IDX_MASK, r)
0023 #define GET_DATA_RATE_NSS(r)        FIELD_GET(DATA_RATE_VHT_HE_NSS_MASK, r)
0024 
0025 /* TX WD BODY DWORD 0 */
0026 #define RTW89_TXWD_BODY0_WP_OFFSET GENMASK(31, 24)
0027 #define RTW89_TXWD_BODY0_WP_OFFSET_V1 GENMASK(28, 24)
0028 #define RTW89_TXWD_BODY0_MORE_DATA BIT(23)
0029 #define RTW89_TXWD_BODY0_WD_INFO_EN BIT(22)
0030 #define RTW89_TXWD_BODY0_FW_DL BIT(20)
0031 #define RTW89_TXWD_BODY0_CHANNEL_DMA GENMASK(19, 16)
0032 #define RTW89_TXWD_BODY0_HDR_LLC_LEN GENMASK(15, 11)
0033 #define RTW89_TXWD_BODY0_WD_PAGE BIT(7)
0034 #define RTW89_TXWD_BODY0_HW_AMSDU BIT(5)
0035 #define RTW89_TXWD_BODY0_HW_SSN_SEL GENMASK(3, 2)
0036 #define RTW89_TXWD_BODY0_HW_SSN_MODE GENMASK(1, 0)
0037 
0038 /* TX WD BODY DWORD 1 */
0039 #define RTW89_TXWD_BODY1_ADDR_INFO_NUM GENMASK(31, 26)
0040 #define RTW89_TXWD_BODY1_PAYLOAD_ID GENMASK(31, 16)
0041 #define RTW89_TXWD_BODY1_SEC_KEYID GENMASK(5, 4)
0042 #define RTW89_TXWD_BODY1_SEC_TYPE GENMASK(3, 0)
0043 
0044 /* TX WD BODY DWORD 2 */
0045 #define RTW89_TXWD_BODY2_MACID GENMASK(30, 24)
0046 #define RTW89_TXWD_BODY2_TID_INDICATE BIT(23)
0047 #define RTW89_TXWD_BODY2_QSEL GENMASK(22, 17)
0048 #define RTW89_TXWD_BODY2_TXPKT_SIZE GENMASK(13, 0)
0049 
0050 /* TX WD BODY DWORD 3 */
0051 #define RTW89_TXWD_BODY3_BK BIT(13)
0052 #define RTW89_TXWD_BODY3_AGG_EN BIT(12)
0053 #define RTW89_TXWD_BODY3_SW_SEQ GENMASK(11, 0)
0054 
0055 /* TX WD BODY DWORD 4 */
0056 #define RTW89_TXWD_BODY4_SEC_IV_L1 GENMASK(31, 24)
0057 #define RTW89_TXWD_BODY4_SEC_IV_L0 GENMASK(23, 16)
0058 
0059 /* TX WD BODY DWORD 5 */
0060 #define RTW89_TXWD_BODY5_SEC_IV_H5 GENMASK(31, 24)
0061 #define RTW89_TXWD_BODY5_SEC_IV_H4 GENMASK(23, 16)
0062 #define RTW89_TXWD_BODY5_SEC_IV_H3 GENMASK(15, 8)
0063 #define RTW89_TXWD_BODY5_SEC_IV_H2 GENMASK(7, 0)
0064 
0065 /* TX WD BODY DWORD 6 (V1) */
0066 
0067 /* TX WD BODY DWORD 7 (V1) */
0068 #define RTW89_TXWD_BODY7_USE_RATE_V1 BIT(31)
0069 #define RTW89_TXWD_BODY7_DATA_BW GENMASK(29, 28)
0070 #define RTW89_TXWD_BODY7_GI_LTF GENMASK(27, 25)
0071 #define RTW89_TXWD_BODY7_DATA_RATE GENMASK(24, 16)
0072 
0073 /* TX WD INFO DWORD 0 */
0074 #define RTW89_TXWD_INFO0_USE_RATE BIT(30)
0075 #define RTW89_TXWD_INFO0_DATA_BW GENMASK(29, 28)
0076 #define RTW89_TXWD_INFO0_GI_LTF GENMASK(27, 25)
0077 #define RTW89_TXWD_INFO0_DATA_RATE GENMASK(24, 16)
0078 #define RTW89_TXWD_INFO0_DISDATAFB BIT(10)
0079 #define RTW89_TXWD_INFO0_MULTIPORT_ID GENMASK(6, 4)
0080 
0081 /* TX WD INFO DWORD 1 */
0082 #define RTW89_TXWD_INFO1_DATA_RTY_LOWEST_RATE GENMASK(24, 16)
0083 #define RTW89_TXWD_INFO1_A_CTRL_BSR BIT(14)
0084 #define RTW89_TXWD_INFO1_MAX_AGGNUM GENMASK(7, 0)
0085 
0086 /* TX WD INFO DWORD 2 */
0087 #define RTW89_TXWD_INFO2_AMPDU_DENSITY GENMASK(20, 18)
0088 #define RTW89_TXWD_INFO2_SEC_TYPE GENMASK(12, 9)
0089 #define RTW89_TXWD_INFO2_SEC_HW_ENC BIT(8)
0090 #define RTW89_TXWD_INFO2_FORCE_KEY_EN BIT(8)
0091 #define RTW89_TXWD_INFO2_SEC_CAM_IDX GENMASK(7, 0)
0092 
0093 /* TX WD INFO DWORD 3 */
0094 
0095 /* TX WD INFO DWORD 4 */
0096 #define RTW89_TXWD_INFO4_RTS_EN BIT(27)
0097 #define RTW89_TXWD_INFO4_HW_RTS_EN BIT(31)
0098 
0099 /* TX WD INFO DWORD 5 */
0100 
0101 /* RX WD dword0 */
0102 #define AX_RXD_RPKT_LEN_MASK GENMASK(13, 0)
0103 #define AX_RXD_SHIFT_MASK GENMASK(15, 14)
0104 #define AX_RXD_WL_HD_IV_LEN_MASK GENMASK(21, 16)
0105 #define AX_RXD_BB_SEL BIT(22)
0106 #define AX_RXD_MAC_INFO_VLD BIT(23)
0107 #define AX_RXD_RPKT_TYPE_MASK GENMASK(27, 24)
0108 #define AX_RXD_DRV_INFO_SIZE_MASK GENMASK(30, 28)
0109 #define AX_RXD_LONG_RXD BIT(31)
0110 
0111 /* RX WD dword1 */
0112 #define AX_RXD_PPDU_TYPE_MASK GENMASK(3, 0)
0113 #define AX_RXD_PPDU_CNT_MASK GENMASK(6, 4)
0114 #define AX_RXD_SR_EN BIT(7)
0115 #define AX_RXD_USER_ID_MASK GENMASK(15, 8)
0116 #define AX_RXD_USER_ID_v1_MASK GENMASK(13, 8)
0117 #define AX_RXD_RX_DATARATE_MASK GENMASK(24, 16)
0118 #define AX_RXD_RX_GI_LTF_MASK GENMASK(27, 25)
0119 #define AX_RXD_NON_SRG_PPDU BIT(28)
0120 #define AX_RXD_INTER_PPDU BIT(29)
0121 #define AX_RXD_NON_SRG_PPDU_v1 BIT(14)
0122 #define AX_RXD_INTER_PPDU_v1 BIT(15)
0123 #define AX_RXD_BW_MASK GENMASK(31, 30)
0124 #define AX_RXD_BW_v1_MASK GENMASK(31, 29)
0125 
0126 /* RX WD dword2 */
0127 #define AX_RXD_FREERUN_CNT_MASK GENMASK(31, 0)
0128 
0129 /* RX WD dword3 */
0130 #define AX_RXD_A1_MATCH BIT(0)
0131 #define AX_RXD_SW_DEC BIT(1)
0132 #define AX_RXD_HW_DEC BIT(2)
0133 #define AX_RXD_AMPDU BIT(3)
0134 #define AX_RXD_AMPDU_END_PKT BIT(4)
0135 #define AX_RXD_AMSDU BIT(5)
0136 #define AX_RXD_AMSDU_CUT BIT(6)
0137 #define AX_RXD_LAST_MSDU BIT(7)
0138 #define AX_RXD_BYPASS BIT(8)
0139 #define AX_RXD_CRC32_ERR BIT(9)
0140 #define AX_RXD_ICV_ERR BIT(10)
0141 #define AX_RXD_MAGIC_WAKE BIT(11)
0142 #define AX_RXD_UNICAST_WAKE BIT(12)
0143 #define AX_RXD_PATTERN_WAKE BIT(13)
0144 #define AX_RXD_GET_CH_INFO_MASK GENMASK(15, 14)
0145 #define AX_RXD_PATTERN_IDX_MASK GENMASK(20, 16)
0146 #define AX_RXD_TARGET_IDC_MASK GENMASK(23, 21)
0147 #define AX_RXD_CHKSUM_OFFLOAD_EN BIT(24)
0148 #define AX_RXD_WITH_LLC BIT(25)
0149 #define AX_RXD_RX_STATISTICS BIT(26)
0150 
0151 /* RX WD dword4 */
0152 #define AX_RXD_TYPE_MASK GENMASK(1, 0)
0153 #define AX_RXD_MC BIT(2)
0154 #define AX_RXD_BC BIT(3)
0155 #define AX_RXD_MD BIT(4)
0156 #define AX_RXD_MF BIT(5)
0157 #define AX_RXD_PWR BIT(6)
0158 #define AX_RXD_QOS BIT(7)
0159 #define AX_RXD_TID_MASK GENMASK(11, 8)
0160 #define AX_RXD_EOSP BIT(12)
0161 #define AX_RXD_HTC BIT(13)
0162 #define AX_RXD_QNULL BIT(14)
0163 #define AX_RXD_SEQ_MASK GENMASK(27, 16)
0164 #define AX_RXD_FRAG_MASK GENMASK(31, 28)
0165 
0166 /* RX WD dword5 */
0167 #define AX_RXD_SEC_CAM_IDX_MASK GENMASK(7, 0)
0168 #define AX_RXD_ADDR_CAM_MASK GENMASK(15, 8)
0169 #define AX_RXD_MAC_ID_MASK GENMASK(23, 16)
0170 #define AX_RXD_RX_PL_ID_MASK GENMASK(27, 24)
0171 #define AX_RXD_ADDR_CAM_VLD BIT(28)
0172 #define AX_RXD_ADDR_FWD_EN BIT(29)
0173 #define AX_RXD_RX_PL_MATCH BIT(30)
0174 
0175 /* RX WD dword6 */
0176 #define AX_RXD_MAC_ADDR_MASK GENMASK(31, 0)
0177 
0178 /* RX WD dword7 */
0179 #define AX_RXD_MAC_ADDR_H_MASK GENMASK(15, 0)
0180 #define AX_RXD_SMART_ANT BIT(16)
0181 #define AX_RXD_SEC_TYPE_MASK GENMASK(20, 17)
0182 #define AX_RXD_HDR_CNV BIT(21)
0183 #define AX_RXD_HDR_OFFSET_MASK GENMASK(26, 22)
0184 #define AX_RXD_BIP_KEYID BIT(27)
0185 #define AX_RXD_BIP_ENC BIT(28)
0186 
0187 /* RX DESC helpers */
0188 /* Short Descriptor */
0189 #define RTW89_GET_RXWD_LONG_RXD(rxdesc) \
0190     le32_get_bits((rxdesc)->dword0, BIT(31))
0191 #define RTW89_GET_RXWD_DRV_INFO_SIZE(rxdesc) \
0192     le32_get_bits((rxdesc)->dword0, GENMASK(30, 28))
0193 #define RTW89_GET_RXWD_RPKT_TYPE(rxdesc) \
0194     le32_get_bits((rxdesc)->dword0, GENMASK(27, 24))
0195 #define RTW89_GET_RXWD_MAC_INFO_VALID(rxdesc) \
0196     le32_get_bits((rxdesc)->dword0, BIT(23))
0197 #define RTW89_GET_RXWD_BB_SEL(rxdesc) \
0198     le32_get_bits((rxdesc)->dword0, BIT(22))
0199 #define RTW89_GET_RXWD_HD_IV_LEN(rxdesc) \
0200     le32_get_bits((rxdesc)->dword0, GENMASK(21, 16))
0201 #define RTW89_GET_RXWD_SHIFT(rxdesc) \
0202     le32_get_bits((rxdesc)->dword0, GENMASK(15, 14))
0203 #define RTW89_GET_RXWD_PKT_SIZE(rxdesc) \
0204     le32_get_bits((rxdesc)->dword0, GENMASK(13, 0))
0205 #define RTW89_GET_RXWD_BW(rxdesc) \
0206     le32_get_bits((rxdesc)->dword1, GENMASK(31, 30))
0207 #define RTW89_GET_RXWD_BW_V1(rxdesc) \
0208     le32_get_bits((rxdesc)->dword1, GENMASK(31, 29))
0209 #define RTW89_GET_RXWD_GI_LTF(rxdesc) \
0210     le32_get_bits((rxdesc)->dword1, GENMASK(27, 25))
0211 #define RTW89_GET_RXWD_DATA_RATE(rxdesc) \
0212     le32_get_bits((rxdesc)->dword1, GENMASK(24, 16))
0213 #define RTW89_GET_RXWD_USER_ID(rxdesc) \
0214     le32_get_bits((rxdesc)->dword1, GENMASK(15, 8))
0215 #define RTW89_GET_RXWD_SR_EN(rxdesc) \
0216     le32_get_bits((rxdesc)->dword1, BIT(7))
0217 #define RTW89_GET_RXWD_PPDU_CNT(rxdesc) \
0218     le32_get_bits((rxdesc)->dword1, GENMASK(6, 4))
0219 #define RTW89_GET_RXWD_PPDU_TYPE(rxdesc) \
0220     le32_get_bits((rxdesc)->dword1, GENMASK(3, 0))
0221 #define RTW89_GET_RXWD_FREE_RUN_CNT(rxdesc) \
0222     le32_get_bits((rxdesc)->dword2, GENMASK(31, 0))
0223 #define RTW89_GET_RXWD_ICV_ERR(rxdesc) \
0224     le32_get_bits((rxdesc)->dword3, BIT(10))
0225 #define RTW89_GET_RXWD_CRC32_ERR(rxdesc) \
0226     le32_get_bits((rxdesc)->dword3, BIT(9))
0227 #define RTW89_GET_RXWD_HW_DEC(rxdesc) \
0228     le32_get_bits((rxdesc)->dword3, BIT(2))
0229 #define RTW89_GET_RXWD_SW_DEC(rxdesc) \
0230     le32_get_bits((rxdesc)->dword3, BIT(1))
0231 #define RTW89_GET_RXWD_A1_MATCH(rxdesc) \
0232     le32_get_bits((rxdesc)->dword3, BIT(0))
0233 
0234 /* Long Descriptor */
0235 #define RTW89_GET_RXWD_FRAG(rxdesc) \
0236     le32_get_bits((rxdesc)->dword4, GENMASK(31, 28))
0237 #define RTW89_GET_RXWD_SEQ(rxdesc) \
0238     le32_get_bits((rxdesc)->dword4, GENMASK(27, 16))
0239 #define RTW89_GET_RXWD_TYPE(rxdesc) \
0240     le32_get_bits((rxdesc)->dword4, GENMASK(1, 0))
0241 #define RTW89_GET_RXWD_ADDR_CAM_VLD(rxdesc) \
0242     le32_get_bits((rxdesc)->dword5, BIT(28))
0243 #define RTW89_GET_RXWD_RX_PL_ID(rxdesc) \
0244     le32_get_bits((rxdesc)->dword5, GENMASK(27, 24))
0245 #define RTW89_GET_RXWD_MAC_ID(rxdesc) \
0246     le32_get_bits((rxdesc)->dword5, GENMASK(23, 16))
0247 #define RTW89_GET_RXWD_ADDR_CAM_ID(rxdesc) \
0248     le32_get_bits((rxdesc)->dword5, GENMASK(15, 8))
0249 #define RTW89_GET_RXWD_SEC_CAM_ID(rxdesc) \
0250     le32_get_bits((rxdesc)->dword5, GENMASK(7, 0))
0251 
0252 #define RTW89_GET_RXINFO_USR_NUM(rpt) \
0253     le32_get_bits(*((const __le32 *)rpt), GENMASK(3, 0))
0254 #define RTW89_GET_RXINFO_FW_DEFINE(rpt) \
0255     le32_get_bits(*((const __le32 *)rpt), GENMASK(15, 8))
0256 #define RTW89_GET_RXINFO_LSIG_LEN(rpt) \
0257     le32_get_bits(*((const __le32 *)rpt), GENMASK(27, 16))
0258 #define RTW89_GET_RXINFO_IS_TO_SELF(rpt) \
0259     le32_get_bits(*((const __le32 *)rpt), BIT(28))
0260 #define RTW89_GET_RXINFO_RX_CNT_VLD(rpt) \
0261     le32_get_bits(*((const __le32 *)rpt), BIT(29))
0262 #define RTW89_GET_RXINFO_LONG_RXD(rpt) \
0263     le32_get_bits(*((const __le32 *)rpt), GENMASK(31, 30))
0264 #define RTW89_GET_RXINFO_SERVICE(rpt) \
0265     le32_get_bits(*((const __le32 *)(rpt) + 1), GENMASK(15, 0))
0266 #define RTW89_GET_RXINFO_PLCP_LEN(rpt) \
0267     le32_get_bits(*((const __le32 *)(rpt) + 1), GENMASK(23, 16))
0268 #define RTW89_GET_RXINFO_MAC_ID_VALID(rpt, usr) \
0269     le32_get_bits(*((const __le32 *)(rpt) + (usr) + 2), BIT(0))
0270 #define RTW89_GET_RXINFO_DATA(rpt, usr) \
0271     le32_get_bits(*((const __le32 *)(rpt) + (usr) + 2), BIT(1))
0272 #define RTW89_GET_RXINFO_CTRL(rpt, usr) \
0273     le32_get_bits(*((const __le32 *)(rpt) + (usr) + 2), BIT(2))
0274 #define RTW89_GET_RXINFO_MGMT(rpt, usr) \
0275     le32_get_bits(*((const __le32 *)(rpt) + (usr) + 2), BIT(3))
0276 #define RTW89_GET_RXINFO_BCM(rpt, usr) \
0277     le32_get_bits(*((const __le32 *)(rpt) + (usr) + 2), BIT(4))
0278 #define RTW89_GET_RXINFO_MACID(rpt, usr) \
0279     le32_get_bits(*((const __le32 *)(rpt) + (usr) + 2), GENMASK(15, 8))
0280 
0281 #define RTW89_GET_PHY_STS_IE_MAP(sts) \
0282     le32_get_bits(*((const __le32 *)(sts)), GENMASK(4, 0))
0283 #define RTW89_GET_PHY_STS_RSSI_A(sts) \
0284     le32_get_bits(*((const __le32 *)(sts) + 1), GENMASK(7, 0))
0285 #define RTW89_GET_PHY_STS_RSSI_B(sts) \
0286     le32_get_bits(*((const __le32 *)(sts) + 1), GENMASK(15, 8))
0287 #define RTW89_GET_PHY_STS_RSSI_C(sts) \
0288     le32_get_bits(*((const __le32 *)(sts) + 1), GENMASK(23, 16))
0289 #define RTW89_GET_PHY_STS_RSSI_D(sts) \
0290     le32_get_bits(*((const __le32 *)(sts) + 1), GENMASK(31, 24))
0291 #define RTW89_GET_PHY_STS_LEN(sts) \
0292     le32_get_bits(*((const __le32 *)sts), GENMASK(15, 8))
0293 #define RTW89_GET_PHY_STS_RSSI_AVG(sts) \
0294     le32_get_bits(*((const __le32 *)sts), GENMASK(31, 24))
0295 #define RTW89_GET_PHY_STS_IE_TYPE(ie) \
0296     le32_get_bits(*((const __le32 *)ie), GENMASK(4, 0))
0297 #define RTW89_GET_PHY_STS_IE_LEN(ie) \
0298     le32_get_bits(*((const __le32 *)ie), GENMASK(11, 5))
0299 #define RTW89_GET_PHY_STS_IE01_CH_IDX(ie) \
0300     le32_get_bits(*((const __le32 *)ie), GENMASK(23, 16))
0301 #define RTW89_GET_PHY_STS_IE01_CFO(ie) \
0302     le32_get_bits(*((const __le32 *)(ie) + 1), GENMASK(31, 20))
0303 
0304 enum rtw89_tx_channel {
0305     RTW89_TXCH_ACH0 = 0,
0306     RTW89_TXCH_ACH1 = 1,
0307     RTW89_TXCH_ACH2 = 2,
0308     RTW89_TXCH_ACH3 = 3,
0309     RTW89_TXCH_ACH4 = 4,
0310     RTW89_TXCH_ACH5 = 5,
0311     RTW89_TXCH_ACH6 = 6,
0312     RTW89_TXCH_ACH7 = 7,
0313     RTW89_TXCH_CH8  = 8,  /* MGMT Band 0 */
0314     RTW89_TXCH_CH9  = 9,  /* HI Band 0 */
0315     RTW89_TXCH_CH10 = 10, /* MGMT Band 1 */
0316     RTW89_TXCH_CH11 = 11, /* HI Band 1 */
0317     RTW89_TXCH_CH12 = 12, /* FW CMD */
0318 
0319     /* keep last */
0320     RTW89_TXCH_NUM,
0321     RTW89_TXCH_MAX = RTW89_TXCH_NUM - 1
0322 };
0323 
0324 enum rtw89_rx_channel {
0325     RTW89_RXCH_RXQ  = 0,
0326     RTW89_RXCH_RPQ  = 1,
0327 
0328     /* keep last */
0329     RTW89_RXCH_NUM,
0330     RTW89_RXCH_MAX = RTW89_RXCH_NUM - 1
0331 };
0332 
0333 enum rtw89_tx_qsel {
0334     RTW89_TX_QSEL_BE_0      = 0x00,
0335     RTW89_TX_QSEL_BK_0      = 0x01,
0336     RTW89_TX_QSEL_VI_0      = 0x02,
0337     RTW89_TX_QSEL_VO_0      = 0x03,
0338     RTW89_TX_QSEL_BE_1      = 0x04,
0339     RTW89_TX_QSEL_BK_1      = 0x05,
0340     RTW89_TX_QSEL_VI_1      = 0x06,
0341     RTW89_TX_QSEL_VO_1      = 0x07,
0342     RTW89_TX_QSEL_BE_2      = 0x08,
0343     RTW89_TX_QSEL_BK_2      = 0x09,
0344     RTW89_TX_QSEL_VI_2      = 0x0a,
0345     RTW89_TX_QSEL_VO_2      = 0x0b,
0346     RTW89_TX_QSEL_BE_3      = 0x0c,
0347     RTW89_TX_QSEL_BK_3      = 0x0d,
0348     RTW89_TX_QSEL_VI_3      = 0x0e,
0349     RTW89_TX_QSEL_VO_3      = 0x0f,
0350     RTW89_TX_QSEL_B0_BCN        = 0x10,
0351     RTW89_TX_QSEL_B0_HI     = 0x11,
0352     RTW89_TX_QSEL_B0_MGMT       = 0x12,
0353     RTW89_TX_QSEL_B0_NOPS       = 0x13,
0354     RTW89_TX_QSEL_B0_MGMT_FAST  = 0x14,
0355     /* reserved */
0356     /* reserved */
0357     /* reserved */
0358     RTW89_TX_QSEL_B1_BCN        = 0x18,
0359     RTW89_TX_QSEL_B1_HI     = 0x19,
0360     RTW89_TX_QSEL_B1_MGMT       = 0x1a,
0361     RTW89_TX_QSEL_B1_NOPS       = 0x1b,
0362     RTW89_TX_QSEL_B1_MGMT_FAST  = 0x1c,
0363     /* reserved */
0364     /* reserved */
0365     /* reserved */
0366 };
0367 
0368 static inline u8 rtw89_core_get_qsel(struct rtw89_dev *rtwdev, u8 tid)
0369 {
0370     switch (tid) {
0371     default:
0372         rtw89_warn(rtwdev, "Should use tag 1d: %d\n", tid);
0373         fallthrough;
0374     case 0:
0375     case 3:
0376         return RTW89_TX_QSEL_BE_0;
0377     case 1:
0378     case 2:
0379         return RTW89_TX_QSEL_BK_0;
0380     case 4:
0381     case 5:
0382         return RTW89_TX_QSEL_VI_0;
0383     case 6:
0384     case 7:
0385         return RTW89_TX_QSEL_VO_0;
0386     }
0387 }
0388 
0389 static inline u8 rtw89_core_get_ch_dma(struct rtw89_dev *rtwdev, u8 qsel)
0390 {
0391     switch (qsel) {
0392     default:
0393         rtw89_warn(rtwdev, "Cannot map qsel to dma: %d\n", qsel);
0394         fallthrough;
0395     case RTW89_TX_QSEL_BE_0:
0396         return RTW89_TXCH_ACH0;
0397     case RTW89_TX_QSEL_BK_0:
0398         return RTW89_TXCH_ACH1;
0399     case RTW89_TX_QSEL_VI_0:
0400         return RTW89_TXCH_ACH2;
0401     case RTW89_TX_QSEL_VO_0:
0402         return RTW89_TXCH_ACH3;
0403     case RTW89_TX_QSEL_B0_MGMT:
0404         return RTW89_TXCH_CH8;
0405     case RTW89_TX_QSEL_B0_HI:
0406         return RTW89_TXCH_CH9;
0407     case RTW89_TX_QSEL_B1_MGMT:
0408         return RTW89_TXCH_CH10;
0409     case RTW89_TX_QSEL_B1_HI:
0410         return RTW89_TXCH_CH11;
0411     }
0412 }
0413 
0414 static inline u8 rtw89_core_get_tid_indicate(struct rtw89_dev *rtwdev, u8 tid)
0415 {
0416     switch (tid) {
0417     case 3:
0418     case 2:
0419     case 5:
0420     case 7:
0421         return 1;
0422     default:
0423         rtw89_warn(rtwdev, "Should use tag 1d: %d\n", tid);
0424         fallthrough;
0425     case 0:
0426     case 1:
0427     case 4:
0428     case 6:
0429         return 0;
0430     }
0431 }
0432 
0433 #endif
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