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0001 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
0002 /* Copyright(c) 2019-2022  Realtek Corporation
0003  */
0004 
0005 #include "rtw8852c_rfk_table.h"
0006 
0007 static const struct rtw89_reg5_def rtw8852c_dack_reload_defs[] = {
0008     RTW89_DECL_RFK_WM(0xc004, BIT(17), 0x1),
0009     RTW89_DECL_RFK_WM(0xc024, BIT(17), 0x1),
0010     RTW89_DECL_RFK_WM(0xc104, BIT(17), 0x1),
0011     RTW89_DECL_RFK_WM(0xc124, BIT(17), 0x1),
0012 };
0013 
0014 RTW89_DECLARE_RFK_TBL(rtw8852c_dack_reload_defs);
0015 
0016 static const struct rtw89_reg5_def rtw8852c_dack_reset_defs_a[] = {
0017     RTW89_DECL_RFK_WM(0xc000, BIT(17), 0x0),
0018     RTW89_DECL_RFK_WM(0xc000, BIT(17), 0x1),
0019 };
0020 
0021 RTW89_DECLARE_RFK_TBL(rtw8852c_dack_reset_defs_a);
0022 
0023 static const struct rtw89_reg5_def rtw8852c_dack_reset_defs_b[] = {
0024     RTW89_DECL_RFK_WM(0xc100, BIT(17), 0x0),
0025     RTW89_DECL_RFK_WM(0xc100, BIT(17), 0x1),
0026 };
0027 
0028 RTW89_DECLARE_RFK_TBL(rtw8852c_dack_reset_defs_b);
0029 
0030 static const struct rtw89_reg5_def rtw8852c_dack_defs_s0[] = {
0031     RTW89_DECL_RFK_WM(0x12b8, BIT(30), 0x1),
0032     RTW89_DECL_RFK_WM(0x030c, BIT(28), 0x1),
0033     RTW89_DECL_RFK_WM(0x032c, 0x80000000, 0x0),
0034     RTW89_DECL_RFK_WM(0xc004, 0xfff00000, 0x30),
0035     RTW89_DECL_RFK_WM(0xc024, 0xfff00000, 0x30),
0036 };
0037 
0038 RTW89_DECLARE_RFK_TBL(rtw8852c_dack_defs_s0);
0039 
0040 static const struct rtw89_reg5_def rtw8852c_dack_defs_s1[] = {
0041     RTW89_DECL_RFK_WM(0x32b8, BIT(30), 0x1),
0042     RTW89_DECL_RFK_WM(0x030c, BIT(28), 0x1),
0043     RTW89_DECL_RFK_WM(0x032c, 0x80000000, 0x0),
0044     RTW89_DECL_RFK_WM(0xc104, 0xfff00000, 0x30),
0045     RTW89_DECL_RFK_WM(0xc124, 0xfff00000, 0x30),
0046 };
0047 
0048 RTW89_DECLARE_RFK_TBL(rtw8852c_dack_defs_s1);
0049 
0050 static const struct rtw89_reg5_def rtw8852c_drck_defs[] = {
0051     RTW89_DECL_RFK_WM(0xc0c4, BIT(6), 0x0),
0052     RTW89_DECL_RFK_WM(0xc094, BIT(9), 0x1),
0053     RTW89_DECL_RFK_DELAY(1),
0054     RTW89_DECL_RFK_WM(0xc094, BIT(9), 0x0),
0055 };
0056 
0057 RTW89_DECLARE_RFK_TBL(rtw8852c_drck_defs);
0058 
0059 static const struct rtw89_reg5_def rtw8852c_iqk_rxk_cfg_defs[] = {
0060     RTW89_DECL_RFK_WM(0x030c, 0xff000000, 0x0f),
0061     RTW89_DECL_RFK_WM(0x030c, 0xff000000, 0x03),
0062     RTW89_DECL_RFK_WM(0x032c, 0xffff0000, 0x0001),
0063     RTW89_DECL_RFK_WM(0x032c, 0xffff0000, 0x0041),
0064 };
0065 
0066 RTW89_DECLARE_RFK_TBL(rtw8852c_iqk_rxk_cfg_defs);
0067 
0068 static const struct rtw89_reg5_def rtw8852c_iqk_afebb_restore_defs_a[] = {
0069     RTW89_DECL_RFK_WM(0x12b8, 0x40000000, 0x0),
0070     RTW89_DECL_RFK_WM(0x20fc, 0x00010000, 0x1),
0071     RTW89_DECL_RFK_WM(0x20fc, 0x00100000, 0x0),
0072     RTW89_DECL_RFK_WM(0x20fc, 0x01000000, 0x1),
0073     RTW89_DECL_RFK_WM(0x20fc, 0x10000000, 0x0),
0074     RTW89_DECL_RFK_WM(0x5670, MASKDWORD, 0x00000000),
0075     RTW89_DECL_RFK_WM(0x12a0, 0x000ff000, 0x00),
0076     RTW89_DECL_RFK_WM(0x20fc, 0x00010000, 0x0),
0077     RTW89_DECL_RFK_WM(0x20fc, 0x01000000, 0x0),
0078     RTW89_DECL_RFK_WRF(RF_PATH_A, 0x10005, 0x00001, 0x1),
0079 };
0080 
0081 RTW89_DECLARE_RFK_TBL(rtw8852c_iqk_afebb_restore_defs_a);
0082 
0083 static const struct rtw89_reg5_def rtw8852c_iqk_afebb_restore_defs_b[] = {
0084     RTW89_DECL_RFK_WM(0x32b8, 0x40000000, 0x0),
0085     RTW89_DECL_RFK_WM(0x20fc, 0x00020000, 0x1),
0086     RTW89_DECL_RFK_WM(0x20fc, 0x00200000, 0x0),
0087     RTW89_DECL_RFK_WM(0x20fc, 0x02000000, 0x1),
0088     RTW89_DECL_RFK_WM(0x20fc, 0x20000000, 0x0),
0089     RTW89_DECL_RFK_WM(0x7670, MASKDWORD, 0x00000000),
0090     RTW89_DECL_RFK_WM(0x32a0, 0x000ff000, 0x00),
0091     RTW89_DECL_RFK_WM(0x20fc, 0x00020000, 0x0),
0092     RTW89_DECL_RFK_WM(0x20fc, 0x02000000, 0x0),
0093     RTW89_DECL_RFK_WRF(RF_PATH_B, 0x10005, 0x00001, 0x1),
0094 };
0095 
0096 RTW89_DECLARE_RFK_TBL(rtw8852c_iqk_afebb_restore_defs_b);
0097 
0098 static const struct rtw89_reg5_def rtw8852c_read_rxsram_pre_defs[] = {
0099     RTW89_DECL_RFK_WM(0x80e8, BIT(7), 0x1),
0100     RTW89_DECL_RFK_WM(0x8074, BIT(31), 0x1),
0101     RTW89_DECL_RFK_WM(0x80d4, MASKDWORD, 0x00020000),
0102 };
0103 
0104 RTW89_DECLARE_RFK_TBL(rtw8852c_read_rxsram_pre_defs);
0105 
0106 static const struct rtw89_reg5_def rtw8852c_read_rxsram_post_defs[] = {
0107     RTW89_DECL_RFK_WM(0x80e8, BIT(7), 0x0),
0108     RTW89_DECL_RFK_WM(0x8074, BIT(31), 0x0),
0109 };
0110 
0111 RTW89_DECLARE_RFK_TBL(rtw8852c_read_rxsram_post_defs);
0112 
0113 static const struct rtw89_reg5_def rtw8852c_dpk_mdpd_order0_defs[] = {
0114     RTW89_DECL_RFK_WM(0x80a0, BIT(1) | BIT(0), 0x0),
0115     RTW89_DECL_RFK_WM(0x809c, BIT(10) | BIT(9), 0x2),
0116     RTW89_DECL_RFK_WM(0x80a0, 0x00001F00, 0x4),
0117     RTW89_DECL_RFK_WM(0x8070, 0x70000000, 0x1),
0118 };
0119 
0120 RTW89_DECLARE_RFK_TBL(rtw8852c_dpk_mdpd_order0_defs);
0121 
0122 static const struct rtw89_reg5_def rtw8852c_dpk_mdpd_order1_defs[] = {
0123     RTW89_DECL_RFK_WM(0x80a0, BIT(1) | BIT(0), 0x1),
0124     RTW89_DECL_RFK_WM(0x809c, BIT(10) | BIT(9), 0x1),
0125     RTW89_DECL_RFK_WM(0x80a0, 0x00001F00, 0x0),
0126     RTW89_DECL_RFK_WM(0x8070, 0x70000000, 0x0),
0127 };
0128 
0129 RTW89_DECLARE_RFK_TBL(rtw8852c_dpk_mdpd_order1_defs);
0130 
0131 static const struct rtw89_reg5_def rtw8852c_dpk_mdpd_order2_defs[] = {
0132     RTW89_DECL_RFK_WM(0x80a0, BIT(1) | BIT(0), 0x2),
0133     RTW89_DECL_RFK_WM(0x809c, BIT(10) | BIT(9), 0x0),
0134     RTW89_DECL_RFK_WM(0x80a0, 0x00001F00, 0x0),
0135     RTW89_DECL_RFK_WM(0x8070, 0x70000000, 0x0),
0136 };
0137 
0138 RTW89_DECLARE_RFK_TBL(rtw8852c_dpk_mdpd_order2_defs);
0139 
0140 static const struct rtw89_reg5_def rtw8852c_dpk_mdpd_order3_defs[] = {
0141     RTW89_DECL_RFK_WM(0x80a0, BIT(1) | BIT(0), 0x3),
0142     RTW89_DECL_RFK_WM(0x809c, BIT(10) | BIT(9), 0x3),
0143     RTW89_DECL_RFK_WM(0x80a0, 0x00001F00, 0x4),
0144     RTW89_DECL_RFK_WM(0x8070, 0x70000000, 0x1),
0145 };
0146 
0147 RTW89_DECLARE_RFK_TBL(rtw8852c_dpk_mdpd_order3_defs);
0148 
0149 static const struct rtw89_reg5_def rtw8852c_dpk_kip_pwr_clk_on_defs[] = {
0150     RTW89_DECL_RFK_WM(0x8008, MASKDWORD, 0x00000080),
0151     RTW89_DECL_RFK_WM(0x8088, MASKDWORD, 0x807f030a),
0152 };
0153 
0154 RTW89_DECLARE_RFK_TBL(rtw8852c_dpk_kip_pwr_clk_on_defs);
0155 
0156 static const struct rtw89_reg5_def rtw8852c_dpk_kip_pwr_clk_off_defs[] = {
0157     RTW89_DECL_RFK_WM(0x8008, MASKDWORD, 0x00000000),
0158     RTW89_DECL_RFK_WM(0x8088, MASKDWORD, 0x80000000),
0159     RTW89_DECL_RFK_WM(0x80f4, BIT(18), 0x1),
0160 };
0161 
0162 RTW89_DECLARE_RFK_TBL(rtw8852c_dpk_kip_pwr_clk_off_defs);
0163 
0164 static const struct rtw89_reg5_def rtw8852c_tssi_sys_defs[] = {
0165     RTW89_DECL_RFK_WM(0x12bc, 0x000ffff0, 0xb5b5),
0166     RTW89_DECL_RFK_WM(0x32bc, 0x000ffff0, 0xb5b5),
0167     RTW89_DECL_RFK_WM(0x0300, 0xff000000, 0x16),
0168     RTW89_DECL_RFK_WM(0x0304, 0x0000ffff, 0x1f19),
0169     RTW89_DECL_RFK_WM(0x0308, 0xff000000, 0x1c),
0170     RTW89_DECL_RFK_WM(0x0314, 0xffff0000, 0x2041),
0171     RTW89_DECL_RFK_WM(0x0318, 0xffffffff, 0x20012041),
0172     RTW89_DECL_RFK_WM(0x0324, 0xffff0000, 0x2001),
0173     RTW89_DECL_RFK_WM(0x0020, 0x00006000, 0x3),
0174     RTW89_DECL_RFK_WM(0x0024, 0x00006000, 0x3),
0175     RTW89_DECL_RFK_WM(0x0704, 0xffff0000, 0x601e),
0176     RTW89_DECL_RFK_WM(0x2704, 0xffff0000, 0x601e),
0177     RTW89_DECL_RFK_WM(0x0700, 0xf0000000, 0x4),
0178     RTW89_DECL_RFK_WM(0x2700, 0xf0000000, 0x4),
0179     RTW89_DECL_RFK_WM(0x0650, 0x3c000000, 0x0),
0180     RTW89_DECL_RFK_WM(0x2650, 0x3c000000, 0x0),
0181 };
0182 
0183 RTW89_DECLARE_RFK_TBL(rtw8852c_tssi_sys_defs);
0184 
0185 static const struct rtw89_reg5_def rtw8852c_tssi_sys_defs_2g_a[] = {
0186     RTW89_DECL_RFK_WM(0x120c, 0x000000ff, 0x33),
0187     RTW89_DECL_RFK_WM(0x12c0, 0x0ff00000, 0x33),
0188     RTW89_DECL_RFK_WM(0x58f8, 0x40000000, 0x1),
0189 };
0190 
0191 RTW89_DECLARE_RFK_TBL(rtw8852c_tssi_sys_defs_2g_a);
0192 
0193 static const struct rtw89_reg5_def rtw8852c_tssi_sys_defs_2g_b[] = {
0194     RTW89_DECL_RFK_WM(0x320c, 0x000000ff, 0x33),
0195     RTW89_DECL_RFK_WM(0x32c0, 0x0ff00000, 0x33),
0196     RTW89_DECL_RFK_WM(0x78f8, 0x40000000, 0x1),
0197 };
0198 
0199 RTW89_DECLARE_RFK_TBL(rtw8852c_tssi_sys_defs_2g_b);
0200 
0201 static const struct rtw89_reg5_def rtw8852c_tssi_sys_defs_5g_a[] = {
0202     RTW89_DECL_RFK_WM(0x120c, 0x000000ff, 0x44),
0203     RTW89_DECL_RFK_WM(0x12c0, 0x0ff00000, 0x44),
0204     RTW89_DECL_RFK_WM(0x58f8, 0x40000000, 0x0),
0205 };
0206 
0207 RTW89_DECLARE_RFK_TBL(rtw8852c_tssi_sys_defs_5g_a);
0208 
0209 static const struct rtw89_reg5_def rtw8852c_tssi_sys_defs_5g_b[] = {
0210     RTW89_DECL_RFK_WM(0x320c, 0x000000ff, 0x44),
0211     RTW89_DECL_RFK_WM(0x32c0, 0x0ff00000, 0x44),
0212     RTW89_DECL_RFK_WM(0x78f8, 0x40000000, 0x0),
0213 };
0214 
0215 RTW89_DECLARE_RFK_TBL(rtw8852c_tssi_sys_defs_5g_b);
0216 
0217 static const struct rtw89_reg5_def rtw8852c_tssi_txpwr_ctrl_bb_defs_a[] = {
0218     RTW89_DECL_RFK_WM(0x566c, 0x00001000, 0x0),
0219     RTW89_DECL_RFK_WM(0x5800, 0xffffffff, 0x003f807f),
0220     RTW89_DECL_RFK_WM(0x580c, 0x0000007f, 0x40),
0221     RTW89_DECL_RFK_WM(0x580c, 0x0fffff00, 0x00040),
0222     RTW89_DECL_RFK_WM(0x5810, 0xffffffff, 0x59010000),
0223     RTW89_DECL_RFK_WM(0x5814, 0x01ffffff, 0x026d000),
0224     RTW89_DECL_RFK_WM(0x5814, 0xf8000000, 0x00),
0225     RTW89_DECL_RFK_WM(0x5818, 0xffffffff, 0x002c1800),
0226     RTW89_DECL_RFK_WM(0x581c, 0x3fffffff, 0x3dc80280),
0227     RTW89_DECL_RFK_WM(0x5820, 0xffffffff, 0x00000080),
0228     RTW89_DECL_RFK_WM(0x58e8, 0x0000003f, 0x03),
0229     RTW89_DECL_RFK_WM(0x580c, 0x10000000, 0x1),
0230     RTW89_DECL_RFK_WM(0x580c, 0x40000000, 0x1),
0231     RTW89_DECL_RFK_WM(0x5834, 0x3fffffff, 0x000115f2),
0232     RTW89_DECL_RFK_WM(0x5838, 0x7fffffff, 0x0000121),
0233     RTW89_DECL_RFK_WM(0x5854, 0x3fffffff, 0x000115f2),
0234     RTW89_DECL_RFK_WM(0x5858, 0x7fffffff, 0x0000121),
0235     RTW89_DECL_RFK_WM(0x5860, 0x80000000, 0x0),
0236     RTW89_DECL_RFK_WM(0x5864, 0x07ffffff, 0x00801ff),
0237     RTW89_DECL_RFK_WM(0x5898, 0xffffffff, 0x00000000),
0238     RTW89_DECL_RFK_WM(0x589c, 0xffffffff, 0x00000000),
0239     RTW89_DECL_RFK_WM(0x58a4, 0x000000ff, 0x16),
0240     RTW89_DECL_RFK_WM(0x58b4, 0x7fffffff, 0x0a002000),
0241     RTW89_DECL_RFK_WM(0x58b8, 0x7fffffff, 0x00007628),
0242     RTW89_DECL_RFK_WM(0x58bc, 0x07ffffff, 0x7a7807f),
0243     RTW89_DECL_RFK_WM(0x58c0, 0xfffe0000, 0x003f),
0244     RTW89_DECL_RFK_WM(0x58c4, 0xffffffff, 0x0003ffff),
0245     RTW89_DECL_RFK_WM(0x58c8, 0x00ffffff, 0x000000),
0246     RTW89_DECL_RFK_WM(0x58c8, 0xf0000000, 0x0),
0247     RTW89_DECL_RFK_WM(0x58cc, 0xffffffff, 0x00000000),
0248     RTW89_DECL_RFK_WM(0x58d0, 0x07ffffff, 0x2008101),
0249     RTW89_DECL_RFK_WM(0x58d4, 0x000000ff, 0x00),
0250     RTW89_DECL_RFK_WM(0x58d4, 0x0003fe00, 0x0ff),
0251     RTW89_DECL_RFK_WM(0x58d4, 0x07fc0000, 0x100),
0252     RTW89_DECL_RFK_WM(0x58d8, 0xffffffff, 0x8008016c),
0253     RTW89_DECL_RFK_WM(0x58dc, 0x0001ffff, 0x0807f),
0254     RTW89_DECL_RFK_WM(0x58dc, 0xfff00000, 0x800),
0255     RTW89_DECL_RFK_WM(0x58f0, 0x0003ffff, 0x001ff),
0256     RTW89_DECL_RFK_WM(0x58f4, 0x000fffff, 0x000),
0257     RTW89_DECL_RFK_WM(0x58f8, 0x000fffff, 0x000),
0258 };
0259 
0260 RTW89_DECLARE_RFK_TBL(rtw8852c_tssi_txpwr_ctrl_bb_defs_a);
0261 
0262 static const struct rtw89_reg5_def rtw8852c_tssi_txpwr_ctrl_bb_defs_b[] = {
0263     RTW89_DECL_RFK_WM(0x566c, 0x00001000, 0x0),
0264     RTW89_DECL_RFK_WM(0x7800, 0xffffffff, 0x003f807f),
0265     RTW89_DECL_RFK_WM(0x780c, 0x0000007f, 0x40),
0266     RTW89_DECL_RFK_WM(0x780c, 0x0fffff00, 0x00040),
0267     RTW89_DECL_RFK_WM(0x7810, 0xffffffff, 0x59010000),
0268     RTW89_DECL_RFK_WM(0x7814, 0x01ffffff, 0x026d000),
0269     RTW89_DECL_RFK_WM(0x7814, 0xf8000000, 0x00),
0270     RTW89_DECL_RFK_WM(0x7818, 0xffffffff, 0x002c1800),
0271     RTW89_DECL_RFK_WM(0x781c, 0x3fffffff, 0x3dc80280),
0272     RTW89_DECL_RFK_WM(0x7820, 0xffffffff, 0x00000080),
0273     RTW89_DECL_RFK_WM(0x78e8, 0x0000003f, 0x03),
0274     RTW89_DECL_RFK_WM(0x780c, 0x10000000, 0x1),
0275     RTW89_DECL_RFK_WM(0x780c, 0x40000000, 0x1),
0276     RTW89_DECL_RFK_WM(0x7834, 0x3fffffff, 0x000115f2),
0277     RTW89_DECL_RFK_WM(0x7838, 0x7fffffff, 0x0000121),
0278     RTW89_DECL_RFK_WM(0x7854, 0x3fffffff, 0x000115f2),
0279     RTW89_DECL_RFK_WM(0x7858, 0x7fffffff, 0x0000121),
0280     RTW89_DECL_RFK_WM(0x7860, 0x80000000, 0x0),
0281     RTW89_DECL_RFK_WM(0x7864, 0x07ffffff, 0x00801ff),
0282     RTW89_DECL_RFK_WM(0x7898, 0xffffffff, 0x00000000),
0283     RTW89_DECL_RFK_WM(0x789c, 0xffffffff, 0x00000000),
0284     RTW89_DECL_RFK_WM(0x78a4, 0x000000ff, 0x16),
0285     RTW89_DECL_RFK_WM(0x78b4, 0x7fffffff, 0x0a002000),
0286     RTW89_DECL_RFK_WM(0x78b8, 0x7fffffff, 0x00007628),
0287     RTW89_DECL_RFK_WM(0x78bc, 0x07ffffff, 0x7a7807f),
0288     RTW89_DECL_RFK_WM(0x78c0, 0xfffe0000, 0x003f),
0289     RTW89_DECL_RFK_WM(0x78c4, 0xffffffff, 0x0003ffff),
0290     RTW89_DECL_RFK_WM(0x78c8, 0x00ffffff, 0x000000),
0291     RTW89_DECL_RFK_WM(0x78c8, 0xf0000000, 0x0),
0292     RTW89_DECL_RFK_WM(0x78cc, 0xffffffff, 0x00000000),
0293     RTW89_DECL_RFK_WM(0x78d0, 0x07ffffff, 0x2008101),
0294     RTW89_DECL_RFK_WM(0x78d4, 0x000000ff, 0x00),
0295     RTW89_DECL_RFK_WM(0x78d4, 0x0003fe00, 0x0ff),
0296     RTW89_DECL_RFK_WM(0x78d4, 0x07fc0000, 0x100),
0297     RTW89_DECL_RFK_WM(0x78d8, 0xffffffff, 0x8008016c),
0298     RTW89_DECL_RFK_WM(0x78dc, 0x0001ffff, 0x0807f),
0299     RTW89_DECL_RFK_WM(0x78dc, 0xfff00000, 0x800),
0300     RTW89_DECL_RFK_WM(0x78f0, 0x0003ffff, 0x001ff),
0301     RTW89_DECL_RFK_WM(0x78f4, 0x000fffff, 0x000),
0302     RTW89_DECL_RFK_WM(0x78f8, 0x000fffff, 0x000),
0303 };
0304 
0305 RTW89_DECLARE_RFK_TBL(rtw8852c_tssi_txpwr_ctrl_bb_defs_b);
0306 
0307 static const struct rtw89_reg5_def rtw8852c_tssi_txpwr_ctrl_bb_he_tb_defs_a[] = {
0308     RTW89_DECL_RFK_WM(0x58a0, 0xffffffff, 0x000000fe),
0309     RTW89_DECL_RFK_WM(0x58e4, 0x0000007f, 0x1f),
0310 };
0311 
0312 RTW89_DECLARE_RFK_TBL(rtw8852c_tssi_txpwr_ctrl_bb_he_tb_defs_a);
0313 
0314 static const struct rtw89_reg5_def rtw8852c_tssi_txpwr_ctrl_bb_he_tb_defs_b[] = {
0315     RTW89_DECL_RFK_WM(0x78a0, 0xffffffff, 0x000000fe),
0316     RTW89_DECL_RFK_WM(0x78e4, 0x0000007f, 0x1f),
0317 };
0318 
0319 RTW89_DECLARE_RFK_TBL(rtw8852c_tssi_txpwr_ctrl_bb_he_tb_defs_b);
0320 
0321 static const struct rtw89_reg5_def rtw8852c_tssi_dck_defs_a[] = {
0322     RTW89_DECL_RFK_WM(0x58c4, 0x3ffc0000, 0x0),
0323     RTW89_DECL_RFK_WM(0x58c8, 0x00000fff, 0x0),
0324     RTW89_DECL_RFK_WM(0x58c8, 0x00fff000, 0x0),
0325 };
0326 
0327 RTW89_DECLARE_RFK_TBL(rtw8852c_tssi_dck_defs_a);
0328 
0329 static const struct rtw89_reg5_def rtw8852c_tssi_dck_defs_b[] = {
0330     RTW89_DECL_RFK_WM(0x78c4, 0x3ffc0000, 0x0),
0331     RTW89_DECL_RFK_WM(0x78c8, 0x00000fff, 0x0),
0332     RTW89_DECL_RFK_WM(0x78c8, 0x00fff000, 0x0),
0333 };
0334 
0335 RTW89_DECLARE_RFK_TBL(rtw8852c_tssi_dck_defs_b);
0336 
0337 static const struct rtw89_reg5_def rtw8852c_tssi_dck_defs_2g_a[] = {
0338     RTW89_DECL_RFK_WM(0x580c, 0x0fff0000, 0x000),
0339     RTW89_DECL_RFK_WM(0x5814, 0x003ff000, 0x1af),
0340     RTW89_DECL_RFK_WM(0x5814, 0x18000000, 0x0),
0341 };
0342 
0343 RTW89_DECLARE_RFK_TBL(rtw8852c_tssi_dck_defs_2g_a);
0344 
0345 static const struct rtw89_reg5_def rtw8852c_tssi_dck_defs_2g_b[] = {
0346     RTW89_DECL_RFK_WM(0x780c, 0x0fff0000, 0x000),
0347     RTW89_DECL_RFK_WM(0x7814, 0x003ff000, 0x1af),
0348     RTW89_DECL_RFK_WM(0x7814, 0x18000000, 0x0),
0349 };
0350 
0351 RTW89_DECLARE_RFK_TBL(rtw8852c_tssi_dck_defs_2g_b);
0352 
0353 static const struct rtw89_reg5_def rtw8852c_tssi_dck_defs_5g_a[] = {
0354     RTW89_DECL_RFK_WM(0x580c, 0x0fff0000, 0x000),
0355     RTW89_DECL_RFK_WM(0x5814, 0x00001000, 0x1),
0356     RTW89_DECL_RFK_WM(0x5814, 0x0003c000, 0xb),
0357     RTW89_DECL_RFK_WM(0x5814, 0x00002000, 0x1),
0358     RTW89_DECL_RFK_WM(0x5814, 0x003c0000, 0x6),
0359     RTW89_DECL_RFK_WM(0x5814, 0x18000000, 0x0),
0360 };
0361 
0362 RTW89_DECLARE_RFK_TBL(rtw8852c_tssi_dck_defs_5g_a);
0363 
0364 static const struct rtw89_reg5_def rtw8852c_tssi_dck_defs_5g_b[] = {
0365     RTW89_DECL_RFK_WM(0x780c, 0x0fff0000, 0x000),
0366     RTW89_DECL_RFK_WM(0x7814, 0x00001000, 0x1),
0367     RTW89_DECL_RFK_WM(0x7814, 0x0003c000, 0xb),
0368     RTW89_DECL_RFK_WM(0x7814, 0x00002000, 0x1),
0369     RTW89_DECL_RFK_WM(0x7814, 0x003c0000, 0x6),
0370     RTW89_DECL_RFK_WM(0x7814, 0x18000000, 0x0),
0371 };
0372 
0373 RTW89_DECLARE_RFK_TBL(rtw8852c_tssi_dck_defs_5g_b);
0374 
0375 static const struct rtw89_reg5_def rtw8852c_tssi_set_bbgain_split_a[] = {
0376     RTW89_DECL_RFK_WM(0x5818, 0x08000000, 0x1),
0377     RTW89_DECL_RFK_WM(0x58d4, 0xf0000000, 0x7),
0378     RTW89_DECL_RFK_WM(0x58f0, 0x000c0000, 0x1),
0379     RTW89_DECL_RFK_WM(0x58f0, 0xfff00000, 0x400),
0380 };
0381 
0382 RTW89_DECLARE_RFK_TBL(rtw8852c_tssi_set_bbgain_split_a);
0383 
0384 static const struct rtw89_reg5_def rtw8852c_tssi_set_bbgain_split_b[] = {
0385     RTW89_DECL_RFK_WM(0x7818, 0x08000000, 0x1),
0386     RTW89_DECL_RFK_WM(0x78d4, 0xf0000000, 0x7),
0387     RTW89_DECL_RFK_WM(0x78f0, 0x000c0000, 0x1),
0388     RTW89_DECL_RFK_WM(0x78f0, 0xfff00000, 0x400),
0389 };
0390 
0391 RTW89_DECLARE_RFK_TBL(rtw8852c_tssi_set_bbgain_split_b);
0392 
0393 static const struct rtw89_reg5_def rtw8852c_tssi_slope_cal_org_defs_2g_a[] = {
0394     RTW89_DECL_RFK_WM(0x5608, 0x07ffffff, 0x0201008),
0395     RTW89_DECL_RFK_WM(0x560c, 0x07ffffff, 0x0201008),
0396     RTW89_DECL_RFK_WM(0x5610, 0x07ffffff, 0x0201020),
0397     RTW89_DECL_RFK_WM(0x5614, 0x07ffffff, 0x0201008),
0398     RTW89_DECL_RFK_WM(0x5618, 0x07ffffff, 0x0801008),
0399     RTW89_DECL_RFK_WM(0x561c, 0x000001ff, 0x008),
0400     RTW89_DECL_RFK_WM(0x561c, 0xffff0000, 0x0808),
0401     RTW89_DECL_RFK_WM(0x5620, 0xffffffff, 0x08080808),
0402     RTW89_DECL_RFK_WM(0x5624, 0xffffffff, 0x0808081e),
0403     RTW89_DECL_RFK_WM(0x5628, 0xffffffff, 0x08080808),
0404     RTW89_DECL_RFK_WM(0x562c, 0x0000ffff, 0x081d),
0405     RTW89_DECL_RFK_WM(0x581c, 0x00100000, 0x1),
0406 };
0407 
0408 RTW89_DECLARE_RFK_TBL(rtw8852c_tssi_slope_cal_org_defs_2g_a);
0409 
0410 static const struct rtw89_reg5_def rtw8852c_tssi_slope_cal_org_defs_2g_b[] = {
0411     RTW89_DECL_RFK_WM(0x7608, 0x07ffffff, 0x0201008),
0412     RTW89_DECL_RFK_WM(0x760c, 0x07ffffff, 0x0201008),
0413     RTW89_DECL_RFK_WM(0x7610, 0x07ffffff, 0x0204020),
0414     RTW89_DECL_RFK_WM(0x7614, 0x07ffffff, 0x0201008),
0415     RTW89_DECL_RFK_WM(0x7618, 0x07ffffff, 0x0801008),
0416     RTW89_DECL_RFK_WM(0x761c, 0x000001ff, 0x020),
0417     RTW89_DECL_RFK_WM(0x761c, 0xffff0000, 0x0808),
0418     RTW89_DECL_RFK_WM(0x7620, 0xffffffff, 0x08080808),
0419     RTW89_DECL_RFK_WM(0x7624, 0xffffffff, 0x08081e21),
0420     RTW89_DECL_RFK_WM(0x7628, 0xffffffff, 0x08080808),
0421     RTW89_DECL_RFK_WM(0x762c, 0x0000ffff, 0x1d23),
0422     RTW89_DECL_RFK_WM(0x781c, 0x00100000, 0x1),
0423 };
0424 
0425 RTW89_DECLARE_RFK_TBL(rtw8852c_tssi_slope_cal_org_defs_2g_b);
0426 
0427 static const struct rtw89_reg5_def rtw8852c_tssi_slope_cal_org_defs_5g_a[] = {
0428     RTW89_DECL_RFK_WM(0x5608, 0x07ffffff, 0x0201008),
0429     RTW89_DECL_RFK_WM(0x560c, 0x07ffffff, 0x0201008),
0430     RTW89_DECL_RFK_WM(0x5610, 0x07ffffff, 0x0201008),
0431     RTW89_DECL_RFK_WM(0x5614, 0x07ffffff, 0x0201008),
0432     RTW89_DECL_RFK_WM(0x5618, 0x07ffffff, 0x0201008),
0433     RTW89_DECL_RFK_WM(0x561c, 0x000001ff, 0x008),
0434     RTW89_DECL_RFK_WM(0x561c, 0xffff0000, 0x0808),
0435     RTW89_DECL_RFK_WM(0x5620, 0xffffffff, 0x08080808),
0436     RTW89_DECL_RFK_WM(0x5624, 0xffffffff, 0x08080808),
0437     RTW89_DECL_RFK_WM(0x5628, 0xffffffff, 0x08080808),
0438     RTW89_DECL_RFK_WM(0x562c, 0x0000ffff, 0x0808),
0439     RTW89_DECL_RFK_WM(0x581c, 0x00100000, 0x0),
0440 };
0441 
0442 RTW89_DECLARE_RFK_TBL(rtw8852c_tssi_slope_cal_org_defs_5g_a);
0443 
0444 static const struct rtw89_reg5_def rtw8852c_tssi_slope_cal_org_defs_5g_b[] = {
0445     RTW89_DECL_RFK_WM(0x7608, 0x07ffffff, 0x0201008),
0446     RTW89_DECL_RFK_WM(0x760c, 0x07ffffff, 0x0201008),
0447     RTW89_DECL_RFK_WM(0x7610, 0x07ffffff, 0x0201008),
0448     RTW89_DECL_RFK_WM(0x7614, 0x07ffffff, 0x0201008),
0449     RTW89_DECL_RFK_WM(0x7618, 0x07ffffff, 0x0201008),
0450     RTW89_DECL_RFK_WM(0x761c, 0x000001ff, 0x008),
0451     RTW89_DECL_RFK_WM(0x761c, 0xffff0000, 0x0808),
0452     RTW89_DECL_RFK_WM(0x7620, 0xffffffff, 0x08080808),
0453     RTW89_DECL_RFK_WM(0x7624, 0xffffffff, 0x08080808),
0454     RTW89_DECL_RFK_WM(0x7628, 0xffffffff, 0x08080808),
0455     RTW89_DECL_RFK_WM(0x762c, 0x0000ffff, 0x0808),
0456     RTW89_DECL_RFK_WM(0x781c, 0x00100000, 0x0),
0457 };
0458 
0459 RTW89_DECLARE_RFK_TBL(rtw8852c_tssi_slope_cal_org_defs_5g_b);
0460 
0461 static const struct rtw89_reg5_def rtw8852c_tssi_set_aligk_default_defs_2g_a[] = {
0462     RTW89_DECL_RFK_WM(0x5604, 0x80000000, 0x1),
0463     RTW89_DECL_RFK_WM(0x5600, 0x3fffffff, 0x000000),
0464     RTW89_DECL_RFK_WM(0x5604, 0x003fffff, 0x2d2721),
0465     RTW89_DECL_RFK_WM(0x5630, 0x3fffffff, 0x00000000),
0466     RTW89_DECL_RFK_WM(0x5634, 0x000003ff, 0x000),
0467     RTW89_DECL_RFK_WM(0x5634, 0x000ffc00, 0x3b8),
0468     RTW89_DECL_RFK_WM(0x5634, 0x3ff00000, 0x3d2),
0469     RTW89_DECL_RFK_WM(0x5638, 0x000003ff, 0x042),
0470     RTW89_DECL_RFK_WM(0x5638, 0x000ffc00, 0x06b),
0471     RTW89_DECL_RFK_WM(0x563c, 0x3fffffff, 0x00000000),
0472     RTW89_DECL_RFK_WM(0x5640, 0x000003ff, 0x000),
0473     RTW89_DECL_RFK_WM(0x5640, 0x000ffc00, 0x3bc),
0474     RTW89_DECL_RFK_WM(0x5640, 0x3ff00000, 0x3d6),
0475     RTW89_DECL_RFK_WM(0x5644, 0x000003ff, 0x03e),
0476     RTW89_DECL_RFK_WM(0x5644, 0x000ffc00, 0x06b),
0477 };
0478 
0479 RTW89_DECLARE_RFK_TBL(rtw8852c_tssi_set_aligk_default_defs_2g_a);
0480 
0481 static const struct rtw89_reg5_def rtw8852c_tssi_set_aligk_default_defs_2g_b[] = {
0482     RTW89_DECL_RFK_WM(0x7604, 0x80000000, 0x1),
0483     RTW89_DECL_RFK_WM(0x7600, 0x3fffffff, 0x000000),
0484     RTW89_DECL_RFK_WM(0x7604, 0x003fffff, 0x2d2721),
0485     RTW89_DECL_RFK_WM(0x7630, 0x3fffffff, 0x00000000),
0486     RTW89_DECL_RFK_WM(0x7634, 0x000003ff, 0x000),
0487     RTW89_DECL_RFK_WM(0x7634, 0x000ffc00, 0x3c0),
0488     RTW89_DECL_RFK_WM(0x7634, 0x3ff00000, 0x3da),
0489     RTW89_DECL_RFK_WM(0x7638, 0x000003ff, 0x002),
0490     RTW89_DECL_RFK_WM(0x7638, 0x000ffc00, 0x071),
0491     RTW89_DECL_RFK_WM(0x763c, 0x3fffffff, 0x00000000),
0492     RTW89_DECL_RFK_WM(0x7640, 0x000003ff, 0x000),
0493     RTW89_DECL_RFK_WM(0x7640, 0x000ffc00, 0x3c8),
0494     RTW89_DECL_RFK_WM(0x7640, 0x3ff00000, 0x3e2),
0495     RTW89_DECL_RFK_WM(0x7644, 0x000003ff, 0x00c),
0496     RTW89_DECL_RFK_WM(0x7644, 0x000ffc00, 0x071),
0497 };
0498 
0499 RTW89_DECLARE_RFK_TBL(rtw8852c_tssi_set_aligk_default_defs_2g_b);
0500 
0501 static const struct rtw89_reg5_def rtw8852c_tssi_set_aligk_default_defs_5g_a[] = {
0502     RTW89_DECL_RFK_WM(0x5604, 0x80000000, 0x1),
0503     RTW89_DECL_RFK_WM(0x5600, 0x3fffffff, 0x000000),
0504     RTW89_DECL_RFK_WM(0x5604, 0x003fffff, 0x312600),
0505     RTW89_DECL_RFK_WM(0x5630, 0x3fffffff, 0x00000000),
0506     RTW89_DECL_RFK_WM(0x5634, 0x000003ff, 0x000),
0507     RTW89_DECL_RFK_WM(0x5634, 0x000ffc00, 0x000),
0508     RTW89_DECL_RFK_WM(0x5634, 0x3ff00000, 0x3e9),
0509     RTW89_DECL_RFK_WM(0x5638, 0x000003ff, 0x039),
0510     RTW89_DECL_RFK_WM(0x5638, 0x000ffc00, 0x07d),
0511     RTW89_DECL_RFK_WM(0x563c, 0x3fffffff, 0x00000000),
0512     RTW89_DECL_RFK_WM(0x5640, 0x000003ff, 0x000),
0513     RTW89_DECL_RFK_WM(0x5640, 0x000ffc00, 0x000),
0514     RTW89_DECL_RFK_WM(0x5640, 0x3ff00000, 0x000),
0515     RTW89_DECL_RFK_WM(0x5644, 0x000003ff, 0x000),
0516     RTW89_DECL_RFK_WM(0x5644, 0x000ffc00, 0x000),
0517 };
0518 
0519 RTW89_DECLARE_RFK_TBL(rtw8852c_tssi_set_aligk_default_defs_5g_a);
0520 
0521 static const struct rtw89_reg5_def rtw8852c_tssi_set_aligk_default_defs_5g_b[] = {
0522     RTW89_DECL_RFK_WM(0x7604, 0x80000000, 0x1),
0523     RTW89_DECL_RFK_WM(0x7600, 0x3fffffff, 0x000000),
0524     RTW89_DECL_RFK_WM(0x7604, 0x003fffff, 0x312600),
0525     RTW89_DECL_RFK_WM(0x7630, 0x3fffffff, 0x00000000),
0526     RTW89_DECL_RFK_WM(0x7634, 0x000003ff, 0x000),
0527     RTW89_DECL_RFK_WM(0x7634, 0x000ffc00, 0x000),
0528     RTW89_DECL_RFK_WM(0x7634, 0x3ff00000, 0x3e9),
0529     RTW89_DECL_RFK_WM(0x7638, 0x000003ff, 0x039),
0530     RTW89_DECL_RFK_WM(0x7638, 0x000ffc00, 0x07d),
0531     RTW89_DECL_RFK_WM(0x763c, 0x3fffffff, 0x00000000),
0532     RTW89_DECL_RFK_WM(0x7640, 0x000003ff, 0x000),
0533     RTW89_DECL_RFK_WM(0x7640, 0x000ffc00, 0x000),
0534     RTW89_DECL_RFK_WM(0x7640, 0x3ff00000, 0x000),
0535     RTW89_DECL_RFK_WM(0x7644, 0x000003ff, 0x000),
0536     RTW89_DECL_RFK_WM(0x7644, 0x000ffc00, 0x000),
0537 };
0538 
0539 RTW89_DECLARE_RFK_TBL(rtw8852c_tssi_set_aligk_default_defs_5g_b);
0540 
0541 static const struct rtw89_reg5_def rtw8852c_tssi_set_aligk_default_defs_6g_a[] = {
0542     RTW89_DECL_RFK_WM(0x5604, 0x80000000, 0x1),
0543     RTW89_DECL_RFK_WM(0x5600, 0x3fffffff, 0x000000),
0544     RTW89_DECL_RFK_WM(0x5604, 0x003fffff, 0x312600),
0545     RTW89_DECL_RFK_WM(0x5630, 0x3fffffff, 0x00000000),
0546     RTW89_DECL_RFK_WM(0x5634, 0x000003ff, 0x000),
0547     RTW89_DECL_RFK_WM(0x5634, 0x000ffc00, 0x000),
0548     RTW89_DECL_RFK_WM(0x5634, 0x3ff00000, 0x3e9),
0549     RTW89_DECL_RFK_WM(0x5638, 0x000003ff, 0x039),
0550     RTW89_DECL_RFK_WM(0x5638, 0x000ffc00, 0x080),
0551     RTW89_DECL_RFK_WM(0x563c, 0x3fffffff, 0x00000000),
0552     RTW89_DECL_RFK_WM(0x5640, 0x000003ff, 0x000),
0553     RTW89_DECL_RFK_WM(0x5640, 0x000ffc00, 0x000),
0554     RTW89_DECL_RFK_WM(0x5640, 0x3ff00000, 0x000),
0555     RTW89_DECL_RFK_WM(0x5644, 0x000003ff, 0x000),
0556     RTW89_DECL_RFK_WM(0x5644, 0x000ffc00, 0x000),
0557 };
0558 
0559 RTW89_DECLARE_RFK_TBL(rtw8852c_tssi_set_aligk_default_defs_6g_a);
0560 
0561 static const struct rtw89_reg5_def rtw8852c_tssi_set_aligk_default_defs_6g_b[] = {
0562     RTW89_DECL_RFK_WM(0x7604, 0x80000000, 0x1),
0563     RTW89_DECL_RFK_WM(0x7600, 0x3fffffff, 0x000000),
0564     RTW89_DECL_RFK_WM(0x7604, 0x003fffff, 0x312600),
0565     RTW89_DECL_RFK_WM(0x7630, 0x3fffffff, 0x00000000),
0566     RTW89_DECL_RFK_WM(0x7634, 0x000003ff, 0x000),
0567     RTW89_DECL_RFK_WM(0x7634, 0x000ffc00, 0x000),
0568     RTW89_DECL_RFK_WM(0x7634, 0x3ff00000, 0x3e9),
0569     RTW89_DECL_RFK_WM(0x7638, 0x000003ff, 0x039),
0570     RTW89_DECL_RFK_WM(0x7638, 0x000ffc00, 0x080),
0571     RTW89_DECL_RFK_WM(0x763c, 0x3fffffff, 0x00000000),
0572     RTW89_DECL_RFK_WM(0x7640, 0x000003ff, 0x000),
0573     RTW89_DECL_RFK_WM(0x7640, 0x000ffc00, 0x000),
0574     RTW89_DECL_RFK_WM(0x7640, 0x3ff00000, 0x000),
0575     RTW89_DECL_RFK_WM(0x7644, 0x000003ff, 0x000),
0576     RTW89_DECL_RFK_WM(0x7644, 0x000ffc00, 0x000),
0577 };
0578 
0579 RTW89_DECLARE_RFK_TBL(rtw8852c_tssi_set_aligk_default_defs_6g_b);
0580 
0581 static const struct rtw89_reg5_def rtw8852c_tssi_slope_defs_a[] = {
0582     RTW89_DECL_RFK_WM(0x5820, 0x80000000, 0x0),
0583     RTW89_DECL_RFK_WM(0x5818, 0x10000000, 0x0),
0584     RTW89_DECL_RFK_WM(0x5814, 0x00000800, 0x1),
0585     RTW89_DECL_RFK_WM(0x581c, 0x20000000, 0x1),
0586     RTW89_DECL_RFK_WM(0x58e8, 0x0000003f, 0x0f),
0587     RTW89_DECL_RFK_WM(0x581c, 0x000003ff, 0x280),
0588     RTW89_DECL_RFK_WM(0x581c, 0x000ffc00, 0x200),
0589     RTW89_DECL_RFK_WM(0x58b8, 0x007f0000, 0x00),
0590     RTW89_DECL_RFK_WM(0x58b8, 0x7f000000, 0x00),
0591     RTW89_DECL_RFK_WM(0x58b4, 0x7f000000, 0x0a),
0592     RTW89_DECL_RFK_WM(0x58b8, 0x0000007f, 0x28),
0593     RTW89_DECL_RFK_WM(0x58b8, 0x00007f00, 0x76),
0594     RTW89_DECL_RFK_WM(0x5810, 0x20000000, 0x0),
0595     RTW89_DECL_RFK_WM(0x5814, 0x20000000, 0x1),
0596     RTW89_DECL_RFK_WM(0x580c, 0x10000000, 0x1),
0597     RTW89_DECL_RFK_WM(0x580c, 0x40000000, 0x1),
0598     RTW89_DECL_RFK_WM(0x5834, 0x0003ffff, 0x115f2),
0599     RTW89_DECL_RFK_WM(0x5834, 0x3ffc0000, 0x000),
0600     RTW89_DECL_RFK_WM(0x5838, 0x00000fff, 0x121),
0601     RTW89_DECL_RFK_WM(0x5838, 0x003ff000, 0x000),
0602     RTW89_DECL_RFK_WM(0x5854, 0x0003ffff, 0x115f2),
0603     RTW89_DECL_RFK_WM(0x5854, 0x3ffc0000, 0x000),
0604     RTW89_DECL_RFK_WM(0x5858, 0x00000fff, 0x121),
0605     RTW89_DECL_RFK_WM(0x5858, 0x003ff000, 0x000),
0606     RTW89_DECL_RFK_WM(0x5824, 0x0003ffff, 0x115f2),
0607     RTW89_DECL_RFK_WM(0x5824, 0x3ffc0000, 0x000),
0608     RTW89_DECL_RFK_WM(0x5828, 0x00000fff, 0x121),
0609     RTW89_DECL_RFK_WM(0x5828, 0x003ff000, 0x000),
0610     RTW89_DECL_RFK_WM(0x582c, 0x0003ffff, 0x115f2),
0611     RTW89_DECL_RFK_WM(0x582c, 0x3ffc0000, 0x000),
0612     RTW89_DECL_RFK_WM(0x5830, 0x00000fff, 0x121),
0613     RTW89_DECL_RFK_WM(0x5830, 0x003ff000, 0x000),
0614     RTW89_DECL_RFK_WM(0x583c, 0x0003ffff, 0x115f2),
0615     RTW89_DECL_RFK_WM(0x583c, 0x3ffc0000, 0x000),
0616     RTW89_DECL_RFK_WM(0x5840, 0x00000fff, 0x121),
0617     RTW89_DECL_RFK_WM(0x5840, 0x003ff000, 0x000),
0618     RTW89_DECL_RFK_WM(0x5844, 0x0003ffff, 0x115f2),
0619     RTW89_DECL_RFK_WM(0x5844, 0x3ffc0000, 0x000),
0620     RTW89_DECL_RFK_WM(0x5848, 0x00000fff, 0x121),
0621     RTW89_DECL_RFK_WM(0x5848, 0x003ff000, 0x000),
0622     RTW89_DECL_RFK_WM(0x584c, 0x0003ffff, 0x115f2),
0623     RTW89_DECL_RFK_WM(0x584c, 0x3ffc0000, 0x000),
0624     RTW89_DECL_RFK_WM(0x5850, 0x00000fff, 0x121),
0625     RTW89_DECL_RFK_WM(0x5850, 0x003ff000, 0x000),
0626     RTW89_DECL_RFK_WM(0x585c, 0x0003ffff, 0x115f2),
0627     RTW89_DECL_RFK_WM(0x585c, 0x3ffc0000, 0x000),
0628     RTW89_DECL_RFK_WM(0x5860, 0x00000fff, 0x121),
0629     RTW89_DECL_RFK_WM(0x5860, 0x003ff000, 0x000),
0630 };
0631 
0632 RTW89_DECLARE_RFK_TBL(rtw8852c_tssi_slope_defs_a);
0633 
0634 static const struct rtw89_reg5_def rtw8852c_tssi_slope_defs_b[] = {
0635     RTW89_DECL_RFK_WM(0x7820, 0x80000000, 0x0),
0636     RTW89_DECL_RFK_WM(0x7818, 0x10000000, 0x0),
0637     RTW89_DECL_RFK_WM(0x7814, 0x00000800, 0x1),
0638     RTW89_DECL_RFK_WM(0x781c, 0x20000000, 0x1),
0639     RTW89_DECL_RFK_WM(0x78e8, 0x0000003f, 0x0f),
0640     RTW89_DECL_RFK_WM(0x781c, 0x000003ff, 0x280),
0641     RTW89_DECL_RFK_WM(0x781c, 0x000ffc00, 0x200),
0642     RTW89_DECL_RFK_WM(0x78b8, 0x007f0000, 0x00),
0643     RTW89_DECL_RFK_WM(0x78b8, 0x7f000000, 0x00),
0644     RTW89_DECL_RFK_WM(0x78b4, 0x7f000000, 0x0a),
0645     RTW89_DECL_RFK_WM(0x78b8, 0x0000007f, 0x28),
0646     RTW89_DECL_RFK_WM(0x78b8, 0x00007f00, 0x76),
0647     RTW89_DECL_RFK_WM(0x7810, 0x20000000, 0x0),
0648     RTW89_DECL_RFK_WM(0x7814, 0x20000000, 0x1),
0649     RTW89_DECL_RFK_WM(0x780c, 0x10000000, 0x1),
0650     RTW89_DECL_RFK_WM(0x780c, 0x40000000, 0x1),
0651     RTW89_DECL_RFK_WM(0x7834, 0x0003ffff, 0x115f2),
0652     RTW89_DECL_RFK_WM(0x7834, 0x3ffc0000, 0x000),
0653     RTW89_DECL_RFK_WM(0x7838, 0x00000fff, 0x121),
0654     RTW89_DECL_RFK_WM(0x7838, 0x003ff000, 0x000),
0655     RTW89_DECL_RFK_WM(0x7854, 0x0003ffff, 0x115f2),
0656     RTW89_DECL_RFK_WM(0x7854, 0x3ffc0000, 0x000),
0657     RTW89_DECL_RFK_WM(0x7858, 0x00000fff, 0x121),
0658     RTW89_DECL_RFK_WM(0x7858, 0x003ff000, 0x000),
0659     RTW89_DECL_RFK_WM(0x7824, 0x0003ffff, 0x115f2),
0660     RTW89_DECL_RFK_WM(0x7824, 0x3ffc0000, 0x000),
0661     RTW89_DECL_RFK_WM(0x7828, 0x00000fff, 0x121),
0662     RTW89_DECL_RFK_WM(0x7828, 0x003ff000, 0x000),
0663     RTW89_DECL_RFK_WM(0x782c, 0x0003ffff, 0x115f2),
0664     RTW89_DECL_RFK_WM(0x782c, 0x3ffc0000, 0x000),
0665     RTW89_DECL_RFK_WM(0x7830, 0x00000fff, 0x121),
0666     RTW89_DECL_RFK_WM(0x7830, 0x003ff000, 0x000),
0667     RTW89_DECL_RFK_WM(0x783c, 0x0003ffff, 0x115f2),
0668     RTW89_DECL_RFK_WM(0x783c, 0x3ffc0000, 0x000),
0669     RTW89_DECL_RFK_WM(0x7840, 0x00000fff, 0x121),
0670     RTW89_DECL_RFK_WM(0x7840, 0x003ff000, 0x000),
0671     RTW89_DECL_RFK_WM(0x7844, 0x0003ffff, 0x115f2),
0672     RTW89_DECL_RFK_WM(0x7844, 0x3ffc0000, 0x000),
0673     RTW89_DECL_RFK_WM(0x7848, 0x00000fff, 0x121),
0674     RTW89_DECL_RFK_WM(0x7848, 0x003ff000, 0x000),
0675     RTW89_DECL_RFK_WM(0x784c, 0x0003ffff, 0x115f2),
0676     RTW89_DECL_RFK_WM(0x784c, 0x3ffc0000, 0x000),
0677     RTW89_DECL_RFK_WM(0x7850, 0x00000fff, 0x121),
0678     RTW89_DECL_RFK_WM(0x7850, 0x003ff000, 0x000),
0679     RTW89_DECL_RFK_WM(0x785c, 0x0003ffff, 0x115f2),
0680     RTW89_DECL_RFK_WM(0x785c, 0x3ffc0000, 0x000),
0681     RTW89_DECL_RFK_WM(0x7860, 0x00000fff, 0x121),
0682     RTW89_DECL_RFK_WM(0x7860, 0x003ff000, 0x000),
0683 };
0684 
0685 RTW89_DECLARE_RFK_TBL(rtw8852c_tssi_slope_defs_b);
0686 
0687 static const struct rtw89_reg5_def rtw8852c_tssi_run_slope_defs_a[] = {
0688     RTW89_DECL_RFK_WM(0x5820, 0x80000000, 0x0),
0689     RTW89_DECL_RFK_WM(0x5820, 0x80000000, 0x1),
0690 };
0691 
0692 RTW89_DECLARE_RFK_TBL(rtw8852c_tssi_run_slope_defs_a);
0693 
0694 static const struct rtw89_reg5_def rtw8852c_tssi_run_slope_defs_b[] = {
0695     RTW89_DECL_RFK_WM(0x7820, 0x80000000, 0x0),
0696     RTW89_DECL_RFK_WM(0x7820, 0x80000000, 0x1),
0697 };
0698 
0699 RTW89_DECLARE_RFK_TBL(rtw8852c_tssi_run_slope_defs_b);
0700 
0701 static const struct rtw89_reg5_def rtw8852c_tssi_track_defs_a[] = {
0702     RTW89_DECL_RFK_WM(0x5820, 0x80000000, 0x0),
0703     RTW89_DECL_RFK_WM(0x5818, 0x10000000, 0x0),
0704     RTW89_DECL_RFK_WM(0x5814, 0x00000800, 0x0),
0705     RTW89_DECL_RFK_WM(0x581c, 0x20000000, 0x1),
0706     RTW89_DECL_RFK_WM(0x5864, 0x000003ff, 0x1ff),
0707     RTW89_DECL_RFK_WM(0x5864, 0x000ffc00, 0x200),
0708     RTW89_DECL_RFK_WM(0x5820, 0x00000fff, 0x080),
0709     RTW89_DECL_RFK_WM(0x5814, 0x01000000, 0x0),
0710 };
0711 
0712 RTW89_DECLARE_RFK_TBL(rtw8852c_tssi_track_defs_a);
0713 
0714 static const struct rtw89_reg5_def rtw8852c_tssi_track_defs_b[] = {
0715     RTW89_DECL_RFK_WM(0x7820, 0x80000000, 0x0),
0716     RTW89_DECL_RFK_WM(0x7818, 0x10000000, 0x0),
0717     RTW89_DECL_RFK_WM(0x7814, 0x00000800, 0x0),
0718     RTW89_DECL_RFK_WM(0x781c, 0x20000000, 0x1),
0719     RTW89_DECL_RFK_WM(0x7864, 0x000003ff, 0x1ff),
0720     RTW89_DECL_RFK_WM(0x7864, 0x000ffc00, 0x200),
0721     RTW89_DECL_RFK_WM(0x7820, 0x00000fff, 0x080),
0722     RTW89_DECL_RFK_WM(0x7814, 0x01000000, 0x0),
0723 };
0724 
0725 RTW89_DECLARE_RFK_TBL(rtw8852c_tssi_track_defs_b);
0726 
0727 static const struct rtw89_reg5_def rtw8852c_tssi_txagc_ofst_mv_avg_defs_a[] = {
0728     RTW89_DECL_RFK_WM(0x58e4, 0x00003800, 0x1),
0729     RTW89_DECL_RFK_WM(0x58e4, 0x00004000, 0x0),
0730     RTW89_DECL_RFK_WM(0x58e4, 0x00008000, 0x1),
0731     RTW89_DECL_RFK_WM(0x58e4, 0x000f0000, 0x0),
0732     RTW89_DECL_RFK_WM(0x58e8, 0x0000003f, 0x03),
0733 };
0734 
0735 RTW89_DECLARE_RFK_TBL(rtw8852c_tssi_txagc_ofst_mv_avg_defs_a);
0736 
0737 static const struct rtw89_reg5_def rtw8852c_tssi_txagc_ofst_mv_avg_defs_b[] = {
0738     RTW89_DECL_RFK_WM(0x78e4, 0x00003800, 0x1),
0739     RTW89_DECL_RFK_WM(0x78e4, 0x00004000, 0x0),
0740     RTW89_DECL_RFK_WM(0x78e4, 0x00008000, 0x1),
0741     RTW89_DECL_RFK_WM(0x78e4, 0x000f0000, 0x0),
0742     RTW89_DECL_RFK_WM(0x78e8, 0x0000003f, 0x03),
0743 };
0744 
0745 RTW89_DECLARE_RFK_TBL(rtw8852c_tssi_txagc_ofst_mv_avg_defs_b);
0746 
0747 static const struct rtw89_reg5_def rtw8852c_tssi_enable_defs_a[] = {
0748     RTW89_DECL_RFK_WM(0x58e4, 0x00004000, 0x0),
0749     RTW89_DECL_RFK_WM(0x5820, 0x80000000, 0x0),
0750     RTW89_DECL_RFK_WM(0x5820, 0x80000000, 0x1),
0751     RTW89_DECL_RFK_WRF(0x0, 0x10055, 0x00080, 0x1),
0752     RTW89_DECL_RFK_WM(0x5818, 0x10000000, 0x1),
0753 };
0754 
0755 RTW89_DECLARE_RFK_TBL(rtw8852c_tssi_enable_defs_a);
0756 
0757 static const struct rtw89_reg5_def rtw8852c_tssi_enable_defs_b[] = {
0758     RTW89_DECL_RFK_WM(0x78e4, 0x00004000, 0x0),
0759     RTW89_DECL_RFK_WM(0x7820, 0x80000000, 0x0),
0760     RTW89_DECL_RFK_WM(0x7820, 0x80000000, 0x1),
0761     RTW89_DECL_RFK_WRF(0x1, 0x10055, 0x00080, 0x1),
0762     RTW89_DECL_RFK_WM(0x7818, 0x10000000, 0x1),
0763 };
0764 
0765 RTW89_DECLARE_RFK_TBL(rtw8852c_tssi_enable_defs_b);
0766 
0767 static const struct rtw89_reg5_def rtw8852c_tssi_disable_defs_a[] = {
0768     RTW89_DECL_RFK_WM(0x5820, 0x80000000, 0x00000000),
0769     RTW89_DECL_RFK_WM(0x5818, 0x10000000, 0x00000000),
0770     RTW89_DECL_RFK_WM(0x58e4, 0x00004000, 0x00000001),
0771 };
0772 
0773 RTW89_DECLARE_RFK_TBL(rtw8852c_tssi_disable_defs_a);
0774 
0775 static const struct rtw89_reg5_def rtw8852c_tssi_disable_defs_b[] = {
0776     RTW89_DECL_RFK_WM(0x7820, 0x80000000, 0x00000000),
0777     RTW89_DECL_RFK_WM(0x7818, 0x10000000, 0x00000000),
0778     RTW89_DECL_RFK_WM(0x78e4, 0x00004000, 0x00000001),
0779 };
0780 
0781 RTW89_DECLARE_RFK_TBL(rtw8852c_tssi_disable_defs_b);
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