realtek/rtw89/rtw8852c.c

0001 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
0002 /* Copyright(c) 2019-2022  Realtek Corporation
0003  */
0004
0005 #include "coex.h"
0006 #include "debug.h"
0007 #include "fw.h"
0008 #include "mac.h"
0009 #include "phy.h"
0010 #include "reg.h"
0011 #include "rtw8852c.h"
0012 #include "rtw8852c_rfk.h"
0013 #include "rtw8852c_table.h"
0014 #include "util.h"
0015
0016 static const struct rtw89_hfc_ch_cfg rtw8852c_hfc_chcfg_pcie[] = {
0017     {13, 1614, grp_0}, /* ACH 0 */
0018     {13, 1614, grp_0}, /* ACH 1 */
0019     {13, 1614, grp_0}, /* ACH 2 */
0020     {13, 1614, grp_0}, /* ACH 3 */
0021     {13, 1614, grp_1}, /* ACH 4 */
0022     {13, 1614, grp_1}, /* ACH 5 */
0023     {13, 1614, grp_1}, /* ACH 6 */
0024     {13, 1614, grp_1}, /* ACH 7 */
0025     {13, 1614, grp_0}, /* B0MGQ */
0026     {13, 1614, grp_0}, /* B0HIQ */
0027     {13, 1614, grp_1}, /* B1MGQ */
0028     {13, 1614, grp_1}, /* B1HIQ */
0029     {40, 0, 0} /* FWCMDQ */
0030 };
0031
0032 static const struct rtw89_hfc_pub_cfg rtw8852c_hfc_pubcfg_pcie = {
0033     1614, /* Group 0 */
0034     1614, /* Group 1 */
0035     3228, /* Public Max */
0036     0 /* WP threshold */
0037 };
0038
0039 static const struct rtw89_hfc_param_ini rtw8852c_hfc_param_ini_pcie[] = {
0040     [RTW89_QTA_SCC] = {rtw8852c_hfc_chcfg_pcie, &rtw8852c_hfc_pubcfg_pcie,
0041                &rtw89_mac_size.hfc_preccfg_pcie, RTW89_HCIFC_POH},
0042     [RTW89_QTA_DLFW] = {NULL, NULL, &rtw89_mac_size.hfc_preccfg_pcie,
0043                 RTW89_HCIFC_POH},
0044     [RTW89_QTA_INVALID] = {NULL},
0045 };
0046
0047 static const struct rtw89_dle_mem rtw8852c_dle_mem_pcie[] = {
0048     [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size19,
0049                &rtw89_mac_size.ple_size19, &rtw89_mac_size.wde_qt18,
0050                &rtw89_mac_size.wde_qt18, &rtw89_mac_size.ple_qt46,
0051                &rtw89_mac_size.ple_qt47},
0052     [RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size18,
0053                 &rtw89_mac_size.ple_size18, &rtw89_mac_size.wde_qt17,
0054                 &rtw89_mac_size.wde_qt17, &rtw89_mac_size.ple_qt44,
0055                 &rtw89_mac_size.ple_qt45},
0056     [RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL,
0057                    NULL},
0058 };
0059
0060 static const u32 rtw8852c_h2c_regs[RTW89_H2CREG_MAX] = {
0061     R_AX_H2CREG_DATA0_V1, R_AX_H2CREG_DATA1_V1, R_AX_H2CREG_DATA2_V1,
0062     R_AX_H2CREG_DATA3_V1
0063 };
0064
0065 static const u32 rtw8852c_c2h_regs[RTW89_H2CREG_MAX] = {
0066     R_AX_C2HREG_DATA0_V1, R_AX_C2HREG_DATA1_V1, R_AX_C2HREG_DATA2_V1,
0067     R_AX_C2HREG_DATA3_V1
0068 };
0069
0070 static const struct rtw89_page_regs rtw8852c_page_regs = {
0071     .hci_fc_ctrl    = R_AX_HCI_FC_CTRL_V1,
0072     .ch_page_ctrl   = R_AX_CH_PAGE_CTRL_V1,
0073     .ach_page_ctrl  = R_AX_ACH0_PAGE_CTRL_V1,
0074     .ach_page_info  = R_AX_ACH0_PAGE_INFO_V1,
0075     .pub_page_info3 = R_AX_PUB_PAGE_INFO3_V1,
0076     .pub_page_ctrl1 = R_AX_PUB_PAGE_CTRL1_V1,
0077     .pub_page_ctrl2 = R_AX_PUB_PAGE_CTRL2_V1,
0078     .pub_page_info1 = R_AX_PUB_PAGE_INFO1_V1,
0079     .pub_page_info2 = R_AX_PUB_PAGE_INFO2_V1,
0080     .wp_page_ctrl1  = R_AX_WP_PAGE_CTRL1_V1,
0081     .wp_page_ctrl2  = R_AX_WP_PAGE_CTRL2_V1,
0082     .wp_page_info1  = R_AX_WP_PAGE_INFO1_V1,
0083 };
0084
0085 static const struct rtw89_reg_def rtw8852c_dcfo_comp = {
0086     R_DCFO_COMP_S0_V1, B_DCFO_COMP_S0_V1_MSK
0087 };
0088
0089 static const struct rtw89_imr_info rtw8852c_imr_info = {
0090     .wdrls_imr_set      = B_AX_WDRLS_IMR_SET_V1,
0091     .wsec_imr_reg       = R_AX_SEC_ERROR_FLAG_IMR,
0092     .wsec_imr_set       = B_AX_TX_HANG_IMR | B_AX_RX_HANG_IMR,
0093     .mpdu_tx_imr_set    = B_AX_MPDU_TX_IMR_SET_V1,
0094     .mpdu_rx_imr_set    = B_AX_MPDU_RX_IMR_SET_V1,
0095     .sta_sch_imr_set    = B_AX_STA_SCHEDULER_IMR_SET,
0096     .txpktctl_imr_b0_reg    = R_AX_TXPKTCTL_B0_ERRFLAG_IMR,
0097     .txpktctl_imr_b0_clr    = B_AX_TXPKTCTL_IMR_B0_CLR_V1,
0098     .txpktctl_imr_b0_set    = B_AX_TXPKTCTL_IMR_B0_SET_V1,
0099     .txpktctl_imr_b1_reg    = R_AX_TXPKTCTL_B1_ERRFLAG_IMR,
0100     .txpktctl_imr_b1_clr    = B_AX_TXPKTCTL_IMR_B1_CLR_V1,
0101     .txpktctl_imr_b1_set    = B_AX_TXPKTCTL_IMR_B1_SET_V1,
0102     .wde_imr_clr        = B_AX_WDE_IMR_CLR_V1,
0103     .wde_imr_set        = B_AX_WDE_IMR_SET_V1,
0104     .ple_imr_clr        = B_AX_PLE_IMR_CLR_V1,
0105     .ple_imr_set        = B_AX_PLE_IMR_SET_V1,
0106     .host_disp_imr_clr  = B_AX_HOST_DISP_IMR_CLR_V1,
0107     .host_disp_imr_set  = B_AX_HOST_DISP_IMR_SET_V1,
0108     .cpu_disp_imr_clr   = B_AX_CPU_DISP_IMR_CLR_V1,
0109     .cpu_disp_imr_set   = B_AX_CPU_DISP_IMR_SET_V1,
0110     .other_disp_imr_clr = B_AX_OTHER_DISP_IMR_CLR_V1,
0111     .other_disp_imr_set = B_AX_OTHER_DISP_IMR_SET_V1,
0112     .bbrpt_chinfo_err_imr_reg = R_AX_BBRPT_CHINFO_ERR_IMR,
0113     .bbrpt_err_imr_set  = R_AX_BBRPT_CHINFO_IMR_SET_V1,
0114     .bbrpt_dfs_err_imr_reg  = R_AX_BBRPT_DFS_ERR_IMR,
0115     .ptcl_imr_clr       = B_AX_PTCL_IMR_CLR_V1,
0116     .ptcl_imr_set       = B_AX_PTCL_IMR_SET_V1,
0117     .cdma_imr_0_reg     = R_AX_RX_ERR_FLAG_IMR,
0118     .cdma_imr_0_clr     = B_AX_RX_ERR_IMR_CLR_V1,
0119     .cdma_imr_0_set     = B_AX_RX_ERR_IMR_SET_V1,
0120     .cdma_imr_1_reg     = R_AX_TX_ERR_FLAG_IMR,
0121     .cdma_imr_1_clr     = B_AX_TX_ERR_IMR_CLR_V1,
0122     .cdma_imr_1_set     = B_AX_TX_ERR_IMR_SET_V1,
0123     .phy_intf_imr_reg   = R_AX_PHYINFO_ERR_IMR_V1,
0124     .phy_intf_imr_clr   = B_AX_PHYINFO_IMR_CLR_V1,
0125     .phy_intf_imr_set   = B_AX_PHYINFO_IMR_SET_V1,
0126     .rmac_imr_reg       = R_AX_RX_ERR_IMR,
0127     .rmac_imr_clr       = B_AX_RMAC_IMR_CLR_V1,
0128     .rmac_imr_set       = B_AX_RMAC_IMR_SET_V1,
0129     .tmac_imr_reg       = R_AX_TRXPTCL_ERROR_INDICA_MASK,
0130     .tmac_imr_clr       = B_AX_TMAC_IMR_CLR_V1,
0131     .tmac_imr_set       = B_AX_TMAC_IMR_SET_V1,
0132 };
0133
0134 static void rtw8852c_ctrl_btg(struct rtw89_dev *rtwdev, bool btg);
0135
0136 static int rtw8852c_pwr_on_func(struct rtw89_dev *rtwdev)
0137 {
0138     u32 val32;
0139     u32 ret;
0140
0141     val32 = rtw89_read32_mask(rtwdev, R_AX_SYS_STATUS1, B_AX_PAD_HCI_SEL_V2_MASK);
0142     if (val32 == MAC_AX_HCI_SEL_PCIE_USB)
0143         rtw89_write32_set(rtwdev, R_AX_LDO_AON_CTRL0, B_AX_PD_REGU_L);
0144
0145     rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_AFSM_WLSUS_EN |
0146                             B_AX_AFSM_PCIE_SUS_EN);
0147     rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_DIS_WLBT_PDNSUSEN_SOPC);
0148     rtw89_write32_set(rtwdev, R_AX_WLLPS_CTRL, B_AX_DIS_WLBT_LPSEN_LOPC);
0149     rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APDM_HPDN);
0150     rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS);
0151
0152     ret = read_poll_timeout(rtw89_read32, val32, val32 & B_AX_RDY_SYSPWR,
0153                 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);
0154     if (ret)
0155         return ret;
0156
0157     rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON);
0158     rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFN_ONMAC);
0159
0160     ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFN_ONMAC),
0161                 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);
0162     if (ret)
0163         return ret;
0164
0165     rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
0166     rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
0167     rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
0168     rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
0169
0170     rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
0171     rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL, B_AX_PCIE_CALIB_EN_V1);
0172
0173     rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, B_AX_CMAC1_FEN);
0174     rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, B_AX_R_SYM_ISO_CMAC12PP);
0175     rtw89_write32_clr(rtwdev, R_AX_AFE_CTRL1, B_AX_R_SYM_WLCMAC1_P4_PC_EN |
0176                           B_AX_R_SYM_WLCMAC1_P3_PC_EN |
0177                           B_AX_R_SYM_WLCMAC1_P2_PC_EN |
0178                           B_AX_R_SYM_WLCMAC1_P1_PC_EN |
0179                           B_AX_R_SYM_WLCMAC1_PC_EN);
0180     rtw89_write32_set(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_PTA_1P3);
0181
0182     ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL,
0183                       XTAL_SI_GND_SHDN_WL, XTAL_SI_GND_SHDN_WL);
0184     if (ret)
0185         return ret;
0186
0187     rtw89_write32_set(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_RFC_1P3);
0188
0189     ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL,
0190                       XTAL_SI_SHDN_WL, XTAL_SI_SHDN_WL);
0191     if (ret)
0192         return ret;
0193     ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_WEI,
0194                       XTAL_SI_OFF_WEI);
0195     if (ret)
0196         return ret;
0197     ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_EI,
0198                       XTAL_SI_OFF_EI);
0199     if (ret)
0200         return ret;
0201     ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_RFC2RF);
0202     if (ret)
0203         return ret;
0204     ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_WEI,
0205                       XTAL_SI_PON_WEI);
0206     if (ret)
0207         return ret;
0208     ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_EI,
0209                       XTAL_SI_PON_EI);
0210     if (ret)
0211         return ret;
0212     ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SRAM2RFC);
0213     if (ret)
0214         return ret;
0215     ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_2, 0, XTAL_SI_LDO_LPS);
0216     if (ret)
0217         return ret;
0218     ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_4, 0, XTAL_SI_LPS_CAP);
0219     if (ret)
0220         return ret;
0221
0222     rtw89_write32_set(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK);
0223     rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_ISO_EB2CORE);
0224     rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B15);
0225
0226     fsleep(1000);
0227
0228     rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B14);
0229     rtw89_write32_clr(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK);
0230     rtw89_write32_set(rtwdev, R_AX_GPIO0_15_EECS_EESK_LED1_PULL_LOW_EN,
0231               B_AX_EECS_PULL_LOW_EN | B_AX_EESK_PULL_LOW_EN |
0232               B_AX_LED1_PULL_LOW_EN);
0233
0234     rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN,
0235               B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_MPDU_PROC_EN |
0236               B_AX_WD_RLS_EN | B_AX_DLE_WDE_EN | B_AX_TXPKT_CTRL_EN |
0237               B_AX_STA_SCH_EN | B_AX_DLE_PLE_EN | B_AX_PKT_BUF_EN |
0238               B_AX_DMAC_TBL_EN | B_AX_PKT_IN_EN | B_AX_DLE_CPUIO_EN |
0239               B_AX_DISPATCHER_EN | B_AX_BBRPT_EN | B_AX_MAC_SEC_EN |
0240               B_AX_MAC_UN_EN | B_AX_H_AXIDMA_EN);
0241
0242     rtw89_write32_set(rtwdev, R_AX_CMAC_FUNC_EN,
0243               B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN |
0244               B_AX_FORCE_CMACREG_GCKEN | B_AX_PHYINTF_EN |
0245               B_AX_CMAC_DMA_EN | B_AX_PTCLTOP_EN | B_AX_SCHEDULER_EN |
0246               B_AX_TMAC_EN | B_AX_RMAC_EN);
0247
0248     return 0;
0249 }
0250
0251 static int rtw8852c_pwr_off_func(struct rtw89_dev *rtwdev)
0252 {
0253     u32 val32;
0254     u32 ret;
0255
0256     ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_RFC2RF,
0257                       XTAL_SI_RFC2RF);
0258     if (ret)
0259         return ret;
0260     ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_EI);
0261     if (ret)
0262         return ret;
0263     ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_WEI);
0264     if (ret)
0265         return ret;
0266     ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0, XTAL_SI_RF00);
0267     if (ret)
0268         return ret;
0269     ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0, XTAL_SI_RF10);
0270     if (ret)
0271         return ret;
0272     ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_SRAM2RFC,
0273                       XTAL_SI_SRAM2RFC);
0274     if (ret)
0275         return ret;
0276     ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_EI);
0277     if (ret)
0278         return ret;
0279     ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_WEI);
0280     if (ret)
0281         return ret;
0282
0283     rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON);
0284     rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, B_AX_FEN_BB_GLB_RSTN | B_AX_FEN_BBRSTB);
0285     rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND,
0286               B_AX_R_SYM_FEN_WLBBGLB_1 | B_AX_R_SYM_FEN_WLBBFUN_1);
0287     rtw89_write32_clr(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_RFC_1P3);
0288
0289     ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SHDN_WL);
0290     if (ret)
0291         return ret;
0292
0293     rtw89_write32_clr(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_PTA_1P3);
0294
0295     ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_GND_SHDN_WL);
0296     if (ret)
0297         return ret;
0298
0299     rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_OFFMAC);
0300
0301     ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFM_OFFMAC),
0302                 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);
0303     if (ret)
0304         return ret;
0305
0306     rtw89_write32(rtwdev, R_AX_WLLPS_CTRL, 0x0001A0B0);
0307     rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_XTAL_OFF_A_DIE);
0308     rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS);
0309
0310     return 0;
0311 }
0312
0313 static void rtw8852c_e_efuse_parsing(struct rtw89_efuse *efuse,
0314                      struct rtw8852c_efuse *map)
0315 {
0316     ether_addr_copy(efuse->addr, map->e.mac_addr);
0317     efuse->rfe_type = map->rfe_type;
0318     efuse->xtal_cap = map->xtal_k;
0319 }
0320
0321 static void rtw8852c_efuse_parsing_tssi(struct rtw89_dev *rtwdev,
0322                     struct rtw8852c_efuse *map)
0323 {
0324     struct rtw89_tssi_info *tssi = &rtwdev->tssi;
0325     struct rtw8852c_tssi_offset *ofst[] = {&map->path_a_tssi, &map->path_b_tssi};
0326     u8 *bw40_1s_tssi_6g_ofst[] = {map->bw40_1s_tssi_6g_a, map->bw40_1s_tssi_6g_b};
0327     u8 i, j;
0328
0329     tssi->thermal[RF_PATH_A] = map->path_a_therm;
0330     tssi->thermal[RF_PATH_B] = map->path_b_therm;
0331
0332     for (i = 0; i < RF_PATH_NUM_8852C; i++) {
0333         memcpy(tssi->tssi_cck[i], ofst[i]->cck_tssi,
0334                sizeof(ofst[i]->cck_tssi));
0335
0336         for (j = 0; j < TSSI_CCK_CH_GROUP_NUM; j++)
0337             rtw89_debug(rtwdev, RTW89_DBG_TSSI,
0338                     "[TSSI][EFUSE] path=%d cck[%d]=0x%x\n",
0339                     i, j, tssi->tssi_cck[i][j]);
0340
0341         memcpy(tssi->tssi_mcs[i], ofst[i]->bw40_tssi,
0342                sizeof(ofst[i]->bw40_tssi));
0343         memcpy(tssi->tssi_mcs[i] + TSSI_MCS_2G_CH_GROUP_NUM,
0344                ofst[i]->bw40_1s_tssi_5g, sizeof(ofst[i]->bw40_1s_tssi_5g));
0345         memcpy(tssi->tssi_6g_mcs[i], bw40_1s_tssi_6g_ofst[i],
0346                sizeof(tssi->tssi_6g_mcs[i]));
0347
0348         for (j = 0; j < TSSI_MCS_CH_GROUP_NUM; j++)
0349             rtw89_debug(rtwdev, RTW89_DBG_TSSI,
0350                     "[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n",
0351                     i, j, tssi->tssi_mcs[i][j]);
0352     }
0353 }
0354
0355 static bool _decode_efuse_gain(u8 data, s8 *high, s8 *low)
0356 {
0357     if (high)
0358         *high = sign_extend32(FIELD_GET(GENMASK(7,  4), data), 3);
0359     if (low)
0360         *low = sign_extend32(FIELD_GET(GENMASK(3,  0), data), 3);
0361
0362     return data != 0xff;
0363 }
0364
0365 static void rtw8852c_efuse_parsing_gain_offset(struct rtw89_dev *rtwdev,
0366                            struct rtw8852c_efuse *map)
0367 {
0368     struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
0369     bool valid = false;
0370
0371     valid |= _decode_efuse_gain(map->rx_gain_2g_cck,
0372                     &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_CCK],
0373                     &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_2G_CCK]);
0374     valid |= _decode_efuse_gain(map->rx_gain_2g_ofdm,
0375                     &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_OFDM],
0376                     &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_2G_OFDM]);
0377     valid |= _decode_efuse_gain(map->rx_gain_5g_low,
0378                     &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_LOW],
0379                     &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_LOW]);
0380     valid |= _decode_efuse_gain(map->rx_gain_5g_mid,
0381                     &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_MID],
0382                     &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_MID]);
0383     valid |= _decode_efuse_gain(map->rx_gain_5g_high,
0384                     &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_HIGH],
0385                     &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_HIGH]);
0386
0387     gain->offset_valid = valid;
0388 }
0389
0390 static int rtw8852c_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map)
0391 {
0392     struct rtw89_efuse *efuse = &rtwdev->efuse;
0393     struct rtw8852c_efuse *map;
0394
0395     map = (struct rtw8852c_efuse *)log_map;
0396
0397     efuse->country_code[0] = map->country_code[0];
0398     efuse->country_code[1] = map->country_code[1];
0399     rtw8852c_efuse_parsing_tssi(rtwdev, map);
0400     rtw8852c_efuse_parsing_gain_offset(rtwdev, map);
0401
0402     switch (rtwdev->hci.type) {
0403     case RTW89_HCI_TYPE_PCIE:
0404         rtw8852c_e_efuse_parsing(efuse, map);
0405         break;
0406     default:
0407         return -ENOTSUPP;
0408     }
0409
0410     rtw89_info(rtwdev, "chip rfe_type is %d\n", efuse->rfe_type);
0411
0412     return 0;
0413 }
0414
0415 static void rtw8852c_phycap_parsing_tssi(struct rtw89_dev *rtwdev, u8 *phycap_map)
0416 {
0417     struct rtw89_tssi_info *tssi = &rtwdev->tssi;
0418     static const u32 tssi_trim_addr[RF_PATH_NUM_8852C] = {0x5D6, 0x5AB};
0419     static const u32 tssi_trim_addr_6g[RF_PATH_NUM_8852C] = {0x5CE, 0x5A3};
0420     u32 addr = rtwdev->chip->phycap_addr;
0421     bool pg = false;
0422     u32 ofst;
0423     u8 i, j;
0424
0425     for (i = 0; i < RF_PATH_NUM_8852C; i++) {
0426         for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) {
0427             /* addrs are in decreasing order */
0428             ofst = tssi_trim_addr[i] - addr - j;
0429             tssi->tssi_trim[i][j] = phycap_map[ofst];
0430
0431             if (phycap_map[ofst] != 0xff)
0432                 pg = true;
0433         }
0434
0435         for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM_6G; j++) {
0436             /* addrs are in decreasing order */
0437             ofst = tssi_trim_addr_6g[i] - addr - j;
0438             tssi->tssi_trim_6g[i][j] = phycap_map[ofst];
0439
0440             if (phycap_map[ofst] != 0xff)
0441                 pg = true;
0442         }
0443     }
0444
0445     if (!pg) {
0446         memset(tssi->tssi_trim, 0, sizeof(tssi->tssi_trim));
0447         memset(tssi->tssi_trim_6g, 0, sizeof(tssi->tssi_trim_6g));
0448         rtw89_debug(rtwdev, RTW89_DBG_TSSI,
0449                 "[TSSI][TRIM] no PG, set all trim info to 0\n");
0450     }
0451
0452     for (i = 0; i < RF_PATH_NUM_8852C; i++)
0453         for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++)
0454             rtw89_debug(rtwdev, RTW89_DBG_TSSI,
0455                     "[TSSI] path=%d idx=%d trim=0x%x addr=0x%x\n",
0456                     i, j, tssi->tssi_trim[i][j],
0457                     tssi_trim_addr[i] - j);
0458 }
0459
0460 static void rtw8852c_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev,
0461                          u8 *phycap_map)
0462 {
0463     struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
0464     static const u32 thm_trim_addr[RF_PATH_NUM_8852C] = {0x5DF, 0x5DC};
0465     u32 addr = rtwdev->chip->phycap_addr;
0466     u8 i;
0467
0468     for (i = 0; i < RF_PATH_NUM_8852C; i++) {
0469         info->thermal_trim[i] = phycap_map[thm_trim_addr[i] - addr];
0470
0471         rtw89_debug(rtwdev, RTW89_DBG_RFK,
0472                 "[THERMAL][TRIM] path=%d thermal_trim=0x%x\n",
0473                 i, info->thermal_trim[i]);
0474
0475         if (info->thermal_trim[i] != 0xff)
0476             info->pg_thermal_trim = true;
0477     }
0478 }
0479
0480 static void rtw8852c_thermal_trim(struct rtw89_dev *rtwdev)
0481 {
0482 #define __thm_setting(raw)              \
0483 ({                          \
0484     u8 __v = (raw);                 \
0485     ((__v & 0x1) << 3) | ((__v & 0x1f) >> 1);   \
0486 })
0487     struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
0488     u8 i, val;
0489
0490     if (!info->pg_thermal_trim) {
0491         rtw89_debug(rtwdev, RTW89_DBG_RFK,
0492                 "[THERMAL][TRIM] no PG, do nothing\n");
0493
0494         return;
0495     }
0496
0497     for (i = 0; i < RF_PATH_NUM_8852C; i++) {
0498         val = __thm_setting(info->thermal_trim[i]);
0499         rtw89_write_rf(rtwdev, i, RR_TM2, RR_TM2_OFF, val);
0500
0501         rtw89_debug(rtwdev, RTW89_DBG_RFK,
0502                 "[THERMAL][TRIM] path=%d thermal_setting=0x%x\n",
0503                 i, val);
0504     }
0505 #undef __thm_setting
0506 }
0507
0508 static void rtw8852c_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev,
0509                          u8 *phycap_map)
0510 {
0511     struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
0512     static const u32 pabias_trim_addr[RF_PATH_NUM_8852C] = {0x5DE, 0x5DB};
0513     u32 addr = rtwdev->chip->phycap_addr;
0514     u8 i;
0515
0516     for (i = 0; i < RF_PATH_NUM_8852C; i++) {
0517         info->pa_bias_trim[i] = phycap_map[pabias_trim_addr[i] - addr];
0518
0519         rtw89_debug(rtwdev, RTW89_DBG_RFK,
0520                 "[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n",
0521                 i, info->pa_bias_trim[i]);
0522
0523         if (info->pa_bias_trim[i] != 0xff)
0524             info->pg_pa_bias_trim = true;
0525     }
0526 }
0527
0528 static void rtw8852c_pa_bias_trim(struct rtw89_dev *rtwdev)
0529 {
0530     struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
0531     u8 pabias_2g, pabias_5g;
0532     u8 i;
0533
0534     if (!info->pg_pa_bias_trim) {
0535         rtw89_debug(rtwdev, RTW89_DBG_RFK,
0536                 "[PA_BIAS][TRIM] no PG, do nothing\n");
0537
0538         return;
0539     }
0540
0541     for (i = 0; i < RF_PATH_NUM_8852C; i++) {
0542         pabias_2g = FIELD_GET(GENMASK(3, 0), info->pa_bias_trim[i]);
0543         pabias_5g = FIELD_GET(GENMASK(7, 4), info->pa_bias_trim[i]);
0544
0545         rtw89_debug(rtwdev, RTW89_DBG_RFK,
0546                 "[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n",
0547                 i, pabias_2g, pabias_5g);
0548
0549         rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXG, pabias_2g);
0550         rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXA, pabias_5g);
0551     }
0552 }
0553
0554 static int rtw8852c_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map)
0555 {
0556     rtw8852c_phycap_parsing_tssi(rtwdev, phycap_map);
0557     rtw8852c_phycap_parsing_thermal_trim(rtwdev, phycap_map);
0558     rtw8852c_phycap_parsing_pa_bias_trim(rtwdev, phycap_map);
0559
0560     return 0;
0561 }
0562
0563 static void rtw8852c_power_trim(struct rtw89_dev *rtwdev)
0564 {
0565     rtw8852c_thermal_trim(rtwdev);
0566     rtw8852c_pa_bias_trim(rtwdev);
0567 }
0568
0569 static void rtw8852c_set_channel_mac(struct rtw89_dev *rtwdev,
0570                      struct rtw89_channel_params *param,
0571                      u8 mac_idx)
0572 {
0573     u32 rf_mod = rtw89_mac_reg_by_idx(R_AX_WMAC_RFMOD, mac_idx);
0574     u32 sub_carr = rtw89_mac_reg_by_idx(R_AX_TX_SUB_CARRIER_VALUE,
0575                          mac_idx);
0576     u32 chk_rate = rtw89_mac_reg_by_idx(R_AX_TXRATE_CHK, mac_idx);
0577     u8 txsc20 = 0, txsc40 = 0, txsc80 = 0;
0578     u8 rf_mod_val = 0, chk_rate_mask = 0;
0579     u32 txsc;
0580
0581     switch (param->bandwidth) {
0582     case RTW89_CHANNEL_WIDTH_160:
0583         txsc80 = rtw89_phy_get_txsc(rtwdev, param,
0584                         RTW89_CHANNEL_WIDTH_80);
0585         fallthrough;
0586     case RTW89_CHANNEL_WIDTH_80:
0587         txsc40 = rtw89_phy_get_txsc(rtwdev, param,
0588                         RTW89_CHANNEL_WIDTH_40);
0589         fallthrough;
0590     case RTW89_CHANNEL_WIDTH_40:
0591         txsc20 = rtw89_phy_get_txsc(rtwdev, param,
0592                         RTW89_CHANNEL_WIDTH_20);
0593         break;
0594     default:
0595         break;
0596     }
0597
0598     switch (param->bandwidth) {
0599     case RTW89_CHANNEL_WIDTH_160:
0600         rf_mod_val = AX_WMAC_RFMOD_160M;
0601         txsc = FIELD_PREP(B_AX_TXSC_20M_MASK, txsc20) |
0602                FIELD_PREP(B_AX_TXSC_40M_MASK, txsc40) |
0603                FIELD_PREP(B_AX_TXSC_80M_MASK, txsc80);
0604         break;
0605     case RTW89_CHANNEL_WIDTH_80:
0606         rf_mod_val = AX_WMAC_RFMOD_80M;
0607         txsc = FIELD_PREP(B_AX_TXSC_20M_MASK, txsc20) |
0608                FIELD_PREP(B_AX_TXSC_40M_MASK, txsc40);
0609         break;
0610     case RTW89_CHANNEL_WIDTH_40:
0611         rf_mod_val = AX_WMAC_RFMOD_40M;
0612         txsc = FIELD_PREP(B_AX_TXSC_20M_MASK, txsc20);
0613         break;
0614     case RTW89_CHANNEL_WIDTH_20:
0615     default:
0616         rf_mod_val = AX_WMAC_RFMOD_20M;
0617         txsc = 0;
0618         break;
0619     }
0620     rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, rf_mod_val);
0621     rtw89_write32(rtwdev, sub_carr, txsc);
0622
0623     switch (param->band_type) {
0624     case RTW89_BAND_2G:
0625         chk_rate_mask = B_AX_BAND_MODE;
0626         break;
0627     case RTW89_BAND_5G:
0628     case RTW89_BAND_6G:
0629         chk_rate_mask = B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6;
0630         break;
0631     default:
0632         rtw89_warn(rtwdev, "Invalid band_type:%d\n", param->band_type);
0633         return;
0634     }
0635     rtw89_write8_clr(rtwdev, chk_rate, B_AX_BAND_MODE | B_AX_CHECK_CCK_EN |
0636                        B_AX_RTS_LIMIT_IN_OFDM6);
0637     rtw89_write8_set(rtwdev, chk_rate, chk_rate_mask);
0638 }
0639
0640 static const u32 rtw8852c_sco_barker_threshold[14] = {
0641     0x1fe4f, 0x1ff5e, 0x2006c, 0x2017b, 0x2028a, 0x20399, 0x204a8, 0x205b6,
0642     0x206c5, 0x207d4, 0x208e3, 0x209f2, 0x20b00, 0x20d8a
0643 };
0644
0645 static const u32 rtw8852c_sco_cck_threshold[14] = {
0646     0x2bdac, 0x2bf21, 0x2c095, 0x2c209, 0x2c37e, 0x2c4f2, 0x2c666, 0x2c7db,
0647     0x2c94f, 0x2cac3, 0x2cc38, 0x2cdac, 0x2cf21, 0x2d29e
0648 };
0649
0650 static int rtw8852c_ctrl_sco_cck(struct rtw89_dev *rtwdev, u8 central_ch,
0651                  u8 primary_ch, enum rtw89_bandwidth bw)
0652 {
0653     u8 ch_element;
0654
0655     if (bw == RTW89_CHANNEL_WIDTH_20) {
0656         ch_element = central_ch - 1;
0657     } else if (bw == RTW89_CHANNEL_WIDTH_40) {
0658         if (primary_ch == 1)
0659             ch_element = central_ch - 1 + 2;
0660         else
0661             ch_element = central_ch - 1 - 2;
0662     } else {
0663         rtw89_warn(rtwdev, "Invalid BW:%d for CCK\n", bw);
0664         return -EINVAL;
0665     }
0666     rtw89_phy_write32_mask(rtwdev, R_BK_FC0_INV_V1, B_BK_FC0_INV_MSK_V1,
0667                    rtw8852c_sco_barker_threshold[ch_element]);
0668     rtw89_phy_write32_mask(rtwdev, R_CCK_FC0_INV_V1, B_CCK_FC0_INV_MSK_V1,
0669                    rtw8852c_sco_cck_threshold[ch_element]);
0670
0671     return 0;
0672 }
0673
0674 struct rtw8852c_bb_gain {
0675     u32 gain_g[BB_PATH_NUM_8852C];
0676     u32 gain_a[BB_PATH_NUM_8852C];
0677     u32 gain_mask;
0678 };
0679
0680 static const struct rtw8852c_bb_gain bb_gain_lna[LNA_GAIN_NUM] = {
0681     { .gain_g = {0x4678, 0x475C}, .gain_a = {0x45DC, 0x4740},
0682       .gain_mask = 0x00ff0000 },
0683     { .gain_g = {0x4678, 0x475C}, .gain_a = {0x45DC, 0x4740},
0684       .gain_mask = 0xff000000 },
0685     { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744},
0686       .gain_mask = 0x000000ff },
0687     { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744},
0688       .gain_mask = 0x0000ff00 },
0689     { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744},
0690       .gain_mask = 0x00ff0000 },
0691     { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744},
0692       .gain_mask = 0xff000000 },
0693     { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748},
0694       .gain_mask = 0x000000ff },
0695 };
0696
0697 static const struct rtw8852c_bb_gain bb_gain_tia[TIA_GAIN_NUM] = {
0698     { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748},
0699       .gain_mask = 0x00ff0000 },
0700     { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748},
0701       .gain_mask = 0xff000000 },
0702 };
0703
0704 struct rtw8852c_bb_gain_bypass {
0705     u32 gain_g[BB_PATH_NUM_8852C];
0706     u32 gain_a[BB_PATH_NUM_8852C];
0707     u32 gain_mask_g;
0708     u32 gain_mask_a;
0709 };
0710
0711 static
0712 const struct rtw8852c_bb_gain_bypass bb_gain_bypass_lna[LNA_GAIN_NUM] = {
0713     { .gain_g = {0x4BB8, 0x4C7C}, .gain_a = {0x4BB4, 0x4C78},
0714       .gain_mask_g = 0xff000000, .gain_mask_a = 0xff},
0715     { .gain_g = {0x4BBC, 0x4C80}, .gain_a = {0x4BB4, 0x4C78},
0716       .gain_mask_g = 0xff, .gain_mask_a = 0xff00},
0717     { .gain_g = {0x4BBC, 0x4C80}, .gain_a = {0x4BB4, 0x4C78},
0718       .gain_mask_g = 0xff00, .gain_mask_a = 0xff0000},
0719     { .gain_g = {0x4BBC, 0x4C80}, .gain_a = {0x4BB4, 0x4C78},
0720       .gain_mask_g = 0xff0000, .gain_mask_a = 0xff000000},
0721     { .gain_g = {0x4BBC, 0x4C80}, .gain_a = {0x4BB8, 0x4C7C},
0722       .gain_mask_g = 0xff000000, .gain_mask_a = 0xff},
0723     { .gain_g = {0x4BC0, 0x4C84}, .gain_a = {0x4BB8, 0x4C7C},
0724       .gain_mask_g = 0xff, .gain_mask_a = 0xff00},
0725     { .gain_g = {0x4BC0, 0x4C84}, .gain_a = {0x4BB8, 0x4C7C},
0726       .gain_mask_g = 0xff00, .gain_mask_a = 0xff0000},
0727 };
0728
0729 struct rtw8852c_bb_gain_op1db {
0730     struct {
0731         u32 lna[BB_PATH_NUM_8852C];
0732         u32 tia_lna[BB_PATH_NUM_8852C];
0733         u32 mask;
0734     } reg[LNA_GAIN_NUM];
0735     u32 reg_tia0_lna6[BB_PATH_NUM_8852C];
0736     u32 mask_tia0_lna6;
0737 };
0738
0739 static const struct rtw8852c_bb_gain_op1db bb_gain_op1db_a = {
0740     .reg = {
0741         { .lna = {0x4668, 0x474c}, .tia_lna = {0x4670, 0x4754},
0742           .mask = 0xff},
0743         { .lna = {0x4668, 0x474c}, .tia_lna = {0x4670, 0x4754},
0744           .mask = 0xff00},
0745         { .lna = {0x4668, 0x474c}, .tia_lna = {0x4670, 0x4754},
0746           .mask = 0xff0000},
0747         { .lna = {0x4668, 0x474c}, .tia_lna = {0x4670, 0x4754},
0748           .mask = 0xff000000},
0749         { .lna = {0x466c, 0x4750}, .tia_lna = {0x4674, 0x4758},
0750           .mask = 0xff},
0751         { .lna = {0x466c, 0x4750}, .tia_lna = {0x4674, 0x4758},
0752           .mask = 0xff00},
0753         { .lna = {0x466c, 0x4750}, .tia_lna = {0x4674, 0x4758},
0754           .mask = 0xff0000},
0755     },
0756     .reg_tia0_lna6 = {0x4674, 0x4758},
0757     .mask_tia0_lna6 = 0xff000000,
0758 };
0759
0760 static enum rtw89_phy_bb_gain_band
0761 rtw8852c_mapping_gain_band(enum rtw89_subband subband)
0762 {
0763     switch (subband) {
0764     default:
0765     case RTW89_CH_2G:
0766         return RTW89_BB_GAIN_BAND_2G;
0767     case RTW89_CH_5G_BAND_1:
0768         return RTW89_BB_GAIN_BAND_5G_L;
0769     case RTW89_CH_5G_BAND_3:
0770         return RTW89_BB_GAIN_BAND_5G_M;
0771     case RTW89_CH_5G_BAND_4:
0772         return RTW89_BB_GAIN_BAND_5G_H;
0773     case RTW89_CH_6G_BAND_IDX0:
0774     case RTW89_CH_6G_BAND_IDX1:
0775         return RTW89_BB_GAIN_BAND_6G_L;
0776     case RTW89_CH_6G_BAND_IDX2:
0777     case RTW89_CH_6G_BAND_IDX3:
0778         return RTW89_BB_GAIN_BAND_6G_M;
0779     case RTW89_CH_6G_BAND_IDX4:
0780     case RTW89_CH_6G_BAND_IDX5:
0781         return RTW89_BB_GAIN_BAND_6G_H;
0782     case RTW89_CH_6G_BAND_IDX6:
0783     case RTW89_CH_6G_BAND_IDX7:
0784         return RTW89_BB_GAIN_BAND_6G_UH;
0785     }
0786 }
0787
0788 static void rtw8852c_set_gain_error(struct rtw89_dev *rtwdev,
0789                     enum rtw89_subband subband,
0790                     enum rtw89_rf_path path)
0791 {
0792     const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain;
0793     u8 gain_band = rtw8852c_mapping_gain_band(subband);
0794     s32 val;
0795     u32 reg;
0796     u32 mask;
0797     int i;
0798
0799     for (i = 0; i < LNA_GAIN_NUM; i++) {
0800         if (subband == RTW89_CH_2G)
0801             reg = bb_gain_lna[i].gain_g[path];
0802         else
0803             reg = bb_gain_lna[i].gain_a[path];
0804
0805         mask = bb_gain_lna[i].gain_mask;
0806         val = gain->lna_gain[gain_band][path][i];
0807         rtw89_phy_write32_mask(rtwdev, reg, mask, val);
0808
0809         if (subband == RTW89_CH_2G) {
0810             reg = bb_gain_bypass_lna[i].gain_g[path];
0811             mask = bb_gain_bypass_lna[i].gain_mask_g;
0812         } else {
0813             reg = bb_gain_bypass_lna[i].gain_a[path];
0814             mask = bb_gain_bypass_lna[i].gain_mask_a;
0815         }
0816
0817         val = gain->lna_gain_bypass[gain_band][path][i];
0818         rtw89_phy_write32_mask(rtwdev, reg, mask, val);
0819
0820         if (subband != RTW89_CH_2G) {
0821             reg = bb_gain_op1db_a.reg[i].lna[path];
0822             mask = bb_gain_op1db_a.reg[i].mask;
0823             val = gain->lna_op1db[gain_band][path][i];
0824             rtw89_phy_write32_mask(rtwdev, reg, mask, val);
0825
0826             reg = bb_gain_op1db_a.reg[i].tia_lna[path];
0827             mask = bb_gain_op1db_a.reg[i].mask;
0828             val = gain->tia_lna_op1db[gain_band][path][i];
0829             rtw89_phy_write32_mask(rtwdev, reg, mask, val);
0830         }
0831     }
0832
0833     if (subband != RTW89_CH_2G) {
0834         reg = bb_gain_op1db_a.reg_tia0_lna6[path];
0835         mask = bb_gain_op1db_a.mask_tia0_lna6;
0836         val = gain->tia_lna_op1db[gain_band][path][7];
0837         rtw89_phy_write32_mask(rtwdev, reg, mask, val);
0838     }
0839
0840     for (i = 0; i < TIA_GAIN_NUM; i++) {
0841         if (subband == RTW89_CH_2G)
0842             reg = bb_gain_tia[i].gain_g[path];
0843         else
0844             reg = bb_gain_tia[i].gain_a[path];
0845
0846         mask = bb_gain_tia[i].gain_mask;
0847         val = gain->tia_gain[gain_band][path][i];
0848         rtw89_phy_write32_mask(rtwdev, reg, mask, val);
0849     }
0850 }
0851
0852 static
0853 const u8 rtw8852c_ch_base_table[16] = {1, 0xff,
0854                        36, 100, 132, 149, 0xff,
0855                        1, 33, 65, 97, 129, 161, 193, 225, 0xff};
0856 #define RTW8852C_CH_BASE_IDX_2G     0
0857 #define RTW8852C_CH_BASE_IDX_5G_FIRST   2
0858 #define RTW8852C_CH_BASE_IDX_5G_LAST    5
0859 #define RTW8852C_CH_BASE_IDX_6G_FIRST   7
0860 #define RTW8852C_CH_BASE_IDX_6G_LAST    14
0861
0862 #define RTW8852C_CH_BASE_IDX_MASK   GENMASK(7, 4)
0863 #define RTW8852C_CH_OFFSET_MASK     GENMASK(3, 0)
0864
0865 static u8 rtw8852c_encode_chan_idx(struct rtw89_dev *rtwdev, u8 central_ch, u8 band)
0866 {
0867     u8 chan_idx;
0868     u8 last, first;
0869     u8 idx;
0870
0871     switch (band) {
0872     case RTW89_BAND_2G:
0873         chan_idx = FIELD_PREP(RTW8852C_CH_BASE_IDX_MASK, RTW8852C_CH_BASE_IDX_2G) |
0874                FIELD_PREP(RTW8852C_CH_OFFSET_MASK, central_ch);
0875         return chan_idx;
0876     case RTW89_BAND_5G:
0877         first = RTW8852C_CH_BASE_IDX_5G_FIRST;
0878         last = RTW8852C_CH_BASE_IDX_5G_LAST;
0879         break;
0880     case RTW89_BAND_6G:
0881         first = RTW8852C_CH_BASE_IDX_6G_FIRST;
0882         last = RTW8852C_CH_BASE_IDX_6G_LAST;
0883         break;
0884     default:
0885         rtw89_warn(rtwdev, "Unsupported band %d\n", band);
0886         return 0;
0887     }
0888
0889     for (idx = last; idx >= first; idx--)
0890         if (central_ch >= rtw8852c_ch_base_table[idx])
0891             break;
0892
0893     if (idx < first) {
0894         rtw89_warn(rtwdev, "Unknown band %d channel %d\n", band, central_ch);
0895         return 0;
0896     }
0897
0898     chan_idx = FIELD_PREP(RTW8852C_CH_BASE_IDX_MASK, idx) |
0899            FIELD_PREP(RTW8852C_CH_OFFSET_MASK,
0900                   (central_ch - rtw8852c_ch_base_table[idx]) >> 1);
0901     return chan_idx;
0902 }
0903
0904 static void rtw8852c_decode_chan_idx(struct rtw89_dev *rtwdev, u8 chan_idx,
0905                      u8 *ch, enum nl80211_band *band)
0906 {
0907     u8 idx, offset;
0908
0909     idx = FIELD_GET(RTW8852C_CH_BASE_IDX_MASK, chan_idx);
0910     offset = FIELD_GET(RTW8852C_CH_OFFSET_MASK, chan_idx);
0911
0912     if (idx == RTW8852C_CH_BASE_IDX_2G) {
0913         *band = NL80211_BAND_2GHZ;
0914         *ch = offset;
0915         return;
0916     }
0917
0918     *band = idx <= RTW8852C_CH_BASE_IDX_5G_LAST ? NL80211_BAND_5GHZ : NL80211_BAND_6GHZ;
0919     *ch = rtw8852c_ch_base_table[idx] + (offset << 1);
0920 }
0921
0922 static void rtw8852c_set_gain_offset(struct rtw89_dev *rtwdev,
0923                      const struct rtw89_channel_params *param,
0924                      enum rtw89_phy_idx phy_idx,
0925                      enum rtw89_rf_path path)
0926 {
0927     static const u32 rssi_ofst_addr[2] = {R_PATH0_G_TIA0_LNA6_OP1DB_V1,
0928                           R_PATH1_G_TIA0_LNA6_OP1DB_V1};
0929     static const u32 rpl_mask[2] = {B_RPL_PATHA_MASK, B_RPL_PATHB_MASK};
0930     static const u32 rpl_tb_mask[2] = {B_RSSI_M_PATHA_MASK, B_RSSI_M_PATHB_MASK};
0931     struct rtw89_phy_efuse_gain *efuse_gain = &rtwdev->efuse_gain;
0932     enum rtw89_gain_offset gain_band;
0933     s32 offset_q0, offset_base_q4;
0934     s32 tmp = 0;
0935
0936     if (!efuse_gain->offset_valid)
0937         return;
0938
0939     if (rtwdev->dbcc_en && path == RF_PATH_B)
0940         phy_idx = RTW89_PHY_1;
0941
0942     if (param->band_type == RTW89_BAND_2G) {
0943         offset_q0 = efuse_gain->offset[path][RTW89_GAIN_OFFSET_2G_CCK];
0944         offset_base_q4 = efuse_gain->offset_base[phy_idx];
0945
0946         tmp = clamp_t(s32, (-offset_q0 << 3) + (offset_base_q4 >> 1),
0947                   S8_MIN >> 1, S8_MAX >> 1);
0948         rtw89_phy_write32_mask(rtwdev, R_RPL_OFST, B_RPL_OFST_MASK, tmp & 0x7f);
0949     }
0950
0951     switch (param->subband_type) {
0952     default:
0953     case RTW89_CH_2G:
0954         gain_band = RTW89_GAIN_OFFSET_2G_OFDM;
0955         break;
0956     case RTW89_CH_5G_BAND_1:
0957         gain_band = RTW89_GAIN_OFFSET_5G_LOW;
0958         break;
0959     case RTW89_CH_5G_BAND_3:
0960         gain_band = RTW89_GAIN_OFFSET_5G_MID;
0961         break;
0962     case RTW89_CH_5G_BAND_4:
0963         gain_band = RTW89_GAIN_OFFSET_5G_HIGH;
0964         break;
0965     }
0966
0967     offset_q0 = -efuse_gain->offset[path][gain_band];
0968     offset_base_q4 = efuse_gain->offset_base[phy_idx];
0969
0970     tmp = (offset_q0 << 2) + (offset_base_q4 >> 2);
0971     tmp = clamp_t(s32, -tmp, S8_MIN, S8_MAX);
0972     rtw89_phy_write32_mask(rtwdev, rssi_ofst_addr[path], B_PATH0_R_G_OFST_MASK, tmp & 0xff);
0973
0974     tmp = clamp_t(s32, offset_q0 << 4, S8_MIN, S8_MAX);
0975     rtw89_phy_write32_idx(rtwdev, R_RPL_PATHAB, rpl_mask[path], tmp & 0xff, phy_idx);
0976     rtw89_phy_write32_idx(rtwdev, R_RSSI_M_PATHAB, rpl_tb_mask[path], tmp & 0xff, phy_idx);
0977 }
0978
0979 static void rtw8852c_ctrl_ch(struct rtw89_dev *rtwdev,
0980                  const struct rtw89_channel_params *param,
0981                  enum rtw89_phy_idx phy_idx)
0982 {
0983     u8 sco;
0984     u16 central_freq = param->center_freq;
0985     u8 central_ch = param->center_chan;
0986     u8 band = param->band_type;
0987     u8 subband = param->subband_type;
0988     bool is_2g = band == RTW89_BAND_2G;
0989     u8 chan_idx;
0990
0991     if (!central_freq) {
0992         rtw89_warn(rtwdev, "Invalid central_freq\n");
0993         return;
0994     }
0995
0996     if (phy_idx == RTW89_PHY_0) {
0997         /* Path A */
0998         rtw8852c_set_gain_error(rtwdev, subband, RF_PATH_A);
0999         rtw8852c_set_gain_offset(rtwdev, param, phy_idx, RF_PATH_A);
1000
1001         if (is_2g)
1002             rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1,
1003                           B_PATH0_BAND_SEL_MSK_V1, 1,
1004                           phy_idx);
1005         else
1006             rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1,
1007                           B_PATH0_BAND_SEL_MSK_V1, 0,
1008                           phy_idx);
1009         /* Path B */
1010         if (!rtwdev->dbcc_en) {
1011             rtw8852c_set_gain_error(rtwdev, subband, RF_PATH_B);
1012             rtw8852c_set_gain_offset(rtwdev, param, phy_idx, RF_PATH_B);
1013
1014             if (is_2g)
1015                 rtw89_phy_write32_idx(rtwdev,
1016                               R_PATH1_BAND_SEL_V1,
1017                               B_PATH1_BAND_SEL_MSK_V1,
1018                               1, phy_idx);
1019             else
1020                 rtw89_phy_write32_idx(rtwdev,
1021                               R_PATH1_BAND_SEL_V1,
1022                               B_PATH1_BAND_SEL_MSK_V1,
1023                               0, phy_idx);
1024             rtw89_phy_write32_clr(rtwdev, R_2P4G_BAND, B_2P4G_BAND_SEL);
1025         } else {
1026             if (is_2g)
1027                 rtw89_phy_write32_clr(rtwdev, R_2P4G_BAND, B_2P4G_BAND_SEL);
1028             else
1029                 rtw89_phy_write32_set(rtwdev, R_2P4G_BAND, B_2P4G_BAND_SEL);
1030         }
1031         /* SCO compensate FC setting */
1032         rtw89_phy_write32_idx(rtwdev, R_FC0_V1, B_FC0_MSK_V1,
1033                       central_freq, phy_idx);
1034         /* round_up((1/fc0)*pow(2,18)) */
1035         sco = DIV_ROUND_CLOSEST(1 << 18, central_freq);
1036         rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV, sco,
1037                       phy_idx);
1038     } else {
1039         /* Path B */
1040         rtw8852c_set_gain_error(rtwdev, subband, RF_PATH_B);
1041         rtw8852c_set_gain_offset(rtwdev, param, phy_idx, RF_PATH_B);
1042
1043         if (is_2g)
1044             rtw89_phy_write32_idx(rtwdev, R_PATH1_BAND_SEL_V1,
1045                           B_PATH1_BAND_SEL_MSK_V1,
1046                           1, phy_idx);
1047         else
1048             rtw89_phy_write32_idx(rtwdev, R_PATH1_BAND_SEL_V1,
1049                           B_PATH1_BAND_SEL_MSK_V1,
1050                           0, phy_idx);
1051         /* SCO compensate FC setting */
1052         rtw89_phy_write32_idx(rtwdev, R_FC0_V1, B_FC0_MSK_V1,
1053                       central_freq, phy_idx);
1054         /* round_up((1/fc0)*pow(2,18)) */
1055         sco = DIV_ROUND_CLOSEST(1 << 18, central_freq);
1056         rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV, sco,
1057                       phy_idx);
1058     }
1059     /* CCK parameters */
1060     if (band == RTW89_BAND_2G) {
1061         if (central_ch == 14) {
1062             rtw89_phy_write32_mask(rtwdev, R_PCOEFF0_V1,
1063                            B_PCOEFF01_MSK_V1, 0x3b13ff);
1064             rtw89_phy_write32_mask(rtwdev, R_PCOEFF2_V1,
1065                            B_PCOEFF23_MSK_V1, 0x1c42de);
1066             rtw89_phy_write32_mask(rtwdev, R_PCOEFF4_V1,
1067                            B_PCOEFF45_MSK_V1, 0xfdb0ad);
1068             rtw89_phy_write32_mask(rtwdev, R_PCOEFF6_V1,
1069                            B_PCOEFF67_MSK_V1, 0xf60f6e);
1070             rtw89_phy_write32_mask(rtwdev, R_PCOEFF8_V1,
1071                            B_PCOEFF89_MSK_V1, 0xfd8f92);
1072             rtw89_phy_write32_mask(rtwdev, R_PCOEFFA_V1,
1073                            B_PCOEFFAB_MSK_V1, 0x2d011);
1074             rtw89_phy_write32_mask(rtwdev, R_PCOEFFC_V1,
1075                            B_PCOEFFCD_MSK_V1, 0x1c02c);
1076             rtw89_phy_write32_mask(rtwdev, R_PCOEFFE_V1,
1077                            B_PCOEFFEF_MSK_V1, 0xfff00a);
1078         } else {
1079             rtw89_phy_write32_mask(rtwdev, R_PCOEFF0_V1,
1080                            B_PCOEFF01_MSK_V1, 0x3d23ff);
1081             rtw89_phy_write32_mask(rtwdev, R_PCOEFF2_V1,
1082                            B_PCOEFF23_MSK_V1, 0x29b354);
1083             rtw89_phy_write32_mask(rtwdev, R_PCOEFF4_V1,
1084                            B_PCOEFF45_MSK_V1, 0xfc1c8);
1085             rtw89_phy_write32_mask(rtwdev, R_PCOEFF6_V1,
1086                            B_PCOEFF67_MSK_V1, 0xfdb053);
1087             rtw89_phy_write32_mask(rtwdev, R_PCOEFF8_V1,
1088                            B_PCOEFF89_MSK_V1, 0xf86f9a);
1089             rtw89_phy_write32_mask(rtwdev, R_PCOEFFA_V1,
1090                            B_PCOEFFAB_MSK_V1, 0xfaef92);
1091             rtw89_phy_write32_mask(rtwdev, R_PCOEFFC_V1,
1092                            B_PCOEFFCD_MSK_V1, 0xfe5fcc);
1093             rtw89_phy_write32_mask(rtwdev, R_PCOEFFE_V1,
1094                            B_PCOEFFEF_MSK_V1, 0xffdff5);
1095         }
1096     }
1097
1098     chan_idx = rtw8852c_encode_chan_idx(rtwdev, param->primary_chan, band);
1099     rtw89_phy_write32_idx(rtwdev, R_MAC_PIN_SEL, B_CH_IDX_SEG0, chan_idx, phy_idx);
1100 }
1101
1102 static void rtw8852c_bw_setting(struct rtw89_dev *rtwdev, u8 bw, u8 path)
1103 {
1104     static const u32 adc_sel[2] = {0xC0EC, 0xC1EC};
1105     static const u32 wbadc_sel[2] = {0xC0E4, 0xC1E4};
1106
1107     switch (bw) {
1108     case RTW89_CHANNEL_WIDTH_5:
1109         rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x1);
1110         rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x0);
1111         break;
1112     case RTW89_CHANNEL_WIDTH_10:
1113         rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x2);
1114         rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x1);
1115         break;
1116     case RTW89_CHANNEL_WIDTH_20:
1117     case RTW89_CHANNEL_WIDTH_40:
1118     case RTW89_CHANNEL_WIDTH_80:
1119     case RTW89_CHANNEL_WIDTH_160:
1120         rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0);
1121         rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2);
1122         break;
1123     default:
1124         rtw89_warn(rtwdev, "Fail to set ADC\n");
1125     }
1126 }
1127
1128 static void rtw8852c_edcca_per20_bitmap_sifs(struct rtw89_dev *rtwdev, u8 bw,
1129                          enum rtw89_phy_idx phy_idx)
1130 {
1131     if (bw == RTW89_CHANNEL_WIDTH_20) {
1132         rtw89_phy_write32_idx(rtwdev, R_SNDCCA_A1, B_SNDCCA_A1_EN, 0xff, phy_idx);
1133         rtw89_phy_write32_idx(rtwdev, R_SNDCCA_A2, B_SNDCCA_A2_VAL, 0, phy_idx);
1134     } else {
1135         rtw89_phy_write32_idx(rtwdev, R_SNDCCA_A1, B_SNDCCA_A1_EN, 0, phy_idx);
1136         rtw89_phy_write32_idx(rtwdev, R_SNDCCA_A2, B_SNDCCA_A2_VAL, 0, phy_idx);
1137     }
1138 }
1139
1140 static void
1141 rtw8852c_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_ch, u8 bw,
1142          enum rtw89_phy_idx phy_idx)
1143 {
1144     u8 mod_sbw = 0;
1145
1146     switch (bw) {
1147     case RTW89_CHANNEL_WIDTH_5:
1148     case RTW89_CHANNEL_WIDTH_10:
1149     case RTW89_CHANNEL_WIDTH_20:
1150         if (bw == RTW89_CHANNEL_WIDTH_5)
1151             mod_sbw = 0x1;
1152         else if (bw == RTW89_CHANNEL_WIDTH_10)
1153             mod_sbw = 0x2;
1154         else if (bw == RTW89_CHANNEL_WIDTH_20)
1155             mod_sbw = 0x0;
1156         rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0,
1157                       phy_idx);
1158         rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW,
1159                       mod_sbw, phy_idx);
1160         rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 0x0,
1161                       phy_idx);
1162         rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1,
1163                        B_PATH0_SAMPL_DLY_T_MSK_V1, 0x3);
1164         rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1,
1165                        B_PATH1_SAMPL_DLY_T_MSK_V1, 0x3);
1166         rtw89_phy_write32_mask(rtwdev, R_PATH0_BW_SEL_V1,
1167                        B_PATH0_BW_SEL_MSK_V1, 0xf);
1168         rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1,
1169                        B_PATH1_BW_SEL_MSK_V1, 0xf);
1170         break;
1171     case RTW89_CHANNEL_WIDTH_40:
1172         rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x1,
1173                       phy_idx);
1174         rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0,
1175                       phy_idx);
1176         rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH,
1177                       pri_ch,
1178                       phy_idx);
1179         rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1,
1180                        B_PATH0_SAMPL_DLY_T_MSK_V1, 0x3);
1181         rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1,
1182                        B_PATH1_SAMPL_DLY_T_MSK_V1, 0x3);
1183         rtw89_phy_write32_mask(rtwdev, R_PATH0_BW_SEL_V1,
1184                        B_PATH0_BW_SEL_MSK_V1, 0xf);
1185         rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1,
1186                        B_PATH1_BW_SEL_MSK_V1, 0xf);
1187         break;
1188     case RTW89_CHANNEL_WIDTH_80:
1189         rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x2,
1190                       phy_idx);
1191         rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0,
1192                       phy_idx);
1193         rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH,
1194                       pri_ch,
1195                       phy_idx);
1196         rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1,
1197                        B_PATH0_SAMPL_DLY_T_MSK_V1, 0x2);
1198         rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1,
1199                        B_PATH1_SAMPL_DLY_T_MSK_V1, 0x2);
1200         rtw89_phy_write32_mask(rtwdev, R_PATH0_BW_SEL_V1,
1201                        B_PATH0_BW_SEL_MSK_V1, 0xd);
1202         rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1,
1203                        B_PATH1_BW_SEL_MSK_V1, 0xd);
1204         break;
1205     case RTW89_CHANNEL_WIDTH_160:
1206         rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x3,
1207                       phy_idx);
1208         rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0,
1209                       phy_idx);
1210         rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH,
1211                       pri_ch,
1212                       phy_idx);
1213         rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1,
1214                        B_PATH0_SAMPL_DLY_T_MSK_V1, 0x1);
1215         rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1,
1216                        B_PATH1_SAMPL_DLY_T_MSK_V1, 0x1);
1217         rtw89_phy_write32_mask(rtwdev, R_PATH0_BW_SEL_V1,
1218                        B_PATH0_BW_SEL_MSK_V1, 0xb);
1219         rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1,
1220                        B_PATH1_BW_SEL_MSK_V1, 0xb);
1221         break;
1222     default:
1223         rtw89_warn(rtwdev, "Fail to switch bw (bw:%d, pri ch:%d)\n", bw,
1224                pri_ch);
1225     }
1226
1227     if (bw == RTW89_CHANNEL_WIDTH_40) {
1228         rtw89_phy_write32_idx(rtwdev, R_RX_BW40_2XFFT_EN_V1,
1229                       B_RX_BW40_2XFFT_EN_MSK_V1, 0x1, phy_idx);
1230         rtw89_phy_write32_idx(rtwdev, R_T2F_GI_COMB, B_T2F_GI_COMB_EN, 1, phy_idx);
1231     } else {
1232         rtw89_phy_write32_idx(rtwdev, R_RX_BW40_2XFFT_EN_V1,
1233                       B_RX_BW40_2XFFT_EN_MSK_V1, 0x0, phy_idx);
1234         rtw89_phy_write32_idx(rtwdev, R_T2F_GI_COMB, B_T2F_GI_COMB_EN, 0, phy_idx);
1235     }
1236
1237     if (phy_idx == RTW89_PHY_0) {
1238         rtw8852c_bw_setting(rtwdev, bw, RF_PATH_A);
1239         if (!rtwdev->dbcc_en)
1240             rtw8852c_bw_setting(rtwdev, bw, RF_PATH_B);
1241     } else {
1242         rtw8852c_bw_setting(rtwdev, bw, RF_PATH_B);
1243     }
1244
1245     rtw8852c_edcca_per20_bitmap_sifs(rtwdev, bw, phy_idx);
1246 }
1247
1248 static u32 rtw8852c_spur_freq(struct rtw89_dev *rtwdev,
1249                   struct rtw89_channel_params *param)
1250 {
1251     u8 center_chan = param->center_chan;
1252     u8 bw = param->bandwidth;
1253
1254     switch (param->band_type) {
1255     case RTW89_BAND_2G:
1256         if (bw == RTW89_CHANNEL_WIDTH_20) {
1257             if (center_chan >= 5 && center_chan <= 8)
1258                 return 2440;
1259             if (center_chan == 13)
1260                 return 2480;
1261         } else if (bw == RTW89_CHANNEL_WIDTH_40) {
1262             if (center_chan >= 3 && center_chan <= 10)
1263                 return 2440;
1264         }
1265         break;
1266     case RTW89_BAND_5G:
1267         if (center_chan == 151 || center_chan == 153 ||
1268             center_chan == 155 || center_chan == 163)
1269             return 5760;
1270         break;
1271     case RTW89_BAND_6G:
1272         if (center_chan == 195 || center_chan == 197 ||
1273             center_chan == 199 || center_chan == 207)
1274             return 6920;
1275         break;
1276     default:
1277         break;
1278     }
1279
1280     return 0;
1281 }
1282
1283 #define CARRIER_SPACING_312_5 312500 /* 312.5 kHz */
1284 #define CARRIER_SPACING_78_125 78125 /* 78.125 kHz */
1285 #define MAX_TONE_NUM 2048
1286
1287 static void rtw8852c_set_csi_tone_idx(struct rtw89_dev *rtwdev,
1288                       struct rtw89_channel_params *param,
1289                       enum rtw89_phy_idx phy_idx)
1290 {
1291     u32 spur_freq;
1292     s32 freq_diff, csi_idx, csi_tone_idx;
1293
1294     spur_freq = rtw8852c_spur_freq(rtwdev, param);
1295     if (spur_freq == 0) {
1296         rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 0, phy_idx);
1297         return;
1298     }
1299
1300     freq_diff = (spur_freq - param->center_freq) * 1000000;
1301     csi_idx = s32_div_u32_round_closest(freq_diff, CARRIER_SPACING_78_125);
1302     s32_div_u32_round_down(csi_idx, MAX_TONE_NUM, &csi_tone_idx);
1303
1304     rtw89_phy_write32_idx(rtwdev, R_SEG0CSI, B_SEG0CSI_IDX, csi_tone_idx, phy_idx);
1305     rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 1, phy_idx);
1306 }
1307
1308 static const struct rtw89_nbi_reg_def rtw8852c_nbi_reg_def[] = {
1309     [RF_PATH_A] = {
1310         .notch1_idx = {0x4C14, 0xFF},
1311         .notch1_frac_idx = {0x4C14, 0xC00},
1312         .notch1_en = {0x4C14, 0x1000},
1313         .notch2_idx = {0x4C20, 0xFF},
1314         .notch2_frac_idx = {0x4C20, 0xC00},
1315         .notch2_en = {0x4C20, 0x1000},
1316     },
1317     [RF_PATH_B] = {
1318         .notch1_idx = {0x4CD8, 0xFF},
1319         .notch1_frac_idx = {0x4CD8, 0xC00},
1320         .notch1_en = {0x4CD8, 0x1000},
1321         .notch2_idx = {0x4CE4, 0xFF},
1322         .notch2_frac_idx = {0x4CE4, 0xC00},
1323         .notch2_en = {0x4CE4, 0x1000},
1324     },
1325 };
1326
1327 static void rtw8852c_set_nbi_tone_idx(struct rtw89_dev *rtwdev,
1328                       struct rtw89_channel_params *param,
1329                       enum rtw89_rf_path path)
1330 {
1331     const struct rtw89_nbi_reg_def *nbi = &rtw8852c_nbi_reg_def[path];
1332     u32 spur_freq, fc;
1333     s32 freq_diff;
1334     s32 nbi_idx, nbi_tone_idx;
1335     s32 nbi_frac_idx, nbi_frac_tone_idx;
1336     bool notch2_chk = false;
1337
1338     spur_freq = rtw8852c_spur_freq(rtwdev, param);
1339     if (spur_freq == 0) {
1340         rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 0);
1341         rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 0);
1342         return;
1343     }
1344
1345     fc = param->center_freq;
1346     if (param->bandwidth == RTW89_CHANNEL_WIDTH_160) {
1347         fc = (spur_freq > fc) ? fc + 40 : fc - 40;
1348         if ((fc > spur_freq && param->center_chan < param->primary_chan) ||
1349             (fc < spur_freq && param->center_chan > param->primary_chan))
1350             notch2_chk = true;
1351     }
1352
1353     freq_diff = (spur_freq - fc) * 1000000;
1354     nbi_idx = s32_div_u32_round_down(freq_diff, CARRIER_SPACING_312_5, &nbi_frac_idx);
1355
1356     if (param->bandwidth == RTW89_CHANNEL_WIDTH_20) {
1357         s32_div_u32_round_down(nbi_idx + 32, 64, &nbi_tone_idx);
1358     } else {
1359         u16 tone_para = (param->bandwidth == RTW89_CHANNEL_WIDTH_40) ? 128 : 256;
1360
1361         s32_div_u32_round_down(nbi_idx, tone_para, &nbi_tone_idx);
1362     }
1363     nbi_frac_tone_idx = s32_div_u32_round_closest(nbi_frac_idx, CARRIER_SPACING_78_125);
1364
1365     if (param->bandwidth == RTW89_CHANNEL_WIDTH_160 && notch2_chk) {
1366         rtw89_phy_write32_mask(rtwdev, nbi->notch2_idx.addr,
1367                        nbi->notch2_idx.mask, nbi_tone_idx);
1368         rtw89_phy_write32_mask(rtwdev, nbi->notch2_frac_idx.addr,
1369                        nbi->notch2_frac_idx.mask, nbi_frac_tone_idx);
1370         rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr, nbi->notch2_en.mask, 0);
1371         rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr, nbi->notch2_en.mask, 1);
1372         rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 0);
1373     } else {
1374         rtw89_phy_write32_mask(rtwdev, nbi->notch1_idx.addr,
1375                        nbi->notch1_idx.mask, nbi_tone_idx);
1376         rtw89_phy_write32_mask(rtwdev, nbi->notch1_frac_idx.addr,
1377                        nbi->notch1_frac_idx.mask, nbi_frac_tone_idx);
1378         rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 0);
1379         rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 1);
1380         rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr, nbi->notch2_en.mask, 0);
1381     }
1382 }
1383
1384 static void rtw8852c_spur_notch(struct rtw89_dev *rtwdev, u32 val,
1385                 enum rtw89_phy_idx phy_idx)
1386 {
1387     u32 notch;
1388     u32 notch2;
1389
1390     if (phy_idx == RTW89_PHY_0) {
1391         notch = R_PATH0_NOTCH;
1392         notch2 = R_PATH0_NOTCH2;
1393     } else {
1394         notch = R_PATH1_NOTCH;
1395         notch2 = R_PATH1_NOTCH2;
1396     }
1397
1398     rtw89_phy_write32_mask(rtwdev, notch,
1399                    B_PATH0_NOTCH_VAL | B_PATH0_NOTCH_EN, val);
1400     rtw89_phy_write32_set(rtwdev, notch, B_PATH0_NOTCH_EN);
1401     rtw89_phy_write32_mask(rtwdev, notch2,
1402                    B_PATH0_NOTCH2_VAL | B_PATH0_NOTCH2_EN, val);
1403     rtw89_phy_write32_set(rtwdev, notch2, B_PATH0_NOTCH2_EN);
1404 }
1405
1406 static void rtw8852c_spur_elimination(struct rtw89_dev *rtwdev,
1407                       struct rtw89_channel_params *param,
1408                       u8 pri_ch_idx,
1409                       enum rtw89_phy_idx phy_idx)
1410 {
1411     rtw8852c_set_csi_tone_idx(rtwdev, param, phy_idx);
1412
1413     if (phy_idx == RTW89_PHY_0) {
1414         if (param->bandwidth == RTW89_CHANNEL_WIDTH_160 &&
1415             (pri_ch_idx == RTW89_SC_20_LOWER ||
1416              pri_ch_idx == RTW89_SC_20_UP3X)) {
1417             rtw8852c_spur_notch(rtwdev, 0xe7f, RTW89_PHY_0);
1418             if (!rtwdev->dbcc_en)
1419                 rtw8852c_spur_notch(rtwdev, 0xe7f, RTW89_PHY_1);
1420         } else if (param->bandwidth == RTW89_CHANNEL_WIDTH_160 &&
1421                (pri_ch_idx == RTW89_SC_20_UPPER ||
1422                 pri_ch_idx == RTW89_SC_20_LOW3X)) {
1423             rtw8852c_spur_notch(rtwdev, 0x280, RTW89_PHY_0);
1424             if (!rtwdev->dbcc_en)
1425                 rtw8852c_spur_notch(rtwdev, 0x280, RTW89_PHY_1);
1426         } else {
1427             rtw8852c_set_nbi_tone_idx(rtwdev, param, RF_PATH_A);
1428             if (!rtwdev->dbcc_en)
1429                 rtw8852c_set_nbi_tone_idx(rtwdev, param,
1430                               RF_PATH_B);
1431         }
1432     } else {
1433         if (param->bandwidth == RTW89_CHANNEL_WIDTH_160 &&
1434             (pri_ch_idx == RTW89_SC_20_LOWER ||
1435              pri_ch_idx == RTW89_SC_20_UP3X)) {
1436             rtw8852c_spur_notch(rtwdev, 0xe7f, RTW89_PHY_1);
1437         } else if (param->bandwidth == RTW89_CHANNEL_WIDTH_160 &&
1438                (pri_ch_idx == RTW89_SC_20_UPPER ||
1439                 pri_ch_idx == RTW89_SC_20_LOW3X)) {
1440             rtw8852c_spur_notch(rtwdev, 0x280, RTW89_PHY_1);
1441         } else {
1442             rtw8852c_set_nbi_tone_idx(rtwdev, param, RF_PATH_B);
1443         }
1444     }
1445
1446     if (pri_ch_idx == RTW89_SC_20_UP3X || pri_ch_idx == RTW89_SC_20_LOW3X)
1447         rtw89_phy_write32_idx(rtwdev, R_PD_BOOST_EN, B_PD_BOOST_EN, 0, phy_idx);
1448     else
1449         rtw89_phy_write32_idx(rtwdev, R_PD_BOOST_EN, B_PD_BOOST_EN, 1, phy_idx);
1450 }
1451
1452 static void rtw8852c_5m_mask(struct rtw89_dev *rtwdev,
1453                  struct rtw89_channel_params *param,
1454                  enum rtw89_phy_idx phy_idx)
1455 {
1456     u8 pri_ch = param->primary_chan;
1457     bool mask_5m_low;
1458     bool mask_5m_en;
1459
1460     switch (param->bandwidth) {
1461     case RTW89_CHANNEL_WIDTH_40:
1462         mask_5m_en = true;
1463         mask_5m_low = pri_ch == 2;
1464         break;
1465     case RTW89_CHANNEL_WIDTH_80:
1466         mask_5m_en = ((pri_ch == 3) || (pri_ch == 4));
1467         mask_5m_low = pri_ch == 4;
1468         break;
1469     default:
1470         mask_5m_en = false;
1471         mask_5m_low = false;
1472         break;
1473     }
1474
1475     if (!mask_5m_en) {
1476         rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_EN, 0x0);
1477         rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_EN, 0x0);
1478         rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT,
1479                       B_ASSIGN_SBD_OPT_EN, 0x0, phy_idx);
1480     } else {
1481         if (mask_5m_low) {
1482             rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_TH, 0x4);
1483             rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_EN, 0x1);
1484             rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_SB2, 0x0);
1485             rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_SB0, 0x1);
1486             rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_TH, 0x4);
1487             rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_EN, 0x1);
1488             rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_SB2, 0x0);
1489             rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_SB0, 0x1);
1490         } else {
1491             rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_TH, 0x4);
1492             rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_EN, 0x1);
1493             rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_SB2, 0x1);
1494             rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_SB0, 0x0);
1495             rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_TH, 0x4);
1496             rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_EN, 0x1);
1497             rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_SB2, 0x1);
1498             rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_SB0, 0x0);
1499         }
1500         rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT, B_ASSIGN_SBD_OPT_EN, 0x1, phy_idx);
1501     }
1502 }
1503
1504 static void rtw8852c_bb_reset_all(struct rtw89_dev *rtwdev,
1505                   enum rtw89_phy_idx phy_idx)
1506 {
1507     /*HW SI reset*/
1508     rtw89_phy_write32_mask(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG,
1509                    0x7);
1510     rtw89_phy_write32_mask(rtwdev, R_S1_HW_SI_DIS, B_S1_HW_SI_DIS_W_R_TRIG,
1511                    0x7);
1512
1513     udelay(1);
1514
1515     rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1,
1516                   phy_idx);
1517     rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0,
1518                   phy_idx);
1519     /*HW SI reset*/
1520     rtw89_phy_write32_mask(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG,
1521                    0x0);
1522     rtw89_phy_write32_mask(rtwdev, R_S1_HW_SI_DIS, B_S1_HW_SI_DIS_W_R_TRIG,
1523                    0x0);
1524
1525     rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1,
1526                   phy_idx);
1527 }
1528
1529 static void rtw8852c_bb_reset_en(struct rtw89_dev *rtwdev,
1530                  enum rtw89_phy_idx phy_idx, bool en)
1531 {
1532     struct rtw89_hal *hal = &rtwdev->hal;
1533
1534     if (en) {
1535         rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS,
1536                       B_S0_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx);
1537         rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS,
1538                       B_S1_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx);
1539         rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1,
1540                       phy_idx);
1541         if (hal->current_band_type == RTW89_BAND_2G)
1542             rtw89_phy_write32_mask(rtwdev, R_RXCCA_V1, B_RXCCA_DIS_V1, 0x0);
1543         rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x0);
1544     } else {
1545         rtw89_phy_write32_mask(rtwdev, R_RXCCA_V1, B_RXCCA_DIS_V1, 0x1);
1546         rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x1);
1547         rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS,
1548                       B_S0_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx);
1549         rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS,
1550                       B_S1_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx);
1551         fsleep(1);
1552         rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0,
1553                       phy_idx);
1554     }
1555 }
1556
1557 static void rtw8852c_bb_reset(struct rtw89_dev *rtwdev,
1558                   enum rtw89_phy_idx phy_idx)
1559 {
1560     rtw8852c_bb_reset_all(rtwdev, phy_idx);
1561 }
1562
1563 static
1564 void rtw8852c_bb_gpio_trsw(struct rtw89_dev *rtwdev, enum rtw89_rf_path path,
1565                u8 tx_path_en, u8 trsw_tx,
1566                u8 trsw_rx, u8 trsw, u8 trsw_b)
1567 {
1568     static const u32 path_cr_bases[] = {0x5868, 0x7868};
1569     u32 mask_ofst = 16;
1570     u32 cr;
1571     u32 val;
1572
1573     if (path >= ARRAY_SIZE(path_cr_bases))
1574         return;
1575
1576     cr = path_cr_bases[path];
1577
1578     mask_ofst += (tx_path_en * 4 + trsw_tx * 2 + trsw_rx) * 2;
1579     val = FIELD_PREP(B_P0_TRSW_A, trsw) | FIELD_PREP(B_P0_TRSW_B, trsw_b);
1580
1581     rtw89_phy_write32_mask(rtwdev, cr, (B_P0_TRSW_A | B_P0_TRSW_B) << mask_ofst, val);
1582 }
1583
1584 enum rtw8852c_rfe_src {
1585     PAPE_RFM,
1586     TRSW_RFM,
1587     LNAON_RFM,
1588 };
1589
1590 static
1591 void rtw8852c_bb_gpio_rfm(struct rtw89_dev *rtwdev, enum rtw89_rf_path path,
1592               enum rtw8852c_rfe_src src, u8 dis_tx_gnt_wl,
1593               u8 active_tx_opt, u8 act_bt_en, u8 rfm_output_val)
1594 {
1595     static const u32 path_cr_bases[] = {0x5894, 0x7894};
1596     static const u32 masks[] = {0, 8, 16};
1597     u32 mask, mask_ofst;
1598     u32 cr;
1599     u32 val;
1600
1601     if (src >= ARRAY_SIZE(masks) || path >= ARRAY_SIZE(path_cr_bases))
1602         return;
1603
1604     mask_ofst = masks[src];
1605     cr = path_cr_bases[path];
1606
1607     val = FIELD_PREP(B_P0_RFM_DIS_WL, dis_tx_gnt_wl) |
1608           FIELD_PREP(B_P0_RFM_TX_OPT, active_tx_opt) |
1609           FIELD_PREP(B_P0_RFM_BT_EN, act_bt_en) |
1610           FIELD_PREP(B_P0_RFM_OUT, rfm_output_val);
1611     mask = 0xff << mask_ofst;
1612
1613     rtw89_phy_write32_mask(rtwdev, cr, mask, val);
1614 }
1615
1616 static void rtw8852c_bb_gpio_init(struct rtw89_dev *rtwdev)
1617 {
1618     static const u32 cr_bases[] = {0x5800, 0x7800};
1619     u32 addr;
1620     u8 i;
1621
1622     for (i = 0; i < ARRAY_SIZE(cr_bases); i++) {
1623         addr = cr_bases[i];
1624         rtw89_phy_write32_set(rtwdev, (addr | 0x68), B_P0_TRSW_A);
1625         rtw89_phy_write32_clr(rtwdev, (addr | 0x68), B_P0_TRSW_X);
1626         rtw89_phy_write32_clr(rtwdev, (addr | 0x68), B_P0_TRSW_SO_A2);
1627         rtw89_phy_write32(rtwdev, (addr | 0x80), 0x77777777);
1628         rtw89_phy_write32(rtwdev, (addr | 0x84), 0x77777777);
1629     }
1630
1631     rtw89_phy_write32(rtwdev, R_RFE_E_A2, 0xffffffff);
1632     rtw89_phy_write32(rtwdev, R_RFE_O_SEL_A2, 0);
1633     rtw89_phy_write32(rtwdev, R_RFE_SEL0_A2, 0);
1634     rtw89_phy_write32(rtwdev, R_RFE_SEL32_A2, 0);
1635
1636     rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 0, 0, 0, 1);
1637     rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 0, 1, 1, 0);
1638     rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 1, 0, 1, 0);
1639     rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 1, 1, 1, 0);
1640     rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 0, 0, 0, 1);
1641     rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 0, 1, 1, 0);
1642     rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 1, 0, 1, 0);
1643     rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 1, 1, 1, 0);
1644
1645     rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 0, 0, 0, 0, 1);
1646     rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 0, 0, 1, 1, 0);
1647     rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 0, 1, 0, 1, 0);
1648     rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 0, 1, 1, 1, 0);
1649     rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 1, 0, 0, 0, 1);
1650     rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 1, 0, 1, 1, 0);
1651     rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 1, 1, 0, 1, 0);
1652     rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 1, 1, 1, 1, 0);
1653
1654     rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_A, PAPE_RFM, 0, 0, 0, 0x0);
1655     rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_A, TRSW_RFM, 0, 0, 0, 0x4);
1656     rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_A, LNAON_RFM, 0, 0, 0, 0x8);
1657
1658     rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_B, PAPE_RFM, 0, 0, 0, 0x0);
1659     rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_B, TRSW_RFM, 0, 0, 0, 0x4);
1660     rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_B, LNAON_RFM, 0, 0, 0, 0x8);
1661 }
1662
1663 static void rtw8852c_bb_macid_ctrl_init(struct rtw89_dev *rtwdev,
1664                     enum rtw89_phy_idx phy_idx)
1665 {
1666     u32 addr;
1667
1668     for (addr = R_AX_PWR_MACID_LMT_TABLE0;
1669          addr <= R_AX_PWR_MACID_LMT_TABLE127; addr += 4)
1670         rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0);
1671 }
1672
1673 static void rtw8852c_bb_sethw(struct rtw89_dev *rtwdev)
1674 {
1675     struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
1676
1677     rtw89_phy_write32_set(rtwdev, R_DBCC_80P80_SEL_EVM_RPT,
1678                   B_DBCC_80P80_SEL_EVM_RPT_EN);
1679     rtw89_phy_write32_set(rtwdev, R_DBCC_80P80_SEL_EVM_RPT2,
1680                   B_DBCC_80P80_SEL_EVM_RPT2_EN);
1681
1682     rtw8852c_bb_macid_ctrl_init(rtwdev, RTW89_PHY_0);
1683     rtw8852c_bb_gpio_init(rtwdev);
1684
1685     /* read these registers after loading BB parameters */
1686     gain->offset_base[RTW89_PHY_0] =
1687         rtw89_phy_read32_mask(rtwdev, R_RPL_BIAS_COMP, B_RPL_BIAS_COMP_MASK);
1688     gain->offset_base[RTW89_PHY_1] =
1689         rtw89_phy_read32_mask(rtwdev, R_RPL_BIAS_COMP1, B_RPL_BIAS_COMP1_MASK);
1690 }
1691
1692 static void rtw8852c_set_channel_bb(struct rtw89_dev *rtwdev,
1693                     struct rtw89_channel_params *param,
1694                     enum rtw89_phy_idx phy_idx)
1695 {
1696     bool cck_en = param->band_type == RTW89_BAND_2G;
1697     u8 pri_ch_idx = param->pri_ch_idx;
1698     u32 mask, reg;
1699     u32 ru_alloc_msk[2] = {B_P80_AT_HIGH_FREQ_RU_ALLOC_PHY0,
1700                    B_P80_AT_HIGH_FREQ_RU_ALLOC_PHY1};
1701
1702     if (param->band_type == RTW89_BAND_2G)
1703         rtw8852c_ctrl_sco_cck(rtwdev, param->center_chan,
1704                       param->primary_chan, param->bandwidth);
1705
1706     rtw8852c_ctrl_ch(rtwdev, param, phy_idx);
1707     rtw8852c_ctrl_bw(rtwdev, pri_ch_idx, param->bandwidth, phy_idx);
1708     if (cck_en) {
1709         rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 1);
1710         rtw89_phy_write32_mask(rtwdev, R_RXCCA_V1, B_RXCCA_DIS_V1, 0);
1711         rtw89_phy_write32_idx(rtwdev, R_PD_ARBITER_OFF,
1712                       B_PD_ARBITER_OFF, 0x0, phy_idx);
1713     } else {
1714         rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 0);
1715         rtw89_phy_write32_mask(rtwdev, R_RXCCA_V1, B_RXCCA_DIS_V1, 1);
1716         rtw89_phy_write32_idx(rtwdev, R_PD_ARBITER_OFF,
1717                       B_PD_ARBITER_OFF, 0x1, phy_idx);
1718     }
1719
1720     rtw8852c_spur_elimination(rtwdev, param, pri_ch_idx, phy_idx);
1721     rtw8852c_ctrl_btg(rtwdev, param->band_type == RTW89_BAND_2G);
1722     rtw8852c_5m_mask(rtwdev, param, phy_idx);
1723
1724     if (param->bandwidth == RTW89_CHANNEL_WIDTH_160 &&
1725         rtwdev->hal.cv != CHIP_CAV) {
1726         rtw89_phy_write32_idx(rtwdev, R_P80_AT_HIGH_FREQ,
1727                       B_P80_AT_HIGH_FREQ, 0x0, phy_idx);
1728         reg = rtw89_mac_reg_by_idx(R_P80_AT_HIGH_FREQ_BB_WRP,
1729                        phy_idx);
1730         if (param->primary_chan > param->center_chan) {
1731             rtw89_phy_write32_mask(rtwdev,
1732                            R_P80_AT_HIGH_FREQ_RU_ALLOC,
1733                            ru_alloc_msk[phy_idx], 1);
1734             rtw89_write32_mask(rtwdev, reg,
1735                        B_P80_AT_HIGH_FREQ_BB_WRP, 1);
1736         } else {
1737             rtw89_phy_write32_mask(rtwdev,
1738                            R_P80_AT_HIGH_FREQ_RU_ALLOC,
1739                            ru_alloc_msk[phy_idx], 0);
1740             rtw89_write32_mask(rtwdev, reg,
1741                        B_P80_AT_HIGH_FREQ_BB_WRP, 0);
1742         }
1743     }
1744
1745     if (param->band_type == RTW89_BAND_6G &&
1746         param->bandwidth == RTW89_CHANNEL_WIDTH_160)
1747         rtw89_phy_write32_idx(rtwdev, R_CDD_EVM_CHK_EN,
1748                       B_CDD_EVM_CHK_EN, 0, phy_idx);
1749     else
1750         rtw89_phy_write32_idx(rtwdev, R_CDD_EVM_CHK_EN,
1751                       B_CDD_EVM_CHK_EN, 1, phy_idx);
1752
1753     if (!rtwdev->dbcc_en) {
1754         mask = B_P0_TXPW_RSTB_TSSI | B_P0_TXPW_RSTB_MANON;
1755         rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask, 0x1);
1756         rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask, 0x3);
1757         mask = B_P1_TXPW_RSTB_TSSI | B_P1_TXPW_RSTB_MANON;
1758         rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask, 0x1);
1759         rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask, 0x3);
1760     } else {
1761         if (phy_idx == RTW89_PHY_0) {
1762             mask = B_P0_TXPW_RSTB_TSSI | B_P0_TXPW_RSTB_MANON;
1763             rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask, 0x1);
1764             rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask, 0x3);
1765         } else {
1766             mask = B_P1_TXPW_RSTB_TSSI | B_P1_TXPW_RSTB_MANON;
1767             rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask, 0x1);
1768             rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask, 0x3);
1769         }
1770     }
1771
1772     rtw8852c_bb_reset_all(rtwdev, phy_idx);
1773 }
1774
1775 static void rtw8852c_set_channel(struct rtw89_dev *rtwdev,
1776                  struct rtw89_channel_params *params)
1777 {
1778     rtw8852c_set_channel_mac(rtwdev, params, RTW89_MAC_0);
1779     rtw8852c_set_channel_bb(rtwdev, params, RTW89_PHY_0);
1780     rtw8852c_set_channel_rf(rtwdev, params, RTW89_PHY_0);
1781 }
1782
1783 static void rtw8852c_dfs_en(struct rtw89_dev *rtwdev, bool en)
1784 {
1785     if (en)
1786         rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 1);
1787     else
1788         rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 0);
1789 }
1790
1791 static void rtw8852c_adc_en(struct rtw89_dev *rtwdev, bool en)
1792 {
1793     if (en)
1794         rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST,
1795                        0x0);
1796     else
1797         rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST,
1798                        0xf);
1799 }
1800
1801 static void rtw8852c_set_channel_help(struct rtw89_dev *rtwdev, bool enter,
1802                       struct rtw89_channel_help_params *p)
1803 {
1804     u8 phy_idx = RTW89_PHY_0;
1805
1806     if (enter) {
1807         rtw89_chip_stop_sch_tx(rtwdev, RTW89_MAC_0, &p->tx_en, RTW89_SCH_TX_SEL_ALL);
1808         rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, false);
1809         rtw8852c_dfs_en(rtwdev, false);
1810         rtw8852c_tssi_cont_en_phyidx(rtwdev, false, RTW89_PHY_0);
1811         rtw8852c_adc_en(rtwdev, false);
1812         fsleep(40);
1813         rtw8852c_bb_reset_en(rtwdev, phy_idx, false);
1814     } else {
1815         rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true);
1816         rtw8852c_adc_en(rtwdev, true);
1817         rtw8852c_dfs_en(rtwdev, true);
1818         rtw8852c_tssi_cont_en_phyidx(rtwdev, true, RTW89_PHY_0);
1819         rtw8852c_bb_reset_en(rtwdev, phy_idx, true);
1820         rtw89_chip_resume_sch_tx(rtwdev, RTW89_MAC_0, p->tx_en);
1821     }
1822 }
1823
1824 static void rtw8852c_rfk_init(struct rtw89_dev *rtwdev)
1825 {
1826     struct rtw89_mcc_info *mcc_info = &rtwdev->mcc;
1827
1828     rtwdev->is_tssi_mode[RF_PATH_A] = false;
1829     rtwdev->is_tssi_mode[RF_PATH_B] = false;
1830     memset(mcc_info, 0, sizeof(*mcc_info));
1831     rtw8852c_lck_init(rtwdev);
1832
1833     rtw8852c_rck(rtwdev);
1834     rtw8852c_dack(rtwdev);
1835     rtw8852c_rx_dck(rtwdev, RTW89_PHY_0, false);
1836 }
1837
1838 static void rtw8852c_rfk_channel(struct rtw89_dev *rtwdev)
1839 {
1840     enum rtw89_phy_idx phy_idx = RTW89_PHY_0;
1841
1842     rtw8852c_mcc_get_ch_info(rtwdev, phy_idx);
1843     rtw8852c_rx_dck(rtwdev, phy_idx, false);
1844     rtw8852c_iqk(rtwdev, phy_idx);
1845     rtw8852c_tssi(rtwdev, phy_idx);
1846     rtw8852c_dpk(rtwdev, phy_idx);
1847     rtw89_fw_h2c_rf_ntfy_mcc(rtwdev);
1848 }
1849
1850 static void rtw8852c_rfk_band_changed(struct rtw89_dev *rtwdev)
1851 {
1852     rtw8852c_tssi_scan(rtwdev, RTW89_PHY_0);
1853 }
1854
1855 static void rtw8852c_rfk_scan(struct rtw89_dev *rtwdev, bool start)
1856 {
1857     rtw8852c_wifi_scan_notify(rtwdev, start, RTW89_PHY_0);
1858 }
1859
1860 static void rtw8852c_rfk_track(struct rtw89_dev *rtwdev)
1861 {
1862     rtw8852c_dpk_track(rtwdev);
1863     rtw8852c_lck_track(rtwdev);
1864     rtw8852c_rx_dck_track(rtwdev);
1865 }
1866
1867 static u32 rtw8852c_bb_cal_txpwr_ref(struct rtw89_dev *rtwdev,
1868                      enum rtw89_phy_idx phy_idx, s16 ref)
1869 {
1870     s8 ofst_int = 0;
1871     u8 base_cw_0db = 0x27;
1872     u16 tssi_16dbm_cw = 0x12c;
1873     s16 pwr_s10_3 = 0;
1874     s16 rf_pwr_cw = 0;
1875     u16 bb_pwr_cw = 0;
1876     u32 pwr_cw = 0;
1877     u32 tssi_ofst_cw = 0;
1878
1879     pwr_s10_3 = (ref << 1) + (s16)(ofst_int) + (s16)(base_cw_0db << 3);
1880     bb_pwr_cw = FIELD_GET(GENMASK(2, 0), pwr_s10_3);
1881     rf_pwr_cw = FIELD_GET(GENMASK(8, 3), pwr_s10_3);
1882     rf_pwr_cw = clamp_t(s16, rf_pwr_cw, 15, 63);
1883     pwr_cw = (rf_pwr_cw << 3) | bb_pwr_cw;
1884
1885     tssi_ofst_cw = (u32)((s16)tssi_16dbm_cw + (ref << 1) - (16 << 3));
1886     rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
1887             "[TXPWR] tssi_ofst_cw=%d rf_cw=0x%x bb_cw=0x%x\n",
1888             tssi_ofst_cw, rf_pwr_cw, bb_pwr_cw);
1889
1890     return (tssi_ofst_cw << 18) | (pwr_cw << 9) | (ref & GENMASK(8, 0));
1891 }
1892
1893 static
1894 void rtw8852c_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev,
1895                      s8 pw_ofst, enum rtw89_mac_idx mac_idx)
1896 {
1897     s8 pw_ofst_2tx;
1898     s8 val_1t;
1899     s8 val_2t;
1900     u32 reg;
1901     u8 i;
1902
1903     if (pw_ofst < -32 || pw_ofst > 31) {
1904         rtw89_warn(rtwdev, "[ULTB] Err pwr_offset=%d\n", pw_ofst);
1905         return;
1906     }
1907     val_1t = pw_ofst << 2;
1908     pw_ofst_2tx = max(pw_ofst - 3, -32);
1909     val_2t = pw_ofst_2tx << 2;
1910
1911     rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] val_1tx=0x%x\n", val_1t);
1912     rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] val_2tx=0x%x\n", val_2t);
1913
1914     for (i = 0; i < 4; i++) {
1915         /* 1TX */
1916         reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_1T, mac_idx);
1917         rtw89_write32_mask(rtwdev, reg,
1918                    B_AX_PWR_UL_TB_1T_V1_MASK << (8 * i),
1919                    val_1t);
1920         /* 2TX */
1921         reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_2T, mac_idx);
1922         rtw89_write32_mask(rtwdev, reg,
1923                    B_AX_PWR_UL_TB_2T_V1_MASK << (8 * i),
1924                    val_2t);
1925     }
1926 }
1927
1928 static void rtw8852c_set_txpwr_ref(struct rtw89_dev *rtwdev,
1929                    enum rtw89_phy_idx phy_idx)
1930 {
1931     static const u32 addr[RF_PATH_NUM_8852C] = {0x5800, 0x7800};
1932     const u32 mask = 0x7FFFFFF;
1933     const u8 ofst_ofdm = 0x4;
1934     const u8 ofst_cck = 0x8;
1935     s16 ref_ofdm = 0;
1936     s16 ref_cck = 0;
1937     u32 val;
1938     u8 i;
1939
1940     rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr reference\n");
1941
1942     rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_CTRL,
1943                      GENMASK(27, 10), 0x0);
1944
1945     rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb ofdm txpwr ref\n");
1946     val = rtw8852c_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_ofdm);
1947
1948     for (i = 0; i < RF_PATH_NUM_8852C; i++)
1949         rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_ofdm, mask, val,
1950                       phy_idx);
1951
1952     rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb cck txpwr ref\n");
1953     val = rtw8852c_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_cck);
1954
1955     for (i = 0; i < RF_PATH_NUM_8852C; i++)
1956         rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_cck, mask, val,
1957                       phy_idx);
1958 }
1959
1960 static void rtw8852c_set_txpwr_byrate(struct rtw89_dev *rtwdev,
1961                       enum rtw89_phy_idx phy_idx)
1962 {
1963     u8 ch = rtwdev->hal.current_channel;
1964     static const u8 rs[] = {
1965         RTW89_RS_CCK,
1966         RTW89_RS_OFDM,
1967         RTW89_RS_MCS,
1968         RTW89_RS_HEDCM,
1969     };
1970     s8 tmp;
1971     u8 i, j;
1972     u32 val, shf, addr = R_AX_PWR_BY_RATE;
1973     struct rtw89_rate_desc cur;
1974
1975     rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
1976             "[TXPWR] set txpwr byrate with ch=%d\n", ch);
1977
1978     for (cur.nss = 0; cur.nss <= RTW89_NSS_2; cur.nss++) {
1979         for (i = 0; i < ARRAY_SIZE(rs); i++) {
1980             if (cur.nss >= rtw89_rs_nss_max[rs[i]])
1981                 continue;
1982
1983             val = 0;
1984             cur.rs = rs[i];
1985
1986             for (j = 0; j < rtw89_rs_idx_max[rs[i]]; j++) {
1987                 cur.idx = j;
1988                 shf = (j % 4) * 8;
1989                 tmp = rtw89_phy_read_txpwr_byrate(rtwdev, &cur);
1990                 val |= (tmp << shf);
1991
1992                 if ((j + 1) % 4)
1993                     continue;
1994
1995                 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val);
1996                 val = 0;
1997                 addr += 4;
1998             }
1999         }
2000     }
2001 }
2002
2003 static void rtw8852c_set_txpwr_offset(struct rtw89_dev *rtwdev,
2004                       enum rtw89_phy_idx phy_idx)
2005 {
2006     struct rtw89_rate_desc desc = {
2007         .nss = RTW89_NSS_1,
2008         .rs = RTW89_RS_OFFSET,
2009     };
2010     u32 val = 0;
2011     s8 v;
2012
2013     rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr offset\n");
2014
2015     for (desc.idx = 0; desc.idx < RTW89_RATE_OFFSET_MAX; desc.idx++) {
2016         v = rtw89_phy_read_txpwr_byrate(rtwdev, &desc);
2017         val |= ((v & 0xf) << (4 * desc.idx));
2018     }
2019
2020     rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_OFST_CTRL,
2021                      GENMASK(19, 0), val);
2022 }
2023
2024 static void rtw8852c_bb_set_tx_shape_dfir(struct rtw89_dev *rtwdev,
2025                       u8 tx_shape_idx,
2026                       enum rtw89_phy_idx phy_idx)
2027 {
2028 #define __DFIR_CFG_MASK 0xffffff
2029 #define __DFIR_CFG_NR 8
2030 #define __DECL_DFIR_VAR(_prefix, _name, _val...) \
2031     static const u32 _prefix ## _ ## _name[] = {_val}; \
2032     static_assert(ARRAY_SIZE(_prefix ## _ ## _name) == __DFIR_CFG_NR)
2033 #define __DECL_DFIR_PARAM(_name, _val...) __DECL_DFIR_VAR(param, _name, _val)
2034 #define __DECL_DFIR_ADDR(_name, _val...) __DECL_DFIR_VAR(addr, _name, _val)
2035
2036     __DECL_DFIR_PARAM(flat,
2037               0x003D23FF, 0x0029B354, 0x000FC1C8, 0x00FDB053,
2038               0x00F86F9A, 0x00FAEF92, 0x00FE5FCC, 0x00FFDFF5);
2039     __DECL_DFIR_PARAM(sharp,
2040               0x003D83FF, 0x002C636A, 0x0013F204, 0x00008090,
2041               0x00F87FB0, 0x00F99F83, 0x00FDBFBA, 0x00003FF5);
2042     __DECL_DFIR_PARAM(sharp_14,
2043               0x003B13FF, 0x001C42DE, 0x00FDB0AD, 0x00F60F6E,
2044               0x00FD8F92, 0x0002D011, 0x0001C02C, 0x00FFF00A);
2045     __DECL_DFIR_ADDR(filter,
2046              0x45BC, 0x45CC, 0x45D0, 0x45D4, 0x45D8, 0x45C0,
2047              0x45C4, 0x45C8);
2048     u8 ch = rtwdev->hal.current_channel;
2049     const u32 *param;
2050     int i;
2051
2052     if (ch > 14) {
2053         rtw89_warn(rtwdev,
2054                "set tx shape dfir by unknown ch: %d on 2G\n", ch);
2055         return;
2056     }
2057
2058     if (ch == 14)
2059         param = param_sharp_14;
2060     else
2061         param = tx_shape_idx == 0 ? param_flat : param_sharp;
2062
2063     for (i = 0; i < __DFIR_CFG_NR; i++) {
2064         rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
2065                 "set tx shape dfir: 0x%x: 0x%x\n", addr_filter[i],
2066                 param[i]);
2067         rtw89_phy_write32_idx(rtwdev, addr_filter[i], __DFIR_CFG_MASK,
2068                       param[i], phy_idx);
2069     }
2070
2071 #undef __DECL_DFIR_ADDR
2072 #undef __DECL_DFIR_PARAM
2073 #undef __DECL_DFIR_VAR
2074 #undef __DFIR_CFG_NR
2075 #undef __DFIR_CFG_MASK
2076 }
2077
2078 static void rtw8852c_set_tx_shape(struct rtw89_dev *rtwdev,
2079                   enum rtw89_phy_idx phy_idx)
2080 {
2081     u8 band = rtwdev->hal.current_band_type;
2082     u8 regd = rtw89_regd_get(rtwdev, band);
2083     u8 tx_shape_cck = rtw89_8852c_tx_shape[band][RTW89_RS_CCK][regd];
2084     u8 tx_shape_ofdm = rtw89_8852c_tx_shape[band][RTW89_RS_OFDM][regd];
2085
2086     if (band == RTW89_BAND_2G)
2087         rtw8852c_bb_set_tx_shape_dfir(rtwdev, tx_shape_cck, phy_idx);
2088
2089     rtw89_phy_tssi_ctrl_set_bandedge_cfg(rtwdev,
2090                          (enum rtw89_mac_idx)phy_idx,
2091                          tx_shape_ofdm);
2092 }
2093
2094 static void rtw8852c_set_txpwr_limit(struct rtw89_dev *rtwdev,
2095                      enum rtw89_phy_idx phy_idx)
2096 {
2097 #define __MAC_TXPWR_LMT_PAGE_SIZE 40
2098     u8 ch = rtwdev->hal.current_channel;
2099     u8 bw = rtwdev->hal.current_band_width;
2100     struct rtw89_txpwr_limit lmt[NTX_NUM_8852C];
2101     u32 addr, val;
2102     const s8 *ptr;
2103     u8 i, j, k;
2104
2105     rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
2106             "[TXPWR] set txpwr limit with ch=%d bw=%d\n", ch, bw);
2107
2108     for (i = 0; i < NTX_NUM_8852C; i++) {
2109         rtw89_phy_fill_txpwr_limit(rtwdev, &lmt[i], i);
2110
2111         for (j = 0; j < __MAC_TXPWR_LMT_PAGE_SIZE; j += 4) {
2112             addr = R_AX_PWR_LMT + j + __MAC_TXPWR_LMT_PAGE_SIZE * i;
2113             ptr = (s8 *)&lmt[i] + j;
2114             val = 0;
2115
2116             for (k = 0; k < 4; k++)
2117                 val |= (ptr[k] << (8 * k));
2118
2119             rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val);
2120         }
2121     }
2122 #undef __MAC_TXPWR_LMT_PAGE_SIZE
2123 }
2124
2125 static void rtw8852c_set_txpwr_limit_ru(struct rtw89_dev *rtwdev,
2126                     enum rtw89_phy_idx phy_idx)
2127 {
2128 #define __MAC_TXPWR_LMT_RU_PAGE_SIZE 24
2129     u8 ch = rtwdev->hal.current_channel;
2130     u8 bw = rtwdev->hal.current_band_width;
2131     struct rtw89_txpwr_limit_ru lmt_ru[NTX_NUM_8852C];
2132     u32 addr, val;
2133     const s8 *ptr;
2134     u8 i, j, k;
2135
2136     rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
2137             "[TXPWR] set txpwr limit ru with ch=%d bw=%d\n", ch, bw);
2138
2139     for (i = 0; i < NTX_NUM_8852C; i++) {
2140         rtw89_phy_fill_txpwr_limit_ru(rtwdev, &lmt_ru[i], i);
2141
2142         for (j = 0; j < __MAC_TXPWR_LMT_RU_PAGE_SIZE; j += 4) {
2143             addr = R_AX_PWR_RU_LMT + j +
2144                    __MAC_TXPWR_LMT_RU_PAGE_SIZE * i;
2145             ptr = (s8 *)&lmt_ru[i] + j;
2146             val = 0;
2147
2148             for (k = 0; k < 4; k++)
2149                 val |= (ptr[k] << (8 * k));
2150
2151             rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val);
2152         }
2153     }
2154
2155 #undef __MAC_TXPWR_LMT_RU_PAGE_SIZE
2156 }
2157
2158 static void rtw8852c_set_txpwr(struct rtw89_dev *rtwdev)
2159 {
2160     rtw8852c_set_txpwr_byrate(rtwdev, RTW89_PHY_0);
2161     rtw8852c_set_txpwr_offset(rtwdev, RTW89_PHY_0);
2162     rtw8852c_set_tx_shape(rtwdev, RTW89_PHY_0);
2163     rtw8852c_set_txpwr_limit(rtwdev, RTW89_PHY_0);
2164     rtw8852c_set_txpwr_limit_ru(rtwdev, RTW89_PHY_0);
2165 }
2166
2167 static void rtw8852c_set_txpwr_ctrl(struct rtw89_dev *rtwdev)
2168 {
2169     rtw8852c_set_txpwr_ref(rtwdev, RTW89_PHY_0);
2170 }
2171
2172 static void
2173 rtw8852c_init_tssi_ctrl(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
2174 {
2175     static const struct rtw89_reg2_def ctrl_ini[] = {
2176         {0xD938, 0x00010100},
2177         {0xD93C, 0x0500D500},
2178         {0xD940, 0x00000500},
2179         {0xD944, 0x00000005},
2180         {0xD94C, 0x00220000},
2181         {0xD950, 0x00030000},
2182     };
2183     u32 addr;
2184     int i;
2185
2186     for (addr = R_AX_TSSI_CTRL_HEAD; addr <= R_AX_TSSI_CTRL_TAIL; addr += 4)
2187         rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0);
2188
2189     for (i = 0; i < ARRAY_SIZE(ctrl_ini); i++)
2190         rtw89_mac_txpwr_write32(rtwdev, phy_idx, ctrl_ini[i].addr,
2191                     ctrl_ini[i].data);
2192
2193     rtw89_phy_tssi_ctrl_set_bandedge_cfg(rtwdev,
2194                          (enum rtw89_mac_idx)phy_idx,
2195                          RTW89_TSSI_BANDEDGE_FLAT);
2196 }
2197
2198 static int
2199 rtw8852c_init_txpwr_unit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
2200 {
2201     int ret;
2202
2203     ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL2, 0x07763333);
2204     if (ret)
2205         return ret;
2206
2207     ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_COEXT_CTRL, 0x01ebf000);
2208     if (ret)
2209         return ret;
2210
2211     ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL0, 0x0002f8ff);
2212     if (ret)
2213         return ret;
2214
2215     rtw8852c_set_txpwr_ul_tb_offset(rtwdev, 0, phy_idx == RTW89_PHY_1 ?
2216                                   RTW89_MAC_1 :
2217                                   RTW89_MAC_0);
2218     rtw8852c_init_tssi_ctrl(rtwdev, phy_idx);
2219
2220     return 0;
2221 }
2222
2223 static void rtw8852c_bb_cfg_rx_path(struct rtw89_dev *rtwdev, u8 rx_path)
2224 {
2225     struct rtw89_hal *hal = &rtwdev->hal;
2226     u32 rst_mask0 = B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI;
2227     u32 rst_mask1 = B_P1_TXPW_RSTB_MANON | B_P1_TXPW_RSTB_TSSI;
2228
2229     if (rtwdev->dbcc_en) {
2230         rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, B_ANT_RX_SEG0, 1);
2231         rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_ANT_RX_SEG0, 2,
2232                       RTW89_PHY_1);
2233
2234         rtw89_phy_write32_mask(rtwdev, R_FC0_BW, B_ANT_RX_1RCCA_SEG0,
2235                        1);
2236         rtw89_phy_write32_mask(rtwdev, R_FC0_BW, B_ANT_RX_1RCCA_SEG1,
2237                        1);
2238         rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_ANT_RX_1RCCA_SEG0, 2,
2239                       RTW89_PHY_1);
2240         rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_ANT_RX_1RCCA_SEG1, 2,
2241                       RTW89_PHY_1);
2242
2243         rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT,
2244                        B_RXHT_MCS_LIMIT, 0);
2245         rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT,
2246                        B_RXVHT_MCS_LIMIT, 0);
2247         rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 8);
2248         rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0);
2249         rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0);
2250
2251         rtw89_phy_write32_idx(rtwdev, R_RXHT_MCS_LIMIT,
2252                       B_RXHT_MCS_LIMIT, 0, RTW89_PHY_1);
2253         rtw89_phy_write32_idx(rtwdev, R_RXVHT_MCS_LIMIT,
2254                       B_RXVHT_MCS_LIMIT, 0, RTW89_PHY_1);
2255         rtw89_phy_write32_idx(rtwdev, R_RXHE, B_RXHE_USER_MAX, 1,
2256                       RTW89_PHY_1);
2257         rtw89_phy_write32_idx(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0,
2258                       RTW89_PHY_1);
2259         rtw89_phy_write32_idx(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0,
2260                       RTW89_PHY_1);
2261         rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 1);
2262         rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 3);
2263         rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 1);
2264         rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 3);
2265     } else {
2266         if (rx_path == RF_PATH_A) {
2267             rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD,
2268                            B_ANT_RX_SEG0, 1);
2269             rtw89_phy_write32_mask(rtwdev, R_FC0_BW,
2270                            B_ANT_RX_1RCCA_SEG0, 1);
2271             rtw89_phy_write32_mask(rtwdev, R_FC0_BW,
2272                            B_ANT_RX_1RCCA_SEG1, 1);
2273             rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT,
2274                            B_RXHT_MCS_LIMIT, 0);
2275             rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT,
2276                            B_RXVHT_MCS_LIMIT, 0);
2277             rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS,
2278                            0);
2279             rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS,
2280                            0);
2281             rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB,
2282                            rst_mask0, 1);
2283             rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB,
2284                            rst_mask0, 3);
2285         } else if (rx_path == RF_PATH_B) {
2286             rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD,
2287                            B_ANT_RX_SEG0, 2);
2288             rtw89_phy_write32_mask(rtwdev, R_FC0_BW,
2289                            B_ANT_RX_1RCCA_SEG0, 2);
2290             rtw89_phy_write32_mask(rtwdev, R_FC0_BW,
2291                            B_ANT_RX_1RCCA_SEG1, 2);
2292             rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT,
2293                            B_RXHT_MCS_LIMIT, 0);
2294             rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT,
2295                            B_RXVHT_MCS_LIMIT, 0);
2296             rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS,
2297                            0);
2298             rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS,
2299                            0);
2300             rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB,
2301                            rst_mask1, 1);
2302             rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB,
2303                            rst_mask1, 3);
2304         } else {
2305             rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD,
2306                            B_ANT_RX_SEG0, 3);
2307             rtw89_phy_write32_mask(rtwdev, R_FC0_BW,
2308                            B_ANT_RX_1RCCA_SEG0, 3);
2309             rtw89_phy_write32_mask(rtwdev, R_FC0_BW,
2310                            B_ANT_RX_1RCCA_SEG1, 3);
2311             rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT,
2312                            B_RXHT_MCS_LIMIT, 1);
2313             rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT,
2314                            B_RXVHT_MCS_LIMIT, 1);
2315             rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS,
2316                            1);
2317             rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS,
2318                            1);
2319             rtw8852c_ctrl_btg(rtwdev, hal->current_band_type == RTW89_BAND_2G);
2320             rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB,
2321                            rst_mask0, 1);
2322             rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB,
2323                            rst_mask0, 3);
2324             rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB,
2325                            rst_mask1, 1);
2326             rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB,
2327                            rst_mask1, 3);
2328         }
2329         rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 8);
2330     }
2331 }
2332
2333 static void rtw8852c_ctrl_tx_path_tmac(struct rtw89_dev *rtwdev, u8 tx_path,
2334                        enum rtw89_mac_idx mac_idx)
2335 {
2336     struct rtw89_reg2_def path_com[] = {
2337         {R_AX_PATH_COM0, AX_PATH_COM0_DFVAL},
2338         {R_AX_PATH_COM1, AX_PATH_COM1_DFVAL},
2339         {R_AX_PATH_COM2, AX_PATH_COM2_DFVAL},
2340         {R_AX_PATH_COM3, AX_PATH_COM3_DFVAL},
2341         {R_AX_PATH_COM4, AX_PATH_COM4_DFVAL},
2342         {R_AX_PATH_COM5, AX_PATH_COM5_DFVAL},
2343         {R_AX_PATH_COM6, AX_PATH_COM6_DFVAL},
2344         {R_AX_PATH_COM7, AX_PATH_COM7_DFVAL},
2345         {R_AX_PATH_COM8, AX_PATH_COM8_DFVAL},
2346         {R_AX_PATH_COM9, AX_PATH_COM9_DFVAL},
2347         {R_AX_PATH_COM10, AX_PATH_COM10_DFVAL},
2348         {R_AX_PATH_COM11, AX_PATH_COM11_DFVAL},
2349     };
2350     u32 addr;
2351     u32 reg;
2352     u8 cr_size = ARRAY_SIZE(path_com);
2353     u8 i = 0;
2354
2355     rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0, RTW89_PHY_0);
2356     rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0, RTW89_PHY_1);
2357
2358     for (addr = R_AX_MACID_ANT_TABLE;
2359          addr <= R_AX_MACID_ANT_TABLE_LAST; addr += 4) {
2360         reg = rtw89_mac_reg_by_idx(addr, mac_idx);
2361         rtw89_write32(rtwdev, reg, 0);
2362     }
2363
2364     if (tx_path == RF_A) {
2365         path_com[0].data = AX_PATH_COM0_PATHA;
2366         path_com[1].data = AX_PATH_COM1_PATHA;
2367         path_com[2].data = AX_PATH_COM2_PATHA;
2368         path_com[7].data = AX_PATH_COM7_PATHA;
2369         path_com[8].data = AX_PATH_COM8_PATHA;
2370     } else if (tx_path == RF_B) {
2371         path_com[0].data = AX_PATH_COM0_PATHB;
2372         path_com[1].data = AX_PATH_COM1_PATHB;
2373         path_com[2].data = AX_PATH_COM2_PATHB;
2374         path_com[7].data = AX_PATH_COM7_PATHB;
2375         path_com[8].data = AX_PATH_COM8_PATHB;
2376     } else if (tx_path == RF_AB) {
2377         path_com[0].data = AX_PATH_COM0_PATHAB;
2378         path_com[1].data = AX_PATH_COM1_PATHAB;
2379         path_com[2].data = AX_PATH_COM2_PATHAB;
2380         path_com[7].data = AX_PATH_COM7_PATHAB;
2381         path_com[8].data = AX_PATH_COM8_PATHAB;
2382     } else {
2383         rtw89_warn(rtwdev, "[Invalid Tx Path]Tx Path: %d\n", tx_path);
2384         return;
2385     }
2386
2387     for (i = 0; i < cr_size; i++) {
2388         rtw89_debug(rtwdev, RTW89_DBG_TSSI, "0x%x = 0x%x\n",
2389                 path_com[i].addr, path_com[i].data);
2390         reg = rtw89_mac_reg_by_idx(path_com[i].addr, mac_idx);
2391         rtw89_write32(rtwdev, reg, path_com[i].data);
2392     }
2393 }
2394
2395 static void rtw8852c_bb_ctrl_btc_preagc(struct rtw89_dev *rtwdev, bool bt_en)
2396 {
2397     if (bt_en) {
2398         rtw89_phy_write32_mask(rtwdev, R_PATH0_FRC_FIR_TYPE_V1,
2399                        B_PATH0_FRC_FIR_TYPE_MSK_V1, 0x3);
2400         rtw89_phy_write32_mask(rtwdev, R_PATH1_FRC_FIR_TYPE_V1,
2401                        B_PATH1_FRC_FIR_TYPE_MSK_V1, 0x3);
2402         rtw89_phy_write32_mask(rtwdev, R_PATH0_RXBB_V1,
2403                        B_PATH0_RXBB_MSK_V1, 0xf);
2404         rtw89_phy_write32_mask(rtwdev, R_PATH1_RXBB_V1,
2405                        B_PATH1_RXBB_MSK_V1, 0xf);
2406         rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1,
2407                        B_PATH0_G_LNA6_OP1DB_V1, 0x80);
2408         rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1,
2409                        B_PATH1_G_LNA6_OP1DB_V1, 0x80);
2410         rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1,
2411                        B_PATH0_G_TIA0_LNA6_OP1DB_V1, 0x80);
2412         rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA1_LNA6_OP1DB_V1,
2413                        B_PATH0_G_TIA1_LNA6_OP1DB_V1, 0x80);
2414         rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1,
2415                        B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x80);
2416         rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA1_LNA6_OP1DB_V1,
2417                        B_PATH1_G_TIA1_LNA6_OP1DB_V1, 0x80);
2418         rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_BACKOFF_V1,
2419                        B_PATH0_BT_BACKOFF_V1, 0x780D1E);
2420         rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_BACKOFF_V1,
2421                        B_PATH1_BT_BACKOFF_V1, 0x780D1E);
2422         rtw89_phy_write32_mask(rtwdev, R_P0_BACKOFF_IBADC_V1,
2423                        B_P0_BACKOFF_IBADC_V1, 0x34);
2424         rtw89_phy_write32_mask(rtwdev, R_P1_BACKOFF_IBADC_V1,
2425                        B_P1_BACKOFF_IBADC_V1, 0x34);
2426     } else {
2427         rtw89_phy_write32_mask(rtwdev, R_PATH0_FRC_FIR_TYPE_V1,
2428                        B_PATH0_FRC_FIR_TYPE_MSK_V1, 0x0);
2429         rtw89_phy_write32_mask(rtwdev, R_PATH1_FRC_FIR_TYPE_V1,
2430                        B_PATH1_FRC_FIR_TYPE_MSK_V1, 0x0);
2431         rtw89_phy_write32_mask(rtwdev, R_PATH0_RXBB_V1,
2432                        B_PATH0_RXBB_MSK_V1, 0x60);
2433         rtw89_phy_write32_mask(rtwdev, R_PATH1_RXBB_V1,
2434                        B_PATH1_RXBB_MSK_V1, 0x60);
2435         rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1,
2436                        B_PATH0_G_LNA6_OP1DB_V1, 0x1a);
2437         rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1,
2438                        B_PATH1_G_LNA6_OP1DB_V1, 0x1a);
2439         rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1,
2440                        B_PATH0_G_TIA0_LNA6_OP1DB_V1, 0x2a);
2441         rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA1_LNA6_OP1DB_V1,
2442                        B_PATH0_G_TIA1_LNA6_OP1DB_V1, 0x2a);
2443         rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1,
2444                        B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x2a);
2445         rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA1_LNA6_OP1DB_V1,
2446                        B_PATH1_G_TIA1_LNA6_OP1DB_V1, 0x2a);
2447         rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_BACKOFF_V1,
2448                        B_PATH0_BT_BACKOFF_V1, 0x79E99E);
2449         rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_BACKOFF_V1,
2450                        B_PATH1_BT_BACKOFF_V1, 0x79E99E);
2451         rtw89_phy_write32_mask(rtwdev, R_P0_BACKOFF_IBADC_V1,
2452                        B_P0_BACKOFF_IBADC_V1, 0x26);
2453         rtw89_phy_write32_mask(rtwdev, R_P1_BACKOFF_IBADC_V1,
2454                        B_P1_BACKOFF_IBADC_V1, 0x26);
2455     }
2456 }
2457
2458 static void rtw8852c_bb_cfg_txrx_path(struct rtw89_dev *rtwdev)
2459 {
2460     struct rtw89_hal *hal = &rtwdev->hal;
2461     u8 ntx_path = hal->antenna_tx ? hal->antenna_tx : RF_AB;
2462
2463     rtw8852c_bb_cfg_rx_path(rtwdev, RF_PATH_AB);
2464
2465     if (hal->rx_nss == 1) {
2466         rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0);
2467         rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0);
2468         rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0);
2469         rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0);
2470     } else {
2471         rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 1);
2472         rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 1);
2473         rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 1);
2474         rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 1);
2475     }
2476
2477     rtw8852c_ctrl_tx_path_tmac(rtwdev, ntx_path, RTW89_MAC_0);
2478 }
2479
2480 static u8 rtw8852c_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path)
2481 {
2482     rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1);
2483     rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x0);
2484     rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1);
2485
2486     fsleep(200);
2487
2488     return rtw89_read_rf(rtwdev, rf_path, RR_TM, RR_TM_VAL);
2489 }
2490
2491 static void rtw8852c_btc_set_rfe(struct rtw89_dev *rtwdev)
2492 {
2493     struct rtw89_btc *btc = &rtwdev->btc;
2494     struct rtw89_btc_module *module = &btc->mdinfo;
2495
2496     module->rfe_type = rtwdev->efuse.rfe_type;
2497     module->cv = rtwdev->hal.cv;
2498     module->bt_solo = 0;
2499     module->switch_type = BTC_SWITCH_INTERNAL;
2500
2501     if (module->rfe_type > 0)
2502         module->ant.num = (module->rfe_type % 2 ? 2 : 3);
2503     else
2504         module->ant.num = 2;
2505
2506     module->ant.diversity = 0;
2507     module->ant.isolation = 10;
2508
2509     if (module->ant.num == 3) {
2510         module->ant.type = BTC_ANT_DEDICATED;
2511         module->bt_pos = BTC_BT_ALONE;
2512     } else {
2513         module->ant.type = BTC_ANT_SHARED;
2514         module->bt_pos = BTC_BT_BTG;
2515     }
2516 }
2517
2518 static void rtw8852c_ctrl_btg(struct rtw89_dev *rtwdev, bool btg)
2519 {
2520     if (btg) {
2521         rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1,
2522                        B_PATH0_BT_SHARE_V1, 0x1);
2523         rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1,
2524                        B_PATH0_BTG_PATH_V1, 0x0);
2525         rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1,
2526                        B_PATH1_G_LNA6_OP1DB_V1, 0x20);
2527         rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1,
2528                        B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x30);
2529         rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_SHARE_V1,
2530                        B_PATH1_BT_SHARE_V1, 0x1);
2531         rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG_PATH_V1,
2532                        B_PATH1_BTG_PATH_V1, 0x1);
2533         rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0x0);
2534         rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, B_BT_SHARE, 0x1);
2535         rtw89_phy_write32_mask(rtwdev, R_FC0_BW, B_ANT_RX_BT_SEG0, 0x2);
2536         rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN,
2537                        B_BT_DYN_DC_EST_EN_MSK, 0x1);
2538         rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN,
2539                        0x1);
2540     } else {
2541         rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1,
2542                        B_PATH0_BT_SHARE_V1, 0x0);
2543         rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1,
2544                        B_PATH0_BTG_PATH_V1, 0x0);
2545         rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1,
2546                        B_PATH1_G_LNA6_OP1DB_V1, 0x1a);
2547         rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1,
2548                        B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x2a);
2549         rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_SHARE_V1,
2550                        B_PATH1_BT_SHARE_V1, 0x0);
2551         rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG_PATH_V1,
2552                        B_PATH1_BTG_PATH_V1, 0x0);
2553         rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0xf);
2554         rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P2, 0x4);
2555         rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, B_BT_SHARE, 0x0);
2556         rtw89_phy_write32_mask(rtwdev, R_FC0_BW, B_ANT_RX_BT_SEG0, 0x0);
2557         rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN,
2558                        B_BT_DYN_DC_EST_EN_MSK, 0x0);
2559         rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN,
2560                        0x0);
2561     }
2562 }
2563
2564 static
2565 void rtw8852c_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val)
2566 {
2567     rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x20000);
2568     rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, group);
2569     rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, val);
2570     rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x0);
2571 }
2572
2573 static void rtw8852c_btc_init_cfg(struct rtw89_dev *rtwdev)
2574 {
2575     struct rtw89_btc *btc = &rtwdev->btc;
2576     struct rtw89_btc_module *module = &btc->mdinfo;
2577     const struct rtw89_chip_info *chip = rtwdev->chip;
2578     const struct rtw89_mac_ax_coex coex_params = {
2579         .pta_mode = RTW89_MAC_AX_COEX_RTK_MODE,
2580         .direction = RTW89_MAC_AX_COEX_INNER,
2581     };
2582
2583     /* PTA init  */
2584     rtw89_mac_coex_init_v1(rtwdev, &coex_params);
2585
2586     /* set WL Tx response = Hi-Pri */
2587     chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_TX_RESP, true);
2588     chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_BEACON, true);
2589
2590     /* set rf gnt debug off */
2591     rtw89_write_rf(rtwdev, RF_PATH_A, RR_WLSEL, RFREG_MASK, 0x0);
2592     rtw89_write_rf(rtwdev, RF_PATH_B, RR_WLSEL, RFREG_MASK, 0x0);
2593
2594     /* set WL Tx thru in TRX mask table if GNT_WL = 0 && BT_S1 = ss group */
2595     if (module->ant.type == BTC_ANT_SHARED) {
2596         rtw8852c_set_trx_mask(rtwdev,
2597                       RF_PATH_A, BTC_BT_SS_GROUP, 0x5ff);
2598         rtw8852c_set_trx_mask(rtwdev,
2599                       RF_PATH_B, BTC_BT_SS_GROUP, 0x5ff);
2600         /* set path-A(S0) Tx/Rx no-mask if GNT_WL=0 && BT_S1=tx group */
2601         rtw8852c_set_trx_mask(rtwdev,
2602                       RF_PATH_A, BTC_BT_TX_GROUP, 0x5ff);
2603     } else { /* set WL Tx stb if GNT_WL = 0 && BT_S1 = ss group for 3-ant */
2604         rtw8852c_set_trx_mask(rtwdev,
2605                       RF_PATH_A, BTC_BT_SS_GROUP, 0x5df);
2606         rtw8852c_set_trx_mask(rtwdev,
2607                       RF_PATH_B, BTC_BT_SS_GROUP, 0x5df);
2608     }
2609
2610     /* set PTA break table */
2611     rtw89_write32(rtwdev, R_AX_BT_BREAK_TABLE, BTC_BREAK_PARAM);
2612
2613      /* enable BT counter 0xda10[1:0] = 2b'11 */
2614     rtw89_write32_set(rtwdev,
2615               R_AX_BT_CNT_CFG, B_AX_BT_CNT_EN |
2616               B_AX_BT_CNT_RST_V1);
2617     btc->cx.wl.status.map.init_ok = true;
2618 }
2619
2620 static
2621 void rtw8852c_btc_set_wl_pri(struct rtw89_dev *rtwdev, u8 map, bool state)
2622 {
2623     u32 bitmap = 0;
2624     u32 reg = 0;
2625
2626     switch (map) {
2627     case BTC_PRI_MASK_TX_RESP:
2628         reg = R_BTC_COEX_WL_REQ;
2629         bitmap = B_BTC_RSP_ACK_HI;
2630         break;
2631     case BTC_PRI_MASK_BEACON:
2632         reg = R_BTC_COEX_WL_REQ;
2633         bitmap = B_BTC_TX_BCN_HI;
2634         break;
2635     default:
2636         return;
2637     }
2638
2639     if (state)
2640         rtw89_write32_set(rtwdev, reg, bitmap);
2641     else
2642         rtw89_write32_clr(rtwdev, reg, bitmap);
2643 }
2644
2645 union rtw8852c_btc_wl_txpwr_ctrl {
2646     u32 txpwr_val;
2647     struct {
2648         union {
2649             u16 ctrl_all_time;
2650             struct {
2651                 s16 data:9;
2652                 u16 rsvd:6;
2653                 u16 flag:1;
2654             } all_time;
2655         };
2656         union {
2657             u16 ctrl_gnt_bt;
2658             struct {
2659                 s16 data:9;
2660                 u16 rsvd:7;
2661             } gnt_bt;
2662         };
2663     };
2664 } __packed;
2665
2666 static void
2667 rtw8852c_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val)
2668 {
2669     union rtw8852c_btc_wl_txpwr_ctrl arg = { .txpwr_val = txpwr_val };
2670     s32 val;
2671
2672 #define __write_ctrl(_reg, _msk, _val, _en, _cond)      \
2673 do {                                \
2674     u32 _wrt = FIELD_PREP(_msk, _val);          \
2675     BUILD_BUG_ON((_msk & _en) != 0);            \
2676     if (_cond)                      \
2677         _wrt |= _en;                    \
2678     else                            \
2679         _wrt &= ~_en;                   \
2680     rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, _reg, \
2681                      _msk | _en, _wrt);     \
2682 } while (0)
2683
2684     switch (arg.ctrl_all_time) {
2685     case 0xffff:
2686         val = 0;
2687         break;
2688     default:
2689         val = arg.all_time.data;
2690         break;
2691     }
2692
2693     __write_ctrl(R_AX_PWR_RATE_CTRL, B_AX_FORCE_PWR_BY_RATE_VALUE_MASK,
2694              val, B_AX_FORCE_PWR_BY_RATE_EN,
2695              arg.ctrl_all_time != 0xffff);
2696
2697     switch (arg.ctrl_gnt_bt) {
2698     case 0xffff:
2699         val = 0;
2700         break;
2701     default:
2702         val = arg.gnt_bt.data;
2703         break;
2704     }
2705
2706     __write_ctrl(R_AX_PWR_COEXT_CTRL, B_AX_TXAGC_BT_MASK, val,
2707              B_AX_TXAGC_BT_EN, arg.ctrl_gnt_bt != 0xffff);
2708
2709 #undef __write_ctrl
2710 }
2711
2712 static
2713 s8 rtw8852c_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val)
2714 {
2715     return clamp_t(s8, val, -100, 0) + 100;
2716 }
2717
2718 static const struct rtw89_btc_rf_trx_para rtw89_btc_8852c_rf_ul[] = {
2719     {255, 0, 0, 7}, /* 0 -> original */
2720     {255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */
2721     {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */
2722     {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */
2723     {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */
2724     {255, 0, 0, 7}, /* the below id is for non-shared-antenna free-run */
2725     {6, 1, 0, 7},
2726     {13, 1, 0, 7},
2727     {13, 1, 0, 7}
2728 };
2729
2730 static const struct rtw89_btc_rf_trx_para rtw89_btc_8852c_rf_dl[] = {
2731     {255, 0, 0, 7}, /* 0 -> original */
2732     {255, 2, 0, 7}, /* 1 -> reserved for shared-antenna */
2733     {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */
2734     {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */
2735     {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */
2736     {255, 0, 0, 7}, /* the below id is for non-shared-antenna free-run */
2737     {255, 1, 0, 7},
2738     {255, 1, 0, 7},
2739     {255, 1, 0, 7}
2740 };
2741
2742 static const u8 rtw89_btc_8852c_wl_rssi_thres[BTC_WL_RSSI_THMAX] = {60, 50, 40, 30};
2743 static const u8 rtw89_btc_8852c_bt_rssi_thres[BTC_BT_RSSI_THMAX] = {40, 36, 31, 28};
2744
2745 static const struct rtw89_btc_fbtc_mreg rtw89_btc_8852c_mon_reg[] = {
2746     RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda00),
2747     RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda04),
2748     RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda24),
2749     RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda30),
2750     RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda34),
2751     RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda38),
2752     RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda44),
2753     RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda48),
2754     RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda4c),
2755     RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd200),
2756     RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd220),
2757     RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x980),
2758 };
2759
2760 static
2761 void rtw8852c_btc_bt_aci_imp(struct rtw89_dev *rtwdev)
2762 {
2763     struct rtw89_btc *btc = &rtwdev->btc;
2764     struct rtw89_btc_dm *dm = &btc->dm;
2765     struct rtw89_btc_bt_info *bt = &btc->cx.bt;
2766     struct rtw89_btc_bt_link_info *b = &bt->link_info;
2767
2768     /* fix LNA2 = level-5 for BT ACI issue at BTG */
2769     if (btc->dm.wl_btg_rx && b->profile_cnt.now != 0)
2770         dm->trx_para_level = 1;
2771 }
2772
2773 static
2774 void rtw8852c_btc_update_bt_cnt(struct rtw89_dev *rtwdev)
2775 {
2776     struct rtw89_btc *btc = &rtwdev->btc;
2777     struct rtw89_btc_cx *cx = &btc->cx;
2778     u32 val;
2779
2780     val = rtw89_read32(rtwdev, R_BTC_BT_CNT_HIGH);
2781     cx->cnt_bt[BTC_BCNT_HIPRI_TX] = FIELD_GET(B_AX_STATIS_BT_HI_TX_MASK, val);
2782     cx->cnt_bt[BTC_BCNT_HIPRI_RX] = FIELD_GET(B_AX_STATIS_BT_HI_RX_MASK, val);
2783
2784     val = rtw89_read32(rtwdev, R_BTC_BT_CNT_LOW);
2785     cx->cnt_bt[BTC_BCNT_LOPRI_TX] = FIELD_GET(B_AX_STATIS_BT_LO_TX_1_MASK, val);
2786     cx->cnt_bt[BTC_BCNT_LOPRI_RX] = FIELD_GET(B_AX_STATIS_BT_LO_RX_1_MASK, val);
2787
2788     /* clock-gate off before reset counter*/
2789     rtw89_write32_set(rtwdev, R_AX_BTC_CFG, B_AX_DIS_BTC_CLK_G);
2790     rtw89_write32_clr(rtwdev, R_AX_BT_CNT_CFG, B_AX_BT_CNT_RST);
2791     rtw89_write32_set(rtwdev, R_AX_BT_CNT_CFG, B_AX_BT_CNT_RST);
2792     rtw89_write32_clr(rtwdev, R_AX_BTC_CFG, B_AX_DIS_BTC_CLK_G);
2793 }
2794
2795 static
2796 void rtw8852c_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state)
2797 {
2798     rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x80000);
2799     rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1);
2800     rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD1, RFREG_MASK, 0x620);
2801
2802     /* set WL standby = Rx for GNT_BT_Tx = 1->0 settle issue */
2803     if (state)
2804         rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0,
2805                    RFREG_MASK, 0x179c);
2806     else
2807         rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0,
2808                    RFREG_MASK, 0x208);
2809
2810     rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0);
2811 }
2812
2813 static void rtw8852c_fill_freq_with_ppdu(struct rtw89_dev *rtwdev,
2814                      struct rtw89_rx_phy_ppdu *phy_ppdu,
2815                      struct ieee80211_rx_status *status)
2816 {
2817     u8 chan_idx = phy_ppdu->chan_idx;
2818     enum nl80211_band band;
2819     u8 ch;
2820
2821     if (chan_idx == 0)
2822         return;
2823
2824     rtw8852c_decode_chan_idx(rtwdev, chan_idx, &ch, &band);
2825     status->freq = ieee80211_channel_to_frequency(ch, band);
2826     status->band = band;
2827 }
2828
2829 static void rtw8852c_query_ppdu(struct rtw89_dev *rtwdev,
2830                 struct rtw89_rx_phy_ppdu *phy_ppdu,
2831                 struct ieee80211_rx_status *status)
2832 {
2833     u8 path;
2834     s8 *rx_power = phy_ppdu->rssi;
2835
2836     status->signal = max_t(s8, rx_power[RF_PATH_A], rx_power[RF_PATH_B]);
2837     for (path = 0; path < rtwdev->chip->rf_path_num; path++) {
2838         status->chains |= BIT(path);
2839         status->chain_signal[path] = rx_power[path];
2840     }
2841     if (phy_ppdu->valid)
2842         rtw8852c_fill_freq_with_ppdu(rtwdev, phy_ppdu, status);
2843 }
2844
2845 static int rtw8852c_mac_enable_bb_rf(struct rtw89_dev *rtwdev)
2846 {
2847     int ret;
2848
2849     rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN,
2850              B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN);
2851
2852     rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
2853     rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
2854     rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
2855
2856     rtw89_write32_mask(rtwdev, R_AX_AFE_OFF_CTRL1, B_AX_S0_LDO_VSEL_F_MASK, 0x1);
2857     rtw89_write32_mask(rtwdev, R_AX_AFE_OFF_CTRL1, B_AX_S1_LDO_VSEL_F_MASK, 0x1);
2858
2859     ret = rtw89_mac_write_xtal_si(rtwdev, XTAL0, 0x7, FULL_BIT_MASK);
2860     if (ret)
2861         return ret;
2862
2863     ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x6c, FULL_BIT_MASK);
2864     if (ret)
2865         return ret;
2866
2867     ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0xc7, FULL_BIT_MASK);
2868     if (ret)
2869         return ret;
2870
2871     ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0xc7, FULL_BIT_MASK);
2872     if (ret)
2873         return ret;
2874
2875     ret = rtw89_mac_write_xtal_si(rtwdev, XTAL3, 0xd, FULL_BIT_MASK);
2876     if (ret)
2877         return ret;
2878
2879     return 0;
2880 }
2881
2882 static void rtw8852c_mac_disable_bb_rf(struct rtw89_dev *rtwdev)
2883 {
2884     rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN,
2885              B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN);
2886 }
2887
2888 static const struct rtw89_chip_ops rtw8852c_chip_ops = {
2889     .enable_bb_rf       = rtw8852c_mac_enable_bb_rf,
2890     .disable_bb_rf      = rtw8852c_mac_disable_bb_rf,
2891     .bb_reset       = rtw8852c_bb_reset,
2892     .bb_sethw       = rtw8852c_bb_sethw,
2893     .read_rf        = rtw89_phy_read_rf_v1,
2894     .write_rf       = rtw89_phy_write_rf_v1,
2895     .set_channel        = rtw8852c_set_channel,
2896     .set_channel_help   = rtw8852c_set_channel_help,
2897     .read_efuse     = rtw8852c_read_efuse,
2898     .read_phycap        = rtw8852c_read_phycap,
2899     .fem_setup      = NULL,
2900     .rfk_init       = rtw8852c_rfk_init,
2901     .rfk_channel        = rtw8852c_rfk_channel,
2902     .rfk_band_changed   = rtw8852c_rfk_band_changed,
2903     .rfk_scan       = rtw8852c_rfk_scan,
2904     .rfk_track      = rtw8852c_rfk_track,
2905     .power_trim     = rtw8852c_power_trim,
2906     .set_txpwr      = rtw8852c_set_txpwr,
2907     .set_txpwr_ctrl     = rtw8852c_set_txpwr_ctrl,
2908     .init_txpwr_unit    = rtw8852c_init_txpwr_unit,
2909     .get_thermal        = rtw8852c_get_thermal,
2910     .ctrl_btg       = rtw8852c_ctrl_btg,
2911     .query_ppdu     = rtw8852c_query_ppdu,
2912     .bb_ctrl_btc_preagc = rtw8852c_bb_ctrl_btc_preagc,
2913     .cfg_txrx_path      = rtw8852c_bb_cfg_txrx_path,
2914     .set_txpwr_ul_tb_offset = rtw8852c_set_txpwr_ul_tb_offset,
2915     .pwr_on_func        = rtw8852c_pwr_on_func,
2916     .pwr_off_func       = rtw8852c_pwr_off_func,
2917     .fill_txdesc        = rtw89_core_fill_txdesc_v1,
2918     .fill_txdesc_fwcmd  = rtw89_core_fill_txdesc_fwcmd_v1,
2919     .cfg_ctrl_path      = rtw89_mac_cfg_ctrl_path_v1,
2920     .mac_cfg_gnt        = rtw89_mac_cfg_gnt_v1,
2921     .stop_sch_tx        = rtw89_mac_stop_sch_tx_v1,
2922     .resume_sch_tx      = rtw89_mac_resume_sch_tx_v1,
2923     .h2c_dctl_sec_cam   = rtw89_fw_h2c_dctl_sec_cam_v1,
2924
2925     .btc_set_rfe        = rtw8852c_btc_set_rfe,
2926     .btc_init_cfg       = rtw8852c_btc_init_cfg,
2927     .btc_set_wl_pri     = rtw8852c_btc_set_wl_pri,
2928     .btc_set_wl_txpwr_ctrl  = rtw8852c_btc_set_wl_txpwr_ctrl,
2929     .btc_get_bt_rssi    = rtw8852c_btc_get_bt_rssi,
2930     .btc_bt_aci_imp     = rtw8852c_btc_bt_aci_imp,
2931     .btc_update_bt_cnt  = rtw8852c_btc_update_bt_cnt,
2932     .btc_wl_s1_standby  = rtw8852c_btc_wl_s1_standby,
2933 };
2934
2935 const struct rtw89_chip_info rtw8852c_chip_info = {
2936     .chip_id        = RTL8852C,
2937     .ops            = &rtw8852c_chip_ops,
2938     .fw_name        = "rtw89/rtw8852c_fw.bin",
2939     .fifo_size      = 458752,
2940     .max_amsdu_limit    = 8000,
2941     .dis_2g_40m_ul_ofdma    = false,
2942     .rsvd_ple_ofst      = 0x6f800,
2943     .hfc_param_ini      = rtw8852c_hfc_param_ini_pcie,
2944     .dle_mem        = rtw8852c_dle_mem_pcie,
2945     .rf_base_addr       = {0xe000, 0xf000},
2946     .pwr_on_seq     = NULL,
2947     .pwr_off_seq        = NULL,
2948     .bb_table       = &rtw89_8852c_phy_bb_table,
2949     .bb_gain_table      = &rtw89_8852c_phy_bb_gain_table,
2950     .rf_table       = {&rtw89_8852c_phy_radiob_table,
2951                    &rtw89_8852c_phy_radioa_table,},
2952     .nctl_table     = &rtw89_8852c_phy_nctl_table,
2953     .byr_table      = &rtw89_8852c_byr_table,
2954     .txpwr_lmt_2g       = &rtw89_8852c_txpwr_lmt_2g,
2955     .txpwr_lmt_5g       = &rtw89_8852c_txpwr_lmt_5g,
2956     .txpwr_lmt_6g       = &rtw89_8852c_txpwr_lmt_6g,
2957     .txpwr_lmt_ru_2g    = &rtw89_8852c_txpwr_lmt_ru_2g,
2958     .txpwr_lmt_ru_5g    = &rtw89_8852c_txpwr_lmt_ru_5g,
2959     .txpwr_lmt_ru_6g    = &rtw89_8852c_txpwr_lmt_ru_6g,
2960     .txpwr_factor_rf    = 2,
2961     .txpwr_factor_mac   = 1,
2962     .dig_table      = NULL,
2963     .tssi_dbw_table     = &rtw89_8852c_tssi_dbw_table,
2964     .support_bands      = BIT(NL80211_BAND_2GHZ) |
2965                   BIT(NL80211_BAND_5GHZ) |
2966                   BIT(NL80211_BAND_6GHZ),
2967     .support_bw160      = true,
2968     .hw_sec_hdr     = true,
2969     .rf_path_num        = 2,
2970     .tx_nss         = 2,
2971     .rx_nss         = 2,
2972     .acam_num       = 128,
2973     .bcam_num       = 20,
2974     .scam_num       = 128,
2975     .sec_ctrl_efuse_size    = 4,
2976     .physical_efuse_size    = 1216,
2977     .logical_efuse_size = 2048,
2978     .limit_efuse_size   = 1280,
2979     .dav_phy_efuse_size = 96,
2980     .dav_log_efuse_size = 16,
2981     .phycap_addr        = 0x590,
2982     .phycap_size        = 0x60,
2983     .para_ver       = 0x05050764,
2984     .wlcx_desired       = 0x05050000,
2985     .btcx_desired       = 0x5,
2986     .scbd           = 0x1,
2987     .mailbox        = 0x1,
2988     .afh_guard_ch       = 6,
2989     .wl_rssi_thres      = rtw89_btc_8852c_wl_rssi_thres,
2990     .bt_rssi_thres      = rtw89_btc_8852c_bt_rssi_thres,
2991     .rssi_tol       = 2,
2992     .mon_reg_num        = ARRAY_SIZE(rtw89_btc_8852c_mon_reg),
2993     .mon_reg        = rtw89_btc_8852c_mon_reg,
2994     .rf_para_ulink_num  = ARRAY_SIZE(rtw89_btc_8852c_rf_ul),
2995     .rf_para_ulink      = rtw89_btc_8852c_rf_ul,
2996     .rf_para_dlink_num  = ARRAY_SIZE(rtw89_btc_8852c_rf_dl),
2997     .rf_para_dlink      = rtw89_btc_8852c_rf_dl,
2998     .ps_mode_supported  = 0,
2999     .low_power_hci_modes    = BIT(RTW89_PS_MODE_CLK_GATED) |
3000                   BIT(RTW89_PS_MODE_PWR_GATED),
3001     .h2c_cctl_func_id   = H2C_FUNC_MAC_CCTLINFO_UD_V1,
3002     .hci_func_en_addr   = R_AX_HCI_FUNC_EN_V1,
3003     .h2c_desc_size      = sizeof(struct rtw89_rxdesc_short),
3004     .txwd_body_size     = sizeof(struct rtw89_txwd_body_v1),
3005     .h2c_ctrl_reg       = R_AX_H2CREG_CTRL_V1,
3006     .h2c_regs       = rtw8852c_h2c_regs,
3007     .c2h_ctrl_reg       = R_AX_C2HREG_CTRL_V1,
3008     .c2h_regs       = rtw8852c_c2h_regs,
3009     .page_regs      = &rtw8852c_page_regs,
3010     .dcfo_comp      = &rtw8852c_dcfo_comp,
3011     .dcfo_comp_sft      = 5,
3012     .imr_info       = &rtw8852c_imr_info
3013 };
3014 EXPORT_SYMBOL(rtw8852c_chip_info);
3015
3016 MODULE_FIRMWARE("rtw89/rtw8852c_fw.bin");
3017 MODULE_AUTHOR("Realtek Corporation");
3018 MODULE_DESCRIPTION("Realtek 802.11ax wireless 8852C driver");
3019 MODULE_LICENSE("Dual BSD/GPL");