realtek/rtw89/rtw8852a.h

0001 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
0002 /* Copyright(c) 2019-2020  Realtek Corporation
0003  */
0004
0005 #ifndef __RTW89_8852A_H__
0006 #define __RTW89_8852A_H__
0007
0008 #include "core.h"
0009
0010 #define RF_PATH_NUM_8852A 2
0011 #define NTX_NUM_8852A 2
0012
0013 enum rtw8852a_pmac_mode {
0014     NONE_TEST,
0015     PKTS_TX,
0016     PKTS_RX,
0017     CONT_TX
0018 };
0019
0020 struct rtw8852au_efuse {
0021     u8 rsvd[0x38];
0022     u8 mac_addr[ETH_ALEN];
0023 };
0024
0025 struct rtw8852ae_efuse {
0026     u8 mac_addr[ETH_ALEN];
0027 };
0028
0029 struct rtw8852a_tssi_offset {
0030     u8 cck_tssi[TSSI_CCK_CH_GROUP_NUM];
0031     u8 bw40_tssi[TSSI_MCS_2G_CH_GROUP_NUM];
0032     u8 rsvd[7];
0033     u8 bw40_1s_tssi_5g[TSSI_MCS_5G_CH_GROUP_NUM];
0034 } __packed;
0035
0036 struct rtw8852a_efuse {
0037     u8 rsvd[0x210];
0038     struct rtw8852a_tssi_offset path_a_tssi;
0039     u8 rsvd1[10];
0040     struct rtw8852a_tssi_offset path_b_tssi;
0041     u8 rsvd2[94];
0042     u8 channel_plan;
0043     u8 xtal_k;
0044     u8 rsvd3;
0045     u8 iqk_lck;
0046     u8 rsvd4[5];
0047     u8 reg_setting:2;
0048     u8 tx_diversity:1;
0049     u8 rx_diversity:2;
0050     u8 ac_mode:1;
0051     u8 module_type:2;
0052     u8 rsvd5;
0053     u8 shared_ant:1;
0054     u8 coex_type:3;
0055     u8 ant_iso:1;
0056     u8 radio_on_off:1;
0057     u8 rsvd6:2;
0058     u8 eeprom_version;
0059     u8 customer_id;
0060     u8 tx_bb_swing_2g;
0061     u8 tx_bb_swing_5g;
0062     u8 tx_cali_pwr_trk_mode;
0063     u8 trx_path_selection;
0064     u8 rfe_type;
0065     u8 country_code[2];
0066     u8 rsvd7[3];
0067     u8 path_a_therm;
0068     u8 path_b_therm;
0069     u8 rsvd8[46];
0070     u8 path_a_cck_pwr_idx[6];
0071     u8 path_a_bw40_1tx_pwr_idx[5];
0072     u8 path_a_ofdm_1tx_pwr_idx_diff:4;
0073     u8 path_a_bw20_1tx_pwr_idx_diff:4;
0074     u8 path_a_bw20_2tx_pwr_idx_diff:4;
0075     u8 path_a_bw40_2tx_pwr_idx_diff:4;
0076     u8 path_a_cck_2tx_pwr_idx_diff:4;
0077     u8 path_a_ofdm_2tx_pwr_idx_diff:4;
0078     u8 rsvd9[0xf2];
0079     union {
0080         struct rtw8852au_efuse u;
0081         struct rtw8852ae_efuse e;
0082     };
0083 } __packed;
0084
0085 struct rtw8852a_bb_pmac_info {
0086     u8 en_pmac_tx:1;
0087     u8 is_cck:1;
0088     u8 mode:3;
0089     u8 rsvd:3;
0090     u16 tx_cnt;
0091     u16 period;
0092     u16 tx_time;
0093     u8 duty_cycle;
0094 };
0095
0096 extern const struct rtw89_chip_info rtw8852a_chip_info;
0097
0098 void rtw8852a_bb_set_plcp_tx(struct rtw89_dev *rtwdev);
0099 void rtw8852a_bb_set_pmac_tx(struct rtw89_dev *rtwdev,
0100                  struct rtw8852a_bb_pmac_info *tx_info,
0101                  enum rtw89_phy_idx idx);
0102 void rtw8852a_bb_set_pmac_pkt_tx(struct rtw89_dev *rtwdev, u8 enable,
0103                  u16 tx_cnt, u16 period, u16 tx_time,
0104                  enum rtw89_phy_idx idx);
0105 void rtw8852a_bb_set_power(struct rtw89_dev *rtwdev, s16 pwr_dbm,
0106                enum rtw89_phy_idx idx);
0107 void rtw8852a_bb_cfg_tx_path(struct rtw89_dev *rtwdev, u8 tx_path);
0108 void rtw8852a_bb_tx_mode_switch(struct rtw89_dev *rtwdev,
0109                 enum rtw89_phy_idx idx, u8 mode);
0110
0111 #endif