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0005 #ifndef __RTW89_PHY_H__
0006 #define __RTW89_PHY_H__
0007
0008 #include "core.h"
0009
0010 #define RTW89_PHY_ADDR_OFFSET 0x10000
0011 #define RTW89_RF_ADDR_ADSEL_MASK BIT(16)
0012
0013 #define get_phy_headline(addr) FIELD_GET(GENMASK(31, 28), addr)
0014 #define PHY_HEADLINE_VALID 0xf
0015 #define get_phy_target(addr) FIELD_GET(GENMASK(27, 0), addr)
0016 #define get_phy_compare(rfe, cv) (FIELD_PREP(GENMASK(23, 16), rfe) | \
0017 FIELD_PREP(GENMASK(7, 0), cv))
0018
0019 #define get_phy_cond(addr) FIELD_GET(GENMASK(31, 28), addr)
0020 #define get_phy_cond_rfe(addr) FIELD_GET(GENMASK(23, 16), addr)
0021 #define get_phy_cond_pkg(addr) FIELD_GET(GENMASK(15, 8), addr)
0022 #define get_phy_cond_cv(addr) FIELD_GET(GENMASK(7, 0), addr)
0023 #define phy_div(a, b) ({typeof(b) _b = (b); (_b) ? ((a) / (_b)) : 0; })
0024 #define PHY_COND_BRANCH_IF 0x8
0025 #define PHY_COND_BRANCH_ELIF 0x9
0026 #define PHY_COND_BRANCH_ELSE 0xa
0027 #define PHY_COND_BRANCH_END 0xb
0028 #define PHY_COND_CHECK 0x4
0029 #define PHY_COND_DONT_CARE 0xff
0030
0031 #define RA_MASK_CCK_RATES GENMASK_ULL(3, 0)
0032 #define RA_MASK_OFDM_RATES GENMASK_ULL(11, 4)
0033 #define RA_MASK_SUBCCK_RATES 0x5ULL
0034 #define RA_MASK_SUBOFDM_RATES 0x10ULL
0035 #define RA_MASK_HT_1SS_RATES GENMASK_ULL(19, 12)
0036 #define RA_MASK_HT_2SS_RATES GENMASK_ULL(31, 24)
0037 #define RA_MASK_HT_3SS_RATES GENMASK_ULL(43, 36)
0038 #define RA_MASK_HT_4SS_RATES GENMASK_ULL(55, 48)
0039 #define RA_MASK_HT_RATES GENMASK_ULL(55, 12)
0040 #define RA_MASK_VHT_1SS_RATES GENMASK_ULL(21, 12)
0041 #define RA_MASK_VHT_2SS_RATES GENMASK_ULL(33, 24)
0042 #define RA_MASK_VHT_3SS_RATES GENMASK_ULL(45, 36)
0043 #define RA_MASK_VHT_4SS_RATES GENMASK_ULL(57, 48)
0044 #define RA_MASK_VHT_RATES GENMASK_ULL(57, 12)
0045 #define RA_MASK_HE_1SS_RATES GENMASK_ULL(23, 12)
0046 #define RA_MASK_HE_2SS_RATES GENMASK_ULL(35, 24)
0047 #define RA_MASK_HE_3SS_RATES GENMASK_ULL(47, 36)
0048 #define RA_MASK_HE_4SS_RATES GENMASK_ULL(59, 48)
0049 #define RA_MASK_HE_RATES GENMASK_ULL(59, 12)
0050
0051 #define CFO_TRK_ENABLE_TH (2 << 2)
0052 #define CFO_TRK_STOP_TH_4 (30 << 2)
0053 #define CFO_TRK_STOP_TH_3 (20 << 2)
0054 #define CFO_TRK_STOP_TH_2 (10 << 2)
0055 #define CFO_TRK_STOP_TH_1 (00 << 2)
0056 #define CFO_TRK_STOP_TH (2 << 2)
0057 #define CFO_SW_COMP_FINE_TUNE (2 << 2)
0058 #define CFO_PERIOD_CNT 15
0059 #define CFO_BOUND 32
0060 #define CFO_TP_UPPER 100
0061 #define CFO_TP_LOWER 50
0062 #define CFO_COMP_PERIOD 250
0063 #define CFO_COMP_WEIGHT 8
0064 #define MAX_CFO_TOLERANCE 30
0065 #define CFO_TF_CNT_TH 300
0066
0067 #define CCX_MAX_PERIOD 2097
0068 #define CCX_MAX_PERIOD_UNIT 32
0069 #define MS_TO_4US_RATIO 250
0070 #define ENV_MNTR_FAIL_DWORD 0xffffffff
0071 #define ENV_MNTR_IFSCLM_HIS_MAX 127
0072 #define PERMIL 1000
0073 #define PERCENT 100
0074 #define IFS_CLM_TH0_UPPER 64
0075 #define IFS_CLM_TH_MUL 4
0076 #define IFS_CLM_TH_START_IDX 0
0077
0078 #define TIA0_GAIN_A 12
0079 #define TIA0_GAIN_G 16
0080 #define LNA0_GAIN (-24)
0081 #define U4_MAX_BIT 3
0082 #define U8_MAX_BIT 7
0083 #define DIG_GAIN_SHIFT 2
0084 #define DIG_GAIN 8
0085
0086 #define LNA_IDX_MAX 6
0087 #define LNA_IDX_MIN 0
0088 #define TIA_IDX_MAX 1
0089 #define TIA_IDX_MIN 0
0090 #define RXB_IDX_MAX 31
0091 #define RXB_IDX_MIN 0
0092
0093 #define IGI_RSSI_MAX 110
0094 #define PD_TH_MAX_RSSI 70
0095 #define PD_TH_MIN_RSSI 8
0096 #define CCKPD_TH_MIN_RSSI (-18)
0097 #define PD_TH_BW160_CMP_VAL 9
0098 #define PD_TH_BW80_CMP_VAL 6
0099 #define PD_TH_BW40_CMP_VAL 3
0100 #define PD_TH_BW20_CMP_VAL 0
0101 #define PD_TH_CMP_VAL 3
0102 #define PD_TH_SB_FLTR_CMP_VAL 7
0103
0104 #define PHYSTS_MGNT BIT(RTW89_RX_TYPE_MGNT)
0105 #define PHYSTS_CTRL BIT(RTW89_RX_TYPE_CTRL)
0106 #define PHYSTS_DATA BIT(RTW89_RX_TYPE_DATA)
0107 #define PHYSTS_RSVD BIT(RTW89_RX_TYPE_RSVD)
0108 #define PPDU_FILTER_BITMAP (PHYSTS_MGNT | PHYSTS_DATA)
0109
0110 enum rtw89_phy_c2h_ra_func {
0111 RTW89_PHY_C2H_FUNC_STS_RPT,
0112 RTW89_PHY_C2H_FUNC_MU_GPTBL_RPT,
0113 RTW89_PHY_C2H_FUNC_TXSTS,
0114 RTW89_PHY_C2H_FUNC_RA_MAX,
0115 };
0116
0117 enum rtw89_phy_c2h_class {
0118 RTW89_PHY_C2H_CLASS_RUA,
0119 RTW89_PHY_C2H_CLASS_RA,
0120 RTW89_PHY_C2H_CLASS_DM,
0121 RTW89_PHY_C2H_CLASS_BTC_MIN = 0x10,
0122 RTW89_PHY_C2H_CLASS_BTC_MAX = 0x17,
0123 RTW89_PHY_C2H_CLASS_MAX,
0124 };
0125
0126 enum rtw89_env_monitor_result_level {
0127 RTW89_PHY_ENV_MON_CCX_FAIL = 0,
0128 RTW89_PHY_ENV_MON_NHM = BIT(0),
0129 RTW89_PHY_ENV_MON_CLM = BIT(1),
0130 RTW89_PHY_ENV_MON_FAHM = BIT(2),
0131 RTW89_PHY_ENV_MON_IFS_CLM = BIT(3),
0132 RTW89_PHY_ENV_MON_EDCCA_CLM = BIT(4),
0133 };
0134
0135 #define CCX_US_BASE_RATIO 4
0136 enum rtw89_ccx_unit {
0137 RTW89_CCX_4_US = 0,
0138 RTW89_CCX_8_US = 1,
0139 RTW89_CCX_16_US = 2,
0140 RTW89_CCX_32_US = 3
0141 };
0142
0143 enum rtw89_phy_status_ie_type {
0144 RTW89_PHYSTS_IE00_CMN_CCK = 0,
0145 RTW89_PHYSTS_IE01_CMN_OFDM = 1,
0146 RTW89_PHYSTS_IE02_CMN_EXT_AX = 2,
0147 RTW89_PHYSTS_IE03_CMN_EXT_SEG_1 = 3,
0148 RTW89_PHYSTS_IE04_CMN_EXT_PATH_A = 4,
0149 RTW89_PHYSTS_IE05_CMN_EXT_PATH_B = 5,
0150 RTW89_PHYSTS_IE06_CMN_EXT_PATH_C = 6,
0151 RTW89_PHYSTS_IE07_CMN_EXT_PATH_D = 7,
0152 RTW89_PHYSTS_IE08_FTR_CH = 8,
0153 RTW89_PHYSTS_IE09_FTR_0 = 9,
0154 RTW89_PHYSTS_IE10_FTR_PLCP_EXT = 10,
0155 RTW89_PHYSTS_IE11_FTR_PLCP_HISTOGRAM = 11,
0156 RTW89_PHYSTS_IE12_MU_EIGEN_INFO = 12,
0157 RTW89_PHYSTS_IE13_DL_MU_DEF = 13,
0158 RTW89_PHYSTS_IE14_TB_UL_CQI = 14,
0159 RTW89_PHYSTS_IE15_TB_UL_DEF = 15,
0160 RTW89_PHYSTS_IE16_RSVD16 = 16,
0161 RTW89_PHYSTS_IE17_TB_UL_CTRL = 17,
0162 RTW89_PHYSTS_IE18_DBG_OFDM_FD_CMN = 18,
0163 RTW89_PHYSTS_IE19_DBG_OFDM_TD_CMN = 19,
0164 RTW89_PHYSTS_IE20_DBG_OFDM_FD_USER_SEG_0 = 20,
0165 RTW89_PHYSTS_IE21_DBG_OFDM_FD_USER_SEG_1 = 21,
0166 RTW89_PHYSTS_IE22_DBG_OFDM_FD_USER_AGC = 22,
0167 RTW89_PHYSTS_IE23_RSVD23 = 23,
0168 RTW89_PHYSTS_IE24_OFDM_TD_PATH_A = 24,
0169 RTW89_PHYSTS_IE25_OFDM_TD_PATH_B = 25,
0170 RTW89_PHYSTS_IE26_OFDM_TD_PATH_C = 26,
0171 RTW89_PHYSTS_IE27_OFDM_TD_PATH_D = 27,
0172 RTW89_PHYSTS_IE28_DBG_CCK_PATH_A = 28,
0173 RTW89_PHYSTS_IE29_DBG_CCK_PATH_B = 29,
0174 RTW89_PHYSTS_IE30_DBG_CCK_PATH_C = 30,
0175 RTW89_PHYSTS_IE31_DBG_CCK_PATH_D = 31,
0176
0177
0178 RTW89_PHYSTS_IE_NUM,
0179 RTW89_PHYSTS_IE_MAX = RTW89_PHYSTS_IE_NUM - 1
0180 };
0181
0182 enum rtw89_phy_status_bitmap {
0183 RTW89_TD_SEARCH_FAIL = 0,
0184 RTW89_BRK_BY_TX_PKT = 1,
0185 RTW89_CCA_SPOOF = 2,
0186 RTW89_OFDM_BRK = 3,
0187 RTW89_CCK_BRK = 4,
0188 RTW89_DL_MU_SPOOFING = 5,
0189 RTW89_HE_MU = 6,
0190 RTW89_VHT_MU = 7,
0191 RTW89_UL_TB_SPOOFING = 8,
0192 RTW89_RSVD_9 = 9,
0193 RTW89_TRIG_BASE_PPDU = 10,
0194 RTW89_CCK_PKT = 11,
0195 RTW89_LEGACY_OFDM_PKT = 12,
0196 RTW89_HT_PKT = 13,
0197 RTW89_VHT_PKT = 14,
0198 RTW89_HE_PKT = 15,
0199
0200 RTW89_PHYSTS_BITMAP_NUM
0201 };
0202
0203 enum rtw89_dig_gain_type {
0204 RTW89_DIG_GAIN_LNA_G = 0,
0205 RTW89_DIG_GAIN_TIA_G = 1,
0206 RTW89_DIG_GAIN_LNA_A = 2,
0207 RTW89_DIG_GAIN_TIA_A = 3,
0208 RTW89_DIG_GAIN_MAX = 4
0209 };
0210
0211 enum rtw89_dig_gain_lna_idx {
0212 RTW89_DIG_GAIN_LNA_IDX1 = 1,
0213 RTW89_DIG_GAIN_LNA_IDX2 = 2,
0214 RTW89_DIG_GAIN_LNA_IDX3 = 3,
0215 RTW89_DIG_GAIN_LNA_IDX4 = 4,
0216 RTW89_DIG_GAIN_LNA_IDX5 = 5,
0217 RTW89_DIG_GAIN_LNA_IDX6 = 6
0218 };
0219
0220 enum rtw89_dig_gain_tia_idx {
0221 RTW89_DIG_GAIN_TIA_IDX0 = 0,
0222 RTW89_DIG_GAIN_TIA_IDX1 = 1
0223 };
0224
0225 enum rtw89_tssi_bandedge_cfg {
0226 RTW89_TSSI_BANDEDGE_FLAT,
0227 RTW89_TSSI_BANDEDGE_LOW,
0228 RTW89_TSSI_BANDEDGE_MID,
0229 RTW89_TSSI_BANDEDGE_HIGH,
0230
0231 RTW89_TSSI_CFG_NUM,
0232 };
0233
0234 enum rtw89_tssi_sbw_idx {
0235 RTW89_TSSI_SBW20,
0236 RTW89_TSSI_SBW40_0,
0237 RTW89_TSSI_SBW40_1,
0238 RTW89_TSSI_SBW80_0,
0239 RTW89_TSSI_SBW80_1,
0240 RTW89_TSSI_SBW80_2,
0241 RTW89_TSSI_SBW80_3,
0242 RTW89_TSSI_SBW160_0,
0243 RTW89_TSSI_SBW160_1,
0244 RTW89_TSSI_SBW160_2,
0245 RTW89_TSSI_SBW160_3,
0246 RTW89_TSSI_SBW160_4,
0247 RTW89_TSSI_SBW160_5,
0248 RTW89_TSSI_SBW160_6,
0249 RTW89_TSSI_SBW160_7,
0250
0251 RTW89_TSSI_SBW_NUM,
0252 };
0253
0254 struct rtw89_txpwr_byrate_cfg {
0255 enum rtw89_band band;
0256 enum rtw89_nss nss;
0257 enum rtw89_rate_section rs;
0258 u8 shf;
0259 u8 len;
0260 u32 data;
0261 };
0262
0263 #define DELTA_SWINGIDX_SIZE 30
0264
0265 struct rtw89_txpwr_track_cfg {
0266 const s8 (*delta_swingidx_6gb_n)[DELTA_SWINGIDX_SIZE];
0267 const s8 (*delta_swingidx_6gb_p)[DELTA_SWINGIDX_SIZE];
0268 const s8 (*delta_swingidx_6ga_n)[DELTA_SWINGIDX_SIZE];
0269 const s8 (*delta_swingidx_6ga_p)[DELTA_SWINGIDX_SIZE];
0270 const s8 (*delta_swingidx_5gb_n)[DELTA_SWINGIDX_SIZE];
0271 const s8 (*delta_swingidx_5gb_p)[DELTA_SWINGIDX_SIZE];
0272 const s8 (*delta_swingidx_5ga_n)[DELTA_SWINGIDX_SIZE];
0273 const s8 (*delta_swingidx_5ga_p)[DELTA_SWINGIDX_SIZE];
0274 const s8 *delta_swingidx_2gb_n;
0275 const s8 *delta_swingidx_2gb_p;
0276 const s8 *delta_swingidx_2ga_n;
0277 const s8 *delta_swingidx_2ga_p;
0278 const s8 *delta_swingidx_2g_cck_b_n;
0279 const s8 *delta_swingidx_2g_cck_b_p;
0280 const s8 *delta_swingidx_2g_cck_a_n;
0281 const s8 *delta_swingidx_2g_cck_a_p;
0282 };
0283
0284 struct rtw89_phy_dig_gain_cfg {
0285 const struct rtw89_reg_def *table;
0286 u8 size;
0287 };
0288
0289 struct rtw89_phy_dig_gain_table {
0290 const struct rtw89_phy_dig_gain_cfg *cfg_lna_g;
0291 const struct rtw89_phy_dig_gain_cfg *cfg_tia_g;
0292 const struct rtw89_phy_dig_gain_cfg *cfg_lna_a;
0293 const struct rtw89_phy_dig_gain_cfg *cfg_tia_a;
0294 };
0295
0296 struct rtw89_phy_tssi_dbw_table {
0297 u32 data[RTW89_TSSI_CFG_NUM][RTW89_TSSI_SBW_NUM];
0298 };
0299
0300 struct rtw89_phy_reg3_tbl {
0301 const struct rtw89_reg3_def *reg3;
0302 int size;
0303 };
0304
0305 #define DECLARE_PHY_REG3_TBL(_name) \
0306 const struct rtw89_phy_reg3_tbl _name ## _tbl = { \
0307 .reg3 = _name, \
0308 .size = ARRAY_SIZE(_name), \
0309 }
0310
0311 struct rtw89_nbi_reg_def {
0312 struct rtw89_reg_def notch1_idx;
0313 struct rtw89_reg_def notch1_frac_idx;
0314 struct rtw89_reg_def notch1_en;
0315 struct rtw89_reg_def notch2_idx;
0316 struct rtw89_reg_def notch2_frac_idx;
0317 struct rtw89_reg_def notch2_en;
0318 };
0319
0320 extern const u8 rtw89_rs_idx_max[RTW89_RS_MAX];
0321 extern const u8 rtw89_rs_nss_max[RTW89_RS_MAX];
0322
0323 static inline void rtw89_phy_write8(struct rtw89_dev *rtwdev,
0324 u32 addr, u8 data)
0325 {
0326 rtw89_write8(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, data);
0327 }
0328
0329 static inline void rtw89_phy_write16(struct rtw89_dev *rtwdev,
0330 u32 addr, u16 data)
0331 {
0332 rtw89_write16(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, data);
0333 }
0334
0335 static inline void rtw89_phy_write32(struct rtw89_dev *rtwdev,
0336 u32 addr, u32 data)
0337 {
0338 rtw89_write32(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, data);
0339 }
0340
0341 static inline void rtw89_phy_write32_set(struct rtw89_dev *rtwdev,
0342 u32 addr, u32 bits)
0343 {
0344 rtw89_write32_set(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, bits);
0345 }
0346
0347 static inline void rtw89_phy_write32_clr(struct rtw89_dev *rtwdev,
0348 u32 addr, u32 bits)
0349 {
0350 rtw89_write32_clr(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, bits);
0351 }
0352
0353 static inline void rtw89_phy_write32_mask(struct rtw89_dev *rtwdev,
0354 u32 addr, u32 mask, u32 data)
0355 {
0356 rtw89_write32_mask(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, mask, data);
0357 }
0358
0359 static inline u8 rtw89_phy_read8(struct rtw89_dev *rtwdev, u32 addr)
0360 {
0361 return rtw89_read8(rtwdev, addr | RTW89_PHY_ADDR_OFFSET);
0362 }
0363
0364 static inline u16 rtw89_phy_read16(struct rtw89_dev *rtwdev, u32 addr)
0365 {
0366 return rtw89_read16(rtwdev, addr | RTW89_PHY_ADDR_OFFSET);
0367 }
0368
0369 static inline u32 rtw89_phy_read32(struct rtw89_dev *rtwdev, u32 addr)
0370 {
0371 return rtw89_read32(rtwdev, addr | RTW89_PHY_ADDR_OFFSET);
0372 }
0373
0374 static inline u32 rtw89_phy_read32_mask(struct rtw89_dev *rtwdev,
0375 u32 addr, u32 mask)
0376 {
0377 return rtw89_read32_mask(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, mask);
0378 }
0379
0380 enum rtw89_rfk_flag {
0381 RTW89_RFK_F_WRF = 0,
0382 RTW89_RFK_F_WM = 1,
0383 RTW89_RFK_F_WS = 2,
0384 RTW89_RFK_F_WC = 3,
0385 RTW89_RFK_F_DELAY = 4,
0386 RTW89_RFK_F_NUM,
0387 };
0388
0389 struct rtw89_rfk_tbl {
0390 const struct rtw89_reg5_def *defs;
0391 u32 size;
0392 };
0393
0394 #define RTW89_DECLARE_RFK_TBL(_name) \
0395 const struct rtw89_rfk_tbl _name ## _tbl = { \
0396 .defs = _name, \
0397 .size = ARRAY_SIZE(_name), \
0398 }
0399
0400 #define RTW89_DECL_RFK_WRF(_path, _addr, _mask, _data) \
0401 {.flag = RTW89_RFK_F_WRF, \
0402 .path = _path, \
0403 .addr = _addr, \
0404 .mask = _mask, \
0405 .data = _data,}
0406
0407 #define RTW89_DECL_RFK_WM(_addr, _mask, _data) \
0408 {.flag = RTW89_RFK_F_WM, \
0409 .addr = _addr, \
0410 .mask = _mask, \
0411 .data = _data,}
0412
0413 #define RTW89_DECL_RFK_WS(_addr, _mask) \
0414 {.flag = RTW89_RFK_F_WS, \
0415 .addr = _addr, \
0416 .mask = _mask,}
0417
0418 #define RTW89_DECL_RFK_WC(_addr, _mask) \
0419 {.flag = RTW89_RFK_F_WC, \
0420 .addr = _addr, \
0421 .mask = _mask,}
0422
0423 #define RTW89_DECL_RFK_DELAY(_data) \
0424 {.flag = RTW89_RFK_F_DELAY, \
0425 .data = _data,}
0426
0427 void
0428 rtw89_rfk_parser(struct rtw89_dev *rtwdev, const struct rtw89_rfk_tbl *tbl);
0429
0430 #define rtw89_rfk_parser_by_cond(dev, cond, tbl_t, tbl_f) \
0431 do { \
0432 typeof(dev) __dev = (dev); \
0433 if (cond) \
0434 rtw89_rfk_parser(__dev, (tbl_t)); \
0435 else \
0436 rtw89_rfk_parser(__dev, (tbl_f)); \
0437 } while (0)
0438
0439 void rtw89_phy_write_reg3_tbl(struct rtw89_dev *rtwdev,
0440 const struct rtw89_phy_reg3_tbl *tbl);
0441 u8 rtw89_phy_get_txsc(struct rtw89_dev *rtwdev,
0442 struct rtw89_channel_params *param,
0443 enum rtw89_bandwidth dbw);
0444 u32 rtw89_phy_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
0445 u32 addr, u32 mask);
0446 u32 rtw89_phy_read_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
0447 u32 addr, u32 mask);
0448 bool rtw89_phy_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
0449 u32 addr, u32 mask, u32 data);
0450 bool rtw89_phy_write_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
0451 u32 addr, u32 mask, u32 data);
0452 void rtw89_phy_init_bb_reg(struct rtw89_dev *rtwdev);
0453 void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev);
0454 void rtw89_phy_config_rf_reg_v1(struct rtw89_dev *rtwdev,
0455 const struct rtw89_reg2_def *reg,
0456 enum rtw89_rf_path rf_path,
0457 void *extra_data);
0458 void rtw89_phy_dm_init(struct rtw89_dev *rtwdev);
0459 void rtw89_phy_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
0460 u32 data, enum rtw89_phy_idx phy_idx);
0461 void rtw89_phy_load_txpwr_byrate(struct rtw89_dev *rtwdev,
0462 const struct rtw89_txpwr_table *tbl);
0463 s8 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev,
0464 const struct rtw89_rate_desc *rate_desc);
0465 void rtw89_phy_fill_txpwr_limit(struct rtw89_dev *rtwdev,
0466 struct rtw89_txpwr_limit *lmt,
0467 u8 ntx);
0468 void rtw89_phy_fill_txpwr_limit_ru(struct rtw89_dev *rtwdev,
0469 struct rtw89_txpwr_limit_ru *lmt_ru,
0470 u8 ntx);
0471 s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev,
0472 u8 bw, u8 ntx, u8 rs, u8 bf, u8 ch);
0473 void rtw89_phy_ra_assoc(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta);
0474 void rtw89_phy_ra_update(struct rtw89_dev *rtwdev);
0475 void rtw89_phy_ra_updata_sta(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta,
0476 u32 changed);
0477 void rtw89_phy_rate_pattern_vif(struct rtw89_dev *rtwdev,
0478 struct ieee80211_vif *vif,
0479 const struct cfg80211_bitrate_mask *mask);
0480 void rtw89_phy_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb,
0481 u32 len, u8 class, u8 func);
0482 void rtw89_phy_cfo_track(struct rtw89_dev *rtwdev);
0483 void rtw89_phy_cfo_track_work(struct work_struct *work);
0484 void rtw89_phy_cfo_parse(struct rtw89_dev *rtwdev, s16 cfo_val,
0485 struct rtw89_rx_phy_ppdu *phy_ppdu);
0486 void rtw89_phy_stat_track(struct rtw89_dev *rtwdev);
0487 void rtw89_phy_env_monitor_track(struct rtw89_dev *rtwdev);
0488 void rtw89_phy_set_phy_regs(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
0489 u32 val);
0490 void rtw89_phy_dig_reset(struct rtw89_dev *rtwdev);
0491 void rtw89_phy_dig(struct rtw89_dev *rtwdev);
0492 void rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif);
0493 void rtw89_phy_tssi_ctrl_set_bandedge_cfg(struct rtw89_dev *rtwdev,
0494 enum rtw89_mac_idx mac_idx,
0495 enum rtw89_tssi_bandedge_cfg bandedge_cfg);
0496
0497 #endif
