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0005 #ifndef __RTW89_MAC_H__
0006 #define __RTW89_MAC_H__
0007
0008 #include "core.h"
0009
0010 #define MAC_MEM_DUMP_PAGE_SIZE 0x40000
0011 #define ADDR_CAM_ENT_SIZE 0x40
0012 #define BSSID_CAM_ENT_SIZE 0x08
0013 #define HFC_PAGE_UNIT 64
0014
0015 enum rtw89_mac_hwmod_sel {
0016 RTW89_DMAC_SEL = 0,
0017 RTW89_CMAC_SEL = 1,
0018
0019 RTW89_MAC_INVALID,
0020 };
0021
0022 enum rtw89_mac_fwd_target {
0023 RTW89_FWD_DONT_CARE = 0,
0024 RTW89_FWD_TO_HOST = 1,
0025 RTW89_FWD_TO_WLAN_CPU = 2
0026 };
0027
0028 enum rtw89_mac_wd_dma_intvl {
0029 RTW89_MAC_WD_DMA_INTVL_0S,
0030 RTW89_MAC_WD_DMA_INTVL_256NS,
0031 RTW89_MAC_WD_DMA_INTVL_512NS,
0032 RTW89_MAC_WD_DMA_INTVL_768NS,
0033 RTW89_MAC_WD_DMA_INTVL_1US,
0034 RTW89_MAC_WD_DMA_INTVL_1_5US,
0035 RTW89_MAC_WD_DMA_INTVL_2US,
0036 RTW89_MAC_WD_DMA_INTVL_4US,
0037 RTW89_MAC_WD_DMA_INTVL_8US,
0038 RTW89_MAC_WD_DMA_INTVL_16US,
0039 RTW89_MAC_WD_DMA_INTVL_DEF = 0xFE
0040 };
0041
0042 enum rtw89_mac_multi_tag_num {
0043 RTW89_MAC_TAG_NUM_1,
0044 RTW89_MAC_TAG_NUM_2,
0045 RTW89_MAC_TAG_NUM_3,
0046 RTW89_MAC_TAG_NUM_4,
0047 RTW89_MAC_TAG_NUM_5,
0048 RTW89_MAC_TAG_NUM_6,
0049 RTW89_MAC_TAG_NUM_7,
0050 RTW89_MAC_TAG_NUM_8,
0051 RTW89_MAC_TAG_NUM_DEF = 0xFE
0052 };
0053
0054 enum rtw89_mac_lbc_tmr {
0055 RTW89_MAC_LBC_TMR_8US = 0,
0056 RTW89_MAC_LBC_TMR_16US,
0057 RTW89_MAC_LBC_TMR_32US,
0058 RTW89_MAC_LBC_TMR_64US,
0059 RTW89_MAC_LBC_TMR_128US,
0060 RTW89_MAC_LBC_TMR_256US,
0061 RTW89_MAC_LBC_TMR_512US,
0062 RTW89_MAC_LBC_TMR_1MS,
0063 RTW89_MAC_LBC_TMR_2MS,
0064 RTW89_MAC_LBC_TMR_4MS,
0065 RTW89_MAC_LBC_TMR_8MS,
0066 RTW89_MAC_LBC_TMR_DEF = 0xFE
0067 };
0068
0069 enum rtw89_mac_cpuio_op_cmd_type {
0070 CPUIO_OP_CMD_GET_1ST_PID = 0,
0071 CPUIO_OP_CMD_GET_NEXT_PID = 1,
0072 CPUIO_OP_CMD_ENQ_TO_TAIL = 4,
0073 CPUIO_OP_CMD_ENQ_TO_HEAD = 5,
0074 CPUIO_OP_CMD_DEQ = 8,
0075 CPUIO_OP_CMD_DEQ_ENQ_ALL = 9,
0076 CPUIO_OP_CMD_DEQ_ENQ_TO_TAIL = 12
0077 };
0078
0079 enum rtw89_mac_wde_dle_port_id {
0080 WDE_DLE_PORT_ID_DISPATCH = 0,
0081 WDE_DLE_PORT_ID_PKTIN = 1,
0082 WDE_DLE_PORT_ID_CMAC0 = 3,
0083 WDE_DLE_PORT_ID_CMAC1 = 4,
0084 WDE_DLE_PORT_ID_CPU_IO = 6,
0085 WDE_DLE_PORT_ID_WDRLS = 7,
0086 WDE_DLE_PORT_ID_END = 8
0087 };
0088
0089 enum rtw89_mac_wde_dle_queid_wdrls {
0090 WDE_DLE_QUEID_TXOK = 0,
0091 WDE_DLE_QUEID_DROP_RETRY_LIMIT = 1,
0092 WDE_DLE_QUEID_DROP_LIFETIME_TO = 2,
0093 WDE_DLE_QUEID_DROP_MACID_DROP = 3,
0094 WDE_DLE_QUEID_NO_REPORT = 4
0095 };
0096
0097 enum rtw89_mac_ple_dle_port_id {
0098 PLE_DLE_PORT_ID_DISPATCH = 0,
0099 PLE_DLE_PORT_ID_MPDU = 1,
0100 PLE_DLE_PORT_ID_SEC = 2,
0101 PLE_DLE_PORT_ID_CMAC0 = 3,
0102 PLE_DLE_PORT_ID_CMAC1 = 4,
0103 PLE_DLE_PORT_ID_WDRLS = 5,
0104 PLE_DLE_PORT_ID_CPU_IO = 6,
0105 PLE_DLE_PORT_ID_PLRLS = 7,
0106 PLE_DLE_PORT_ID_END = 8
0107 };
0108
0109 enum rtw89_mac_ple_dle_queid_plrls {
0110 PLE_DLE_QUEID_NO_REPORT = 0x0
0111 };
0112
0113 enum rtw89_machdr_frame_type {
0114 RTW89_MGNT = 0,
0115 RTW89_CTRL = 1,
0116 RTW89_DATA = 2,
0117 };
0118
0119 enum rtw89_mac_dle_dfi_type {
0120 DLE_DFI_TYPE_FREEPG = 0,
0121 DLE_DFI_TYPE_QUOTA = 1,
0122 DLE_DFI_TYPE_PAGELLT = 2,
0123 DLE_DFI_TYPE_PKTINFO = 3,
0124 DLE_DFI_TYPE_PREPKTLLT = 4,
0125 DLE_DFI_TYPE_NXTPKTLLT = 5,
0126 DLE_DFI_TYPE_QLNKTBL = 6,
0127 DLE_DFI_TYPE_QEMPTY = 7,
0128 };
0129
0130 enum rtw89_mac_dle_wde_quota_id {
0131 WDE_QTAID_HOST_IF = 0,
0132 WDE_QTAID_WLAN_CPU = 1,
0133 WDE_QTAID_DATA_CPU = 2,
0134 WDE_QTAID_PKTIN = 3,
0135 WDE_QTAID_CPUIO = 4,
0136 };
0137
0138 enum rtw89_mac_dle_ple_quota_id {
0139 PLE_QTAID_B0_TXPL = 0,
0140 PLE_QTAID_B1_TXPL = 1,
0141 PLE_QTAID_C2H = 2,
0142 PLE_QTAID_H2C = 3,
0143 PLE_QTAID_WLAN_CPU = 4,
0144 PLE_QTAID_MPDU = 5,
0145 PLE_QTAID_CMAC0_RX = 6,
0146 PLE_QTAID_CMAC1_RX = 7,
0147 PLE_QTAID_CMAC1_BBRPT = 8,
0148 PLE_QTAID_WDRLS = 9,
0149 PLE_QTAID_CPUIO = 10,
0150 };
0151
0152 enum rtw89_mac_dle_ctrl_type {
0153 DLE_CTRL_TYPE_WDE = 0,
0154 DLE_CTRL_TYPE_PLE = 1,
0155 DLE_CTRL_TYPE_NUM = 2,
0156 };
0157
0158 enum rtw89_mac_ax_l0_to_l1_event {
0159 MAC_AX_L0_TO_L1_CHIF_IDLE = 0,
0160 MAC_AX_L0_TO_L1_CMAC_DMA_IDLE = 1,
0161 MAC_AX_L0_TO_L1_RLS_PKID = 2,
0162 MAC_AX_L0_TO_L1_PTCL_IDLE = 3,
0163 MAC_AX_L0_TO_L1_RX_QTA_LOST = 4,
0164 MAC_AX_L0_TO_L1_DLE_STAT_HANG = 5,
0165 MAC_AX_L0_TO_L1_PCIE_STUCK = 6,
0166 MAC_AX_L0_TO_L1_EVENT_MAX = 15,
0167 };
0168
0169 enum rtw89_mac_dbg_port_sel {
0170
0171 RTW89_DBG_PORT_SEL_PTCL_C0 = 0,
0172 RTW89_DBG_PORT_SEL_SCH_C0,
0173 RTW89_DBG_PORT_SEL_TMAC_C0,
0174 RTW89_DBG_PORT_SEL_RMAC_C0,
0175 RTW89_DBG_PORT_SEL_RMACST_C0,
0176 RTW89_DBG_PORT_SEL_RMAC_PLCP_C0,
0177 RTW89_DBG_PORT_SEL_TRXPTCL_C0,
0178 RTW89_DBG_PORT_SEL_TX_INFOL_C0,
0179 RTW89_DBG_PORT_SEL_TX_INFOH_C0,
0180 RTW89_DBG_PORT_SEL_TXTF_INFOL_C0,
0181 RTW89_DBG_PORT_SEL_TXTF_INFOH_C0,
0182
0183 RTW89_DBG_PORT_SEL_PTCL_C1,
0184 RTW89_DBG_PORT_SEL_SCH_C1,
0185 RTW89_DBG_PORT_SEL_TMAC_C1,
0186 RTW89_DBG_PORT_SEL_RMAC_C1,
0187 RTW89_DBG_PORT_SEL_RMACST_C1,
0188 RTW89_DBG_PORT_SEL_RMAC_PLCP_C1,
0189 RTW89_DBG_PORT_SEL_TRXPTCL_C1,
0190 RTW89_DBG_PORT_SEL_TX_INFOL_C1,
0191 RTW89_DBG_PORT_SEL_TX_INFOH_C1,
0192 RTW89_DBG_PORT_SEL_TXTF_INFOL_C1,
0193 RTW89_DBG_PORT_SEL_TXTF_INFOH_C1,
0194
0195 RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG,
0196 RTW89_DBG_PORT_SEL_WDE_BUFMGN_QUOTA,
0197 RTW89_DBG_PORT_SEL_WDE_BUFMGN_PAGELLT,
0198 RTW89_DBG_PORT_SEL_WDE_BUFMGN_PKTINFO,
0199 RTW89_DBG_PORT_SEL_WDE_QUEMGN_PREPKT,
0200 RTW89_DBG_PORT_SEL_WDE_QUEMGN_NXTPKT,
0201 RTW89_DBG_PORT_SEL_WDE_QUEMGN_QLNKTBL,
0202 RTW89_DBG_PORT_SEL_WDE_QUEMGN_QEMPTY,
0203 RTW89_DBG_PORT_SEL_PLE_BUFMGN_FREEPG,
0204 RTW89_DBG_PORT_SEL_PLE_BUFMGN_QUOTA,
0205 RTW89_DBG_PORT_SEL_PLE_BUFMGN_PAGELLT,
0206 RTW89_DBG_PORT_SEL_PLE_BUFMGN_PKTINFO,
0207 RTW89_DBG_PORT_SEL_PLE_QUEMGN_PREPKT,
0208 RTW89_DBG_PORT_SEL_PLE_QUEMGN_NXTPKT,
0209 RTW89_DBG_PORT_SEL_PLE_QUEMGN_QLNKTBL,
0210 RTW89_DBG_PORT_SEL_PLE_QUEMGN_QEMPTY,
0211 RTW89_DBG_PORT_SEL_PKTINFO,
0212
0213 RTW89_DBG_PORT_SEL_PCIE_TXDMA,
0214 RTW89_DBG_PORT_SEL_PCIE_RXDMA,
0215 RTW89_DBG_PORT_SEL_PCIE_CVT,
0216 RTW89_DBG_PORT_SEL_PCIE_CXPL,
0217 RTW89_DBG_PORT_SEL_PCIE_IO,
0218 RTW89_DBG_PORT_SEL_PCIE_MISC,
0219 RTW89_DBG_PORT_SEL_PCIE_MISC2,
0220
0221
0222 RTW89_DBG_PORT_SEL_LAST,
0223 RTW89_DBG_PORT_SEL_MAX = RTW89_DBG_PORT_SEL_LAST,
0224 RTW89_DBG_PORT_SEL_INVALID = RTW89_DBG_PORT_SEL_LAST,
0225 };
0226
0227
0228 #define R_AX_INDIR_ACCESS_ENTRY 0x40000
0229
0230 #define AXIDMA_BASE_ADDR 0x18006000
0231 #define STA_SCHED_BASE_ADDR 0x18808000
0232 #define RXPLD_FLTR_CAM_BASE_ADDR 0x18813000
0233 #define SECURITY_CAM_BASE_ADDR 0x18814000
0234 #define WOW_CAM_BASE_ADDR 0x18815000
0235 #define CMAC_TBL_BASE_ADDR 0x18840000
0236 #define ADDR_CAM_BASE_ADDR 0x18850000
0237 #define BSSID_CAM_BASE_ADDR 0x18853000
0238 #define BA_CAM_BASE_ADDR 0x18854000
0239 #define BCN_IE_CAM0_BASE_ADDR 0x18855000
0240 #define SHARED_BUF_BASE_ADDR 0x18700000
0241 #define DMAC_TBL_BASE_ADDR 0x18800000
0242 #define SHCUT_MACHDR_BASE_ADDR 0x18800800
0243 #define BCN_IE_CAM1_BASE_ADDR 0x188A0000
0244 #define TXD_FIFO_0_BASE_ADDR 0x18856200
0245 #define TXD_FIFO_1_BASE_ADDR 0x188A1080
0246 #define TXDATA_FIFO_0_BASE_ADDR 0x18856000
0247 #define TXDATA_FIFO_1_BASE_ADDR 0x188A1000
0248 #define CPU_LOCAL_BASE_ADDR 0x18003000
0249
0250 #define CCTL_INFO_SIZE 32
0251
0252 enum rtw89_mac_mem_sel {
0253 RTW89_MAC_MEM_AXIDMA,
0254 RTW89_MAC_MEM_SHARED_BUF,
0255 RTW89_MAC_MEM_DMAC_TBL,
0256 RTW89_MAC_MEM_SHCUT_MACHDR,
0257 RTW89_MAC_MEM_STA_SCHED,
0258 RTW89_MAC_MEM_RXPLD_FLTR_CAM,
0259 RTW89_MAC_MEM_SECURITY_CAM,
0260 RTW89_MAC_MEM_WOW_CAM,
0261 RTW89_MAC_MEM_CMAC_TBL,
0262 RTW89_MAC_MEM_ADDR_CAM,
0263 RTW89_MAC_MEM_BA_CAM,
0264 RTW89_MAC_MEM_BCN_IE_CAM0,
0265 RTW89_MAC_MEM_BCN_IE_CAM1,
0266 RTW89_MAC_MEM_TXD_FIFO_0,
0267 RTW89_MAC_MEM_TXD_FIFO_1,
0268 RTW89_MAC_MEM_TXDATA_FIFO_0,
0269 RTW89_MAC_MEM_TXDATA_FIFO_1,
0270 RTW89_MAC_MEM_CPU_LOCAL,
0271 RTW89_MAC_MEM_BSSID_CAM,
0272
0273
0274 RTW89_MAC_MEM_NUM,
0275 };
0276
0277 extern const u32 rtw89_mac_mem_base_addrs[];
0278
0279 enum rtw89_rpwm_req_pwr_state {
0280 RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE = 0,
0281 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFON = 1,
0282 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND1_RFON = 2,
0283 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFOFF = 3,
0284 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND1_RFOFF = 4,
0285 RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED = 5,
0286 RTW89_MAC_RPWM_REQ_PWR_STATE_PWR_GATED = 6,
0287 RTW89_MAC_RPWM_REQ_PWR_STATE_HIOE_PWR_GATED = 7,
0288 RTW89_MAC_RPWM_REQ_PWR_STATE_MAX,
0289 };
0290
0291 struct rtw89_pwr_cfg {
0292 u16 addr;
0293 u8 cv_msk;
0294 u8 intf_msk;
0295 u8 base:4;
0296 u8 cmd:4;
0297 u8 msk;
0298 u8 val;
0299 };
0300
0301 enum rtw89_mac_c2h_ofld_func {
0302 RTW89_MAC_C2H_FUNC_EFUSE_DUMP,
0303 RTW89_MAC_C2H_FUNC_READ_RSP,
0304 RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP,
0305 RTW89_MAC_C2H_FUNC_BCN_RESEND,
0306 RTW89_MAC_C2H_FUNC_MACID_PAUSE,
0307 RTW89_MAC_C2H_FUNC_SCANOFLD_RSP = 0x9,
0308 RTW89_MAC_C2H_FUNC_OFLD_MAX,
0309 };
0310
0311 enum rtw89_mac_c2h_info_func {
0312 RTW89_MAC_C2H_FUNC_REC_ACK,
0313 RTW89_MAC_C2H_FUNC_DONE_ACK,
0314 RTW89_MAC_C2H_FUNC_C2H_LOG,
0315 RTW89_MAC_C2H_FUNC_BCN_CNT,
0316 RTW89_MAC_C2H_FUNC_INFO_MAX,
0317 };
0318
0319 enum rtw89_mac_c2h_class {
0320 RTW89_MAC_C2H_CLASS_INFO,
0321 RTW89_MAC_C2H_CLASS_OFLD,
0322 RTW89_MAC_C2H_CLASS_TWT,
0323 RTW89_MAC_C2H_CLASS_WOW,
0324 RTW89_MAC_C2H_CLASS_MCC,
0325 RTW89_MAC_C2H_CLASS_FWDBG,
0326 RTW89_MAC_C2H_CLASS_MAX,
0327 };
0328
0329 struct rtw89_mac_ax_coex {
0330 #define RTW89_MAC_AX_COEX_RTK_MODE 0
0331 #define RTW89_MAC_AX_COEX_CSR_MODE 1
0332 u8 pta_mode;
0333 #define RTW89_MAC_AX_COEX_INNER 0
0334 #define RTW89_MAC_AX_COEX_OUTPUT 1
0335 #define RTW89_MAC_AX_COEX_INPUT 2
0336 u8 direction;
0337 };
0338
0339 struct rtw89_mac_ax_plt {
0340 #define RTW89_MAC_AX_PLT_LTE_RX BIT(0)
0341 #define RTW89_MAC_AX_PLT_GNT_BT_TX BIT(1)
0342 #define RTW89_MAC_AX_PLT_GNT_BT_RX BIT(2)
0343 #define RTW89_MAC_AX_PLT_GNT_WL BIT(3)
0344 u8 band;
0345 u8 tx;
0346 u8 rx;
0347 };
0348
0349 enum rtw89_mac_bf_rrsc_rate {
0350 RTW89_MAC_BF_RRSC_6M = 0,
0351 RTW89_MAC_BF_RRSC_9M = 1,
0352 RTW89_MAC_BF_RRSC_12M,
0353 RTW89_MAC_BF_RRSC_18M,
0354 RTW89_MAC_BF_RRSC_24M,
0355 RTW89_MAC_BF_RRSC_36M,
0356 RTW89_MAC_BF_RRSC_48M,
0357 RTW89_MAC_BF_RRSC_54M,
0358 RTW89_MAC_BF_RRSC_HT_MSC0,
0359 RTW89_MAC_BF_RRSC_HT_MSC1,
0360 RTW89_MAC_BF_RRSC_HT_MSC2,
0361 RTW89_MAC_BF_RRSC_HT_MSC3,
0362 RTW89_MAC_BF_RRSC_HT_MSC4,
0363 RTW89_MAC_BF_RRSC_HT_MSC5,
0364 RTW89_MAC_BF_RRSC_HT_MSC6,
0365 RTW89_MAC_BF_RRSC_HT_MSC7,
0366 RTW89_MAC_BF_RRSC_VHT_MSC0,
0367 RTW89_MAC_BF_RRSC_VHT_MSC1,
0368 RTW89_MAC_BF_RRSC_VHT_MSC2,
0369 RTW89_MAC_BF_RRSC_VHT_MSC3,
0370 RTW89_MAC_BF_RRSC_VHT_MSC4,
0371 RTW89_MAC_BF_RRSC_VHT_MSC5,
0372 RTW89_MAC_BF_RRSC_VHT_MSC6,
0373 RTW89_MAC_BF_RRSC_VHT_MSC7,
0374 RTW89_MAC_BF_RRSC_HE_MSC0,
0375 RTW89_MAC_BF_RRSC_HE_MSC1,
0376 RTW89_MAC_BF_RRSC_HE_MSC2,
0377 RTW89_MAC_BF_RRSC_HE_MSC3,
0378 RTW89_MAC_BF_RRSC_HE_MSC4,
0379 RTW89_MAC_BF_RRSC_HE_MSC5,
0380 RTW89_MAC_BF_RRSC_HE_MSC6,
0381 RTW89_MAC_BF_RRSC_HE_MSC7 = 31,
0382 RTW89_MAC_BF_RRSC_MAX = 32
0383 };
0384
0385 #define RTW89_R32_EA 0xEAEAEAEA
0386 #define RTW89_R32_DEAD 0xDEADBEEF
0387 #define MAC_REG_POOL_COUNT 10
0388 #define ACCESS_CMAC(_addr) \
0389 ({typeof(_addr) __addr = (_addr); \
0390 __addr >= R_AX_CMAC_REG_START && __addr <= R_AX_CMAC_REG_END; })
0391
0392 #define PTCL_IDLE_POLL_CNT 10000
0393 #define SW_CVR_DUR_US 8
0394 #define SW_CVR_CNT 8
0395
0396 #define DLE_BOUND_UNIT (8 * 1024)
0397 #define DLE_WAIT_CNT 2000
0398 #define TRXCFG_WAIT_CNT 2000
0399
0400 #define RTW89_WDE_PG_64 64
0401 #define RTW89_WDE_PG_128 128
0402 #define RTW89_WDE_PG_256 256
0403
0404 #define S_AX_WDE_PAGE_SEL_64 0
0405 #define S_AX_WDE_PAGE_SEL_128 1
0406 #define S_AX_WDE_PAGE_SEL_256 2
0407
0408 #define RTW89_PLE_PG_64 64
0409 #define RTW89_PLE_PG_128 128
0410 #define RTW89_PLE_PG_256 256
0411
0412 #define S_AX_PLE_PAGE_SEL_64 0
0413 #define S_AX_PLE_PAGE_SEL_128 1
0414 #define S_AX_PLE_PAGE_SEL_256 2
0415
0416 #define SDIO_LOCAL_BASE_ADDR 0x80000000
0417
0418 #define PWR_CMD_WRITE 0
0419 #define PWR_CMD_POLL 1
0420 #define PWR_CMD_DELAY 2
0421 #define PWR_CMD_END 3
0422
0423 #define PWR_INTF_MSK_SDIO BIT(0)
0424 #define PWR_INTF_MSK_USB BIT(1)
0425 #define PWR_INTF_MSK_PCIE BIT(2)
0426 #define PWR_INTF_MSK_ALL 0x7
0427
0428 #define PWR_BASE_MAC 0
0429 #define PWR_BASE_USB 1
0430 #define PWR_BASE_PCIE 2
0431 #define PWR_BASE_SDIO 3
0432
0433 #define PWR_CV_MSK_A BIT(0)
0434 #define PWR_CV_MSK_B BIT(1)
0435 #define PWR_CV_MSK_C BIT(2)
0436 #define PWR_CV_MSK_D BIT(3)
0437 #define PWR_CV_MSK_E BIT(4)
0438 #define PWR_CV_MSK_F BIT(5)
0439 #define PWR_CV_MSK_G BIT(6)
0440 #define PWR_CV_MSK_TEST BIT(7)
0441 #define PWR_CV_MSK_ALL 0xFF
0442
0443 #define PWR_DELAY_US 0
0444 #define PWR_DELAY_MS 1
0445
0446
0447 #define SS_MACID_SH 8
0448 #define SS_TX_LEN_MSK 0x1FFFFF
0449 #define SS_CTRL1_R_TX_LEN 5
0450 #define SS_CTRL1_R_NEXT_LINK 20
0451 #define SS_LINK_SIZE 256
0452
0453
0454 #define TMAC_DBG_SEL_C0 0xA5
0455 #define RMAC_DBG_SEL_C0 0xA6
0456 #define TRXPTCL_DBG_SEL_C0 0xA7
0457 #define TMAC_DBG_SEL_C1 0xB5
0458 #define RMAC_DBG_SEL_C1 0xB6
0459 #define TRXPTCL_DBG_SEL_C1 0xB7
0460 #define FW_PROG_CNTR_DBG_SEL 0xF2
0461 #define PCIE_TXDMA_DBG_SEL 0x30
0462 #define PCIE_RXDMA_DBG_SEL 0x31
0463 #define PCIE_CVT_DBG_SEL 0x32
0464 #define PCIE_CXPL_DBG_SEL 0x33
0465 #define PCIE_IO_DBG_SEL 0x37
0466 #define PCIE_MISC_DBG_SEL 0x38
0467 #define PCIE_MISC2_DBG_SEL 0x00
0468 #define MAC_DBG_SEL 1
0469 #define RMAC_CMAC_DBG_SEL 1
0470
0471
0472 #define TRXPTRL_DBG_SEL_TMAC 0
0473 #define TRXPTRL_DBG_SEL_RMAC 1
0474
0475 struct rtw89_cpuio_ctrl {
0476 u16 pkt_num;
0477 u16 start_pktid;
0478 u16 end_pktid;
0479 u8 cmd_type;
0480 u8 macid;
0481 u8 src_pid;
0482 u8 src_qid;
0483 u8 dst_pid;
0484 u8 dst_qid;
0485 u16 pktid;
0486 };
0487
0488 struct rtw89_mac_dbg_port_info {
0489 u32 sel_addr;
0490 u8 sel_byte;
0491 u32 sel_msk;
0492 u32 srt;
0493 u32 end;
0494 u32 rd_addr;
0495 u8 rd_byte;
0496 u32 rd_msk;
0497 };
0498
0499 #define QLNKTBL_ADDR_INFO_SEL BIT(0)
0500 #define QLNKTBL_ADDR_INFO_SEL_0 0
0501 #define QLNKTBL_ADDR_INFO_SEL_1 1
0502 #define QLNKTBL_ADDR_TBL_IDX_MASK GENMASK(10, 1)
0503 #define QLNKTBL_DATA_SEL1_PKT_CNT_MASK GENMASK(11, 0)
0504
0505 struct rtw89_mac_dle_dfi_ctrl {
0506 enum rtw89_mac_dle_ctrl_type type;
0507 u32 target;
0508 u32 addr;
0509 u32 out_data;
0510 };
0511
0512 struct rtw89_mac_dle_dfi_quota {
0513 enum rtw89_mac_dle_ctrl_type dle_type;
0514 u32 qtaid;
0515 u16 rsv_pgnum;
0516 u16 use_pgnum;
0517 };
0518
0519 struct rtw89_mac_dle_dfi_qempty {
0520 enum rtw89_mac_dle_ctrl_type dle_type;
0521 u32 grpsel;
0522 u32 qempty;
0523 };
0524
0525 enum rtw89_mac_error_scenario {
0526 RTW89_WCPU_CPU_EXCEPTION = 2,
0527 RTW89_WCPU_ASSERTION = 3,
0528 };
0529
0530 #define RTW89_ERROR_SCENARIO(__err) ((__err) >> 28)
0531
0532
0533 enum mac_ax_err_info {
0534
0535
0536
0537 MAC_AX_ERR_L0_ERR_CMAC0 = 0x0001,
0538 MAC_AX_ERR_L0_ERR_CMAC1 = 0x0002,
0539 MAC_AX_ERR_L0_RESET_DONE = 0x0003,
0540 MAC_AX_ERR_L0_PROMOTE_TO_L1 = 0x0010,
0541
0542
0543 MAC_AX_ERR_L1_ERR_DMAC = 0x1000,
0544 MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE = 0x1001,
0545 MAC_AX_ERR_L1_RESET_RECOVERY_DONE = 0x1002,
0546 MAC_AX_ERR_L1_PROMOTE_TO_L2 = 0x1010,
0547 MAC_AX_ERR_L1_RCVY_STOP_DONE = 0x1011,
0548
0549
0550
0551 MAC_AX_ERR_L2_ERR_AH_DMA = 0x2000,
0552 MAC_AX_ERR_L2_ERR_AH_HCI = 0x2010,
0553 MAC_AX_ERR_L2_ERR_AH_RLX4081 = 0x2020,
0554 MAC_AX_ERR_L2_ERR_AH_IDDMA = 0x2030,
0555 MAC_AX_ERR_L2_ERR_AH_HIOE = 0x2040,
0556 MAC_AX_ERR_L2_ERR_AH_IPSEC = 0x2050,
0557 MAC_AX_ERR_L2_ERR_AH_RX4281 = 0x2060,
0558 MAC_AX_ERR_L2_ERR_AH_OTHERS = 0x2070,
0559
0560
0561 MAC_AX_ERR_L2_ERR_AHB_TO_DMA = 0x2100,
0562 MAC_AX_ERR_L2_ERR_AHB_TO_HCI = 0x2110,
0563 MAC_AX_ERR_L2_ERR_AHB_TO_RLX4081 = 0x2120,
0564 MAC_AX_ERR_L2_ERR_AHB_TO_IDDMA = 0x2130,
0565 MAC_AX_ERR_L2_ERR_AHB_TO_HIOE = 0x2140,
0566 MAC_AX_ERR_L2_ERR_AHB_TO_IPSEC = 0x2150,
0567 MAC_AX_ERR_L2_ERR_AHB_TO_RX4281 = 0x2160,
0568 MAC_AX_ERR_L2_ERR_AHB_TO_OTHERS = 0x2170,
0569
0570
0571 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WVA = 0x2200,
0572 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_UART = 0x2201,
0573 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_CPULOCAL = 0x2202,
0574 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_AXIDMA = 0x2203,
0575 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_HIOE = 0x2204,
0576 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IDDMA = 0x2205,
0577 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IPSEC = 0x2206,
0578 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WON = 0x2207,
0579 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WDMAC = 0x2208,
0580 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WCMAC = 0x2209,
0581 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_OTHERS = 0x220A,
0582 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WVA = 0x2210,
0583 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_UART = 0x2211,
0584 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_CPULOCAL = 0x2212,
0585 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_AXIDMA = 0x2213,
0586 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_HIOE = 0x2214,
0587 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IDDMA = 0x2215,
0588 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IPSEC = 0x2216,
0589 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WDMAC = 0x2218,
0590 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WCMAC = 0x2219,
0591 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_OTHERS = 0x221A,
0592 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WVA = 0x2220,
0593 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_UART = 0x2221,
0594 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_CPULOCAL = 0x2222,
0595 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_AXIDMA = 0x2223,
0596 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_HIOE = 0x2224,
0597 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IDDMA = 0x2225,
0598 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IPSEC = 0x2226,
0599 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WON = 0x2227,
0600 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WDMAC = 0x2228,
0601 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WCMAC = 0x2229,
0602 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_OTHERS = 0x222A,
0603 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WVA = 0x2230,
0604 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_UART = 0x2231,
0605 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_CPULOCAL = 0x2232,
0606 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_AXIDMA = 0x2233,
0607 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_HIOE = 0x2234,
0608 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IDDMA = 0x2235,
0609 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IPSEC = 0x2236,
0610 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WON = 0x2237,
0611 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WDMAC = 0x2238,
0612 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WCMAC = 0x2239,
0613 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_OTHERS = 0x223A,
0614 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WVA = 0x2240,
0615 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_UART = 0x2241,
0616 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_CPULOCAL = 0x2242,
0617 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_AXIDMA = 0x2243,
0618 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_HIOE = 0x2244,
0619 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IDDMA = 0x2245,
0620 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IPSEC = 0x2246,
0621 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WON = 0x2247,
0622 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WDMAC = 0x2248,
0623 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WCMAC = 0x2249,
0624 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_OTHERS = 0x224A,
0625 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WVA = 0x2250,
0626 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_UART = 0x2251,
0627 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_CPULOCAL = 0x2252,
0628 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_AXIDMA = 0x2253,
0629 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_HIOE = 0x2254,
0630 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IDDMA = 0x2255,
0631 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IPSEC = 0x2256,
0632 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WON = 0x2257,
0633 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WDMAC = 0x2258,
0634 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WCMAC = 0x2259,
0635 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_OTHERS = 0x225A,
0636 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WVA = 0x2260,
0637 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_UART = 0x2261,
0638 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_CPULOCAL = 0x2262,
0639 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_AXIDMA = 0x2263,
0640 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_HIOE = 0x2264,
0641 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IDDMA = 0x2265,
0642 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IPSEC = 0x2266,
0643 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WON = 0x2267,
0644 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WDMAC = 0x2268,
0645 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WCMAC = 0x2269,
0646 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_OTHERS = 0x226A,
0647 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WVA = 0x2270,
0648 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_UART = 0x2271,
0649 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_CPULOCAL = 0x2272,
0650 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_AXIDMA = 0x2273,
0651 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_HIOE = 0x2274,
0652 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IDDMA = 0x2275,
0653 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IPSEC = 0x2276,
0654 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WON = 0x2277,
0655 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WDMAC = 0x2278,
0656 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WCMAC = 0x2279,
0657 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_OTHERS = 0x227A,
0658
0659
0660 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_DMA = 0x2300,
0661 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HCI = 0x2310,
0662 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RLX4081 = 0x2320,
0663 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IDDMA = 0x2330,
0664 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HIOE = 0x2340,
0665 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IPSEC = 0x2350,
0666 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RX4281 = 0x2360,
0667 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_OTHERS = 0x2370,
0668 MAC_AX_ERR_L2_RESET_DONE = 0x2400,
0669 MAC_AX_ERR_L2_ERR_WDT_TIMEOUT_INT = 0x2599,
0670 MAC_AX_ERR_CPU_EXCEPTION = 0x3000,
0671 MAC_AX_ERR_ASSERTION = 0x4000,
0672 MAC_AX_GET_ERR_MAX,
0673 MAC_AX_DUMP_SHAREBUFF_INDICATOR = 0x80000000,
0674
0675
0676 MAC_AX_ERR_L1_DISABLE_EN = 0x0001,
0677 MAC_AX_ERR_L1_RCVY_EN = 0x0002,
0678 MAC_AX_ERR_L1_RCVY_STOP_REQ = 0x0003,
0679 MAC_AX_ERR_L1_RCVY_START_REQ = 0x0004,
0680 MAC_AX_ERR_L0_CFG_NOTIFY = 0x0010,
0681 MAC_AX_ERR_L0_CFG_DIS_NOTIFY = 0x0011,
0682 MAC_AX_ERR_L0_CFG_HANDSHAKE = 0x0012,
0683 MAC_AX_ERR_L0_RCVY_EN = 0x0013,
0684 MAC_AX_SET_ERR_MAX,
0685 };
0686
0687 struct rtw89_mac_size_set {
0688 const struct rtw89_hfc_prec_cfg hfc_preccfg_pcie;
0689 const struct rtw89_dle_size wde_size0;
0690 const struct rtw89_dle_size wde_size4;
0691 const struct rtw89_dle_size wde_size18;
0692 const struct rtw89_dle_size wde_size19;
0693 const struct rtw89_dle_size ple_size0;
0694 const struct rtw89_dle_size ple_size4;
0695 const struct rtw89_dle_size ple_size18;
0696 const struct rtw89_dle_size ple_size19;
0697 const struct rtw89_wde_quota wde_qt0;
0698 const struct rtw89_wde_quota wde_qt4;
0699 const struct rtw89_wde_quota wde_qt17;
0700 const struct rtw89_wde_quota wde_qt18;
0701 const struct rtw89_ple_quota ple_qt4;
0702 const struct rtw89_ple_quota ple_qt5;
0703 const struct rtw89_ple_quota ple_qt13;
0704 const struct rtw89_ple_quota ple_qt44;
0705 const struct rtw89_ple_quota ple_qt45;
0706 const struct rtw89_ple_quota ple_qt46;
0707 const struct rtw89_ple_quota ple_qt47;
0708 };
0709
0710 extern const struct rtw89_mac_size_set rtw89_mac_size;
0711
0712 static inline u32 rtw89_mac_reg_by_idx(u32 reg_base, u8 band)
0713 {
0714 return band == 0 ? reg_base : (reg_base + 0x2000);
0715 }
0716
0717 static inline u32 rtw89_mac_reg_by_port(u32 base, u8 port, u8 mac_idx)
0718 {
0719 return rtw89_mac_reg_by_idx(base + port * 0x40, mac_idx);
0720 }
0721
0722 static inline u32
0723 rtw89_read32_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
0724 u32 base, u32 mask)
0725 {
0726 u32 reg;
0727
0728 reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx);
0729 return rtw89_read32_mask(rtwdev, reg, mask);
0730 }
0731
0732 static inline void
0733 rtw89_write32_port(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, u32 base,
0734 u32 data)
0735 {
0736 u32 reg;
0737
0738 reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx);
0739 rtw89_write32(rtwdev, reg, data);
0740 }
0741
0742 static inline void
0743 rtw89_write32_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
0744 u32 base, u32 mask, u32 data)
0745 {
0746 u32 reg;
0747
0748 reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx);
0749 rtw89_write32_mask(rtwdev, reg, mask, data);
0750 }
0751
0752 static inline void
0753 rtw89_write16_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
0754 u32 base, u32 mask, u16 data)
0755 {
0756 u32 reg;
0757
0758 reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx);
0759 rtw89_write16_mask(rtwdev, reg, mask, data);
0760 }
0761
0762 static inline void
0763 rtw89_write32_port_clr(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
0764 u32 base, u32 bit)
0765 {
0766 u32 reg;
0767
0768 reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx);
0769 rtw89_write32_clr(rtwdev, reg, bit);
0770 }
0771
0772 static inline void
0773 rtw89_write16_port_clr(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
0774 u32 base, u16 bit)
0775 {
0776 u32 reg;
0777
0778 reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx);
0779 rtw89_write16_clr(rtwdev, reg, bit);
0780 }
0781
0782 static inline void
0783 rtw89_write32_port_set(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
0784 u32 base, u32 bit)
0785 {
0786 u32 reg;
0787
0788 reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx);
0789 rtw89_write32_set(rtwdev, reg, bit);
0790 }
0791
0792 void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev);
0793 int rtw89_mac_partial_init(struct rtw89_dev *rtwdev);
0794 int rtw89_mac_init(struct rtw89_dev *rtwdev);
0795 int rtw89_mac_check_mac_en(struct rtw89_dev *rtwdev, u8 band,
0796 enum rtw89_mac_hwmod_sel sel);
0797 int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val);
0798 int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val);
0799 int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *vif);
0800 int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
0801 int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *vif);
0802 int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev);
0803 void rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev);
0804
0805 static inline int rtw89_chip_enable_bb_rf(struct rtw89_dev *rtwdev)
0806 {
0807 const struct rtw89_chip_info *chip = rtwdev->chip;
0808
0809 return chip->ops->enable_bb_rf(rtwdev);
0810 }
0811
0812 static inline void rtw89_chip_disable_bb_rf(struct rtw89_dev *rtwdev)
0813 {
0814 const struct rtw89_chip_info *chip = rtwdev->chip;
0815
0816 chip->ops->disable_bb_rf(rtwdev);
0817 }
0818
0819 u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev);
0820 int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err);
0821 void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb,
0822 u32 len, u8 class, u8 func);
0823 int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev);
0824 int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx,
0825 u32 *tx_en, enum rtw89_sch_tx_sel sel);
0826 int rtw89_mac_stop_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx,
0827 u32 *tx_en, enum rtw89_sch_tx_sel sel);
0828 int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en);
0829 int rtw89_mac_resume_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en);
0830 int rtw89_mac_cfg_ppdu_status(struct rtw89_dev *rtwdev, u8 mac_ids, bool enable);
0831 void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx);
0832 void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop);
0833 int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex);
0834 int rtw89_mac_coex_init_v1(struct rtw89_dev *rtwdev,
0835 const struct rtw89_mac_ax_coex *coex);
0836 int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev,
0837 const struct rtw89_mac_ax_coex_gnt *gnt_cfg);
0838 int rtw89_mac_cfg_gnt_v1(struct rtw89_dev *rtwdev,
0839 const struct rtw89_mac_ax_coex_gnt *gnt_cfg);
0840 int rtw89_mac_cfg_plt(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt);
0841 u16 rtw89_mac_get_plt_cnt(struct rtw89_dev *rtwdev, u8 band);
0842 void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val);
0843 u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev);
0844 bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev);
0845 int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl);
0846 int rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev *rtwdev, bool wl);
0847 bool rtw89_mac_get_txpwr_cr(struct rtw89_dev *rtwdev,
0848 enum rtw89_phy_idx phy_idx,
0849 u32 reg_base, u32 *cr);
0850 void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter);
0851 void rtw89_mac_notify_wake(struct rtw89_dev *rtwdev);
0852 void rtw89_mac_bf_assoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
0853 struct ieee80211_sta *sta);
0854 void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
0855 struct ieee80211_sta *sta);
0856 void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
0857 struct ieee80211_bss_conf *conf);
0858 void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev,
0859 struct ieee80211_sta *sta, bool disconnect);
0860 void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev);
0861 int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
0862 int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
0863 int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev,
0864 struct rtw89_vif *rtwvif, bool en);
0865 int rtw89_mac_set_macid_pause(struct rtw89_dev *rtwdev, u8 macid, bool pause);
0866
0867 static inline void rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev)
0868 {
0869 if (!test_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags))
0870 return;
0871
0872 _rtw89_mac_bf_monitor_track(rtwdev);
0873 }
0874
0875 static inline int rtw89_mac_txpwr_read32(struct rtw89_dev *rtwdev,
0876 enum rtw89_phy_idx phy_idx,
0877 u32 reg_base, u32 *val)
0878 {
0879 u32 cr;
0880
0881 if (!rtw89_mac_get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr))
0882 return -EINVAL;
0883
0884 *val = rtw89_read32(rtwdev, cr);
0885 return 0;
0886 }
0887
0888 static inline int rtw89_mac_txpwr_write32(struct rtw89_dev *rtwdev,
0889 enum rtw89_phy_idx phy_idx,
0890 u32 reg_base, u32 val)
0891 {
0892 u32 cr;
0893
0894 if (!rtw89_mac_get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr))
0895 return -EINVAL;
0896
0897 rtw89_write32(rtwdev, cr, val);
0898 return 0;
0899 }
0900
0901 static inline int rtw89_mac_txpwr_write32_mask(struct rtw89_dev *rtwdev,
0902 enum rtw89_phy_idx phy_idx,
0903 u32 reg_base, u32 mask, u32 val)
0904 {
0905 u32 cr;
0906
0907 if (!rtw89_mac_get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr))
0908 return -EINVAL;
0909
0910 rtw89_write32_mask(rtwdev, cr, mask, val);
0911 return 0;
0912 }
0913
0914 int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
0915 bool resume, u32 tx_time);
0916 int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
0917 u32 *tx_time);
0918 int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev,
0919 struct rtw89_sta *rtwsta,
0920 bool resume, u8 tx_retry);
0921 int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev,
0922 struct rtw89_sta *rtwsta, u8 *tx_retry);
0923
0924 enum rtw89_mac_xtal_si_offset {
0925 XTAL0 = 0x0,
0926 XTAL3 = 0x3,
0927 XTAL_SI_XTAL_SC_XI = 0x04,
0928 #define XTAL_SC_XI_MASK GENMASK(7, 0)
0929 XTAL_SI_XTAL_SC_XO = 0x05,
0930 #define XTAL_SC_XO_MASK GENMASK(7, 0)
0931 XTAL_SI_PWR_CUT = 0x10,
0932 #define XTAL_SI_SMALL_PWR_CUT BIT(0)
0933 #define XTAL_SI_BIG_PWR_CUT BIT(1)
0934 XTAL_SI_XTAL_XMD_2 = 0x24,
0935 #define XTAL_SI_LDO_LPS GENMASK(6, 4)
0936 XTAL_SI_XTAL_XMD_4 = 0x26,
0937 #define XTAL_SI_LPS_CAP GENMASK(3, 0)
0938 XTAL_SI_CV = 0x41,
0939 XTAL_SI_LOW_ADDR = 0x62,
0940 #define XTAL_SI_LOW_ADDR_MASK GENMASK(7, 0)
0941 XTAL_SI_CTRL = 0x63,
0942 #define XTAL_SI_MODE_SEL_MASK GENMASK(7, 6)
0943 #define XTAL_SI_RDY BIT(5)
0944 #define XTAL_SI_HIGH_ADDR_MASK GENMASK(2, 0)
0945 XTAL_SI_READ_VAL = 0x7A,
0946 XTAL_SI_WL_RFC_S0 = 0x80,
0947 #define XTAL_SI_RF00 BIT(0)
0948 XTAL_SI_WL_RFC_S1 = 0x81,
0949 #define XTAL_SI_RF10 BIT(0)
0950 XTAL_SI_ANAPAR_WL = 0x90,
0951 #define XTAL_SI_SRAM2RFC BIT(7)
0952 #define XTAL_SI_GND_SHDN_WL BIT(6)
0953 #define XTAL_SI_SHDN_WL BIT(5)
0954 #define XTAL_SI_RFC2RF BIT(4)
0955 #define XTAL_SI_OFF_EI BIT(3)
0956 #define XTAL_SI_OFF_WEI BIT(2)
0957 #define XTAL_SI_PON_EI BIT(1)
0958 #define XTAL_SI_PON_WEI BIT(0)
0959 XTAL_SI_SRAM_CTRL = 0xA1,
0960 #define FULL_BIT_MASK GENMASK(7, 0)
0961 };
0962
0963 int rtw89_mac_write_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask);
0964 int rtw89_mac_read_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 *val);
0965
0966 #endif
