0001
0002
0003
0004
0005 #include <linux/vmalloc.h>
0006
0007 #include "coex.h"
0008 #include "debug.h"
0009 #include "fw.h"
0010 #include "mac.h"
0011 #include "ps.h"
0012 #include "reg.h"
0013 #include "sar.h"
0014
0015 #ifdef CONFIG_RTW89_DEBUGMSG
0016 unsigned int rtw89_debug_mask;
0017 EXPORT_SYMBOL(rtw89_debug_mask);
0018 module_param_named(debug_mask, rtw89_debug_mask, uint, 0644);
0019 MODULE_PARM_DESC(debug_mask, "Debugging mask");
0020 #endif
0021
0022 #ifdef CONFIG_RTW89_DEBUGFS
0023 struct rtw89_debugfs_priv {
0024 struct rtw89_dev *rtwdev;
0025 int (*cb_read)(struct seq_file *m, void *v);
0026 ssize_t (*cb_write)(struct file *filp, const char __user *buffer,
0027 size_t count, loff_t *loff);
0028 union {
0029 u32 cb_data;
0030 struct {
0031 u32 addr;
0032 u8 len;
0033 } read_reg;
0034 struct {
0035 u32 addr;
0036 u32 mask;
0037 u8 path;
0038 } read_rf;
0039 struct {
0040 u8 ss_dbg:1;
0041 u8 dle_dbg:1;
0042 u8 dmac_dbg:1;
0043 u8 cmac_dbg:1;
0044 u8 dbg_port:1;
0045 } dbgpkg_en;
0046 struct {
0047 u32 start;
0048 u32 len;
0049 u8 sel;
0050 } mac_mem;
0051 };
0052 };
0053
0054 static int rtw89_debugfs_single_show(struct seq_file *m, void *v)
0055 {
0056 struct rtw89_debugfs_priv *debugfs_priv = m->private;
0057
0058 return debugfs_priv->cb_read(m, v);
0059 }
0060
0061 static ssize_t rtw89_debugfs_single_write(struct file *filp,
0062 const char __user *buffer,
0063 size_t count, loff_t *loff)
0064 {
0065 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data;
0066
0067 return debugfs_priv->cb_write(filp, buffer, count, loff);
0068 }
0069
0070 static ssize_t rtw89_debugfs_seq_file_write(struct file *filp,
0071 const char __user *buffer,
0072 size_t count, loff_t *loff)
0073 {
0074 struct seq_file *seqpriv = (struct seq_file *)filp->private_data;
0075 struct rtw89_debugfs_priv *debugfs_priv = seqpriv->private;
0076
0077 return debugfs_priv->cb_write(filp, buffer, count, loff);
0078 }
0079
0080 static int rtw89_debugfs_single_open(struct inode *inode, struct file *filp)
0081 {
0082 return single_open(filp, rtw89_debugfs_single_show, inode->i_private);
0083 }
0084
0085 static int rtw89_debugfs_close(struct inode *inode, struct file *filp)
0086 {
0087 return 0;
0088 }
0089
0090 static const struct file_operations file_ops_single_r = {
0091 .owner = THIS_MODULE,
0092 .open = rtw89_debugfs_single_open,
0093 .read = seq_read,
0094 .llseek = seq_lseek,
0095 .release = single_release,
0096 };
0097
0098 static const struct file_operations file_ops_common_rw = {
0099 .owner = THIS_MODULE,
0100 .open = rtw89_debugfs_single_open,
0101 .release = single_release,
0102 .read = seq_read,
0103 .llseek = seq_lseek,
0104 .write = rtw89_debugfs_seq_file_write,
0105 };
0106
0107 static const struct file_operations file_ops_single_w = {
0108 .owner = THIS_MODULE,
0109 .write = rtw89_debugfs_single_write,
0110 .open = simple_open,
0111 .release = rtw89_debugfs_close,
0112 };
0113
0114 static ssize_t
0115 rtw89_debug_priv_read_reg_select(struct file *filp,
0116 const char __user *user_buf,
0117 size_t count, loff_t *loff)
0118 {
0119 struct seq_file *m = (struct seq_file *)filp->private_data;
0120 struct rtw89_debugfs_priv *debugfs_priv = m->private;
0121 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
0122 char buf[32];
0123 size_t buf_size;
0124 u32 addr, len;
0125 int num;
0126
0127 buf_size = min(count, sizeof(buf) - 1);
0128 if (copy_from_user(buf, user_buf, buf_size))
0129 return -EFAULT;
0130
0131 buf[buf_size] = '\0';
0132 num = sscanf(buf, "%x %x", &addr, &len);
0133 if (num != 2) {
0134 rtw89_info(rtwdev, "invalid format: <addr> <len>\n");
0135 return -EINVAL;
0136 }
0137
0138 debugfs_priv->read_reg.addr = addr;
0139 debugfs_priv->read_reg.len = len;
0140
0141 rtw89_info(rtwdev, "select read %d bytes from 0x%08x\n", len, addr);
0142
0143 return count;
0144 }
0145
0146 static int rtw89_debug_priv_read_reg_get(struct seq_file *m, void *v)
0147 {
0148 struct rtw89_debugfs_priv *debugfs_priv = m->private;
0149 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
0150 u32 addr, data;
0151 u8 len;
0152
0153 len = debugfs_priv->read_reg.len;
0154 addr = debugfs_priv->read_reg.addr;
0155
0156 switch (len) {
0157 case 1:
0158 data = rtw89_read8(rtwdev, addr);
0159 break;
0160 case 2:
0161 data = rtw89_read16(rtwdev, addr);
0162 break;
0163 case 4:
0164 data = rtw89_read32(rtwdev, addr);
0165 break;
0166 default:
0167 rtw89_info(rtwdev, "invalid read reg len %d\n", len);
0168 return -EINVAL;
0169 }
0170
0171 seq_printf(m, "get %d bytes at 0x%08x=0x%08x\n", len, addr, data);
0172
0173 return 0;
0174 }
0175
0176 static ssize_t rtw89_debug_priv_write_reg_set(struct file *filp,
0177 const char __user *user_buf,
0178 size_t count, loff_t *loff)
0179 {
0180 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data;
0181 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
0182 char buf[32];
0183 size_t buf_size;
0184 u32 addr, val, len;
0185 int num;
0186
0187 buf_size = min(count, sizeof(buf) - 1);
0188 if (copy_from_user(buf, user_buf, buf_size))
0189 return -EFAULT;
0190
0191 buf[buf_size] = '\0';
0192 num = sscanf(buf, "%x %x %x", &addr, &val, &len);
0193 if (num != 3) {
0194 rtw89_info(rtwdev, "invalid format: <addr> <val> <len>\n");
0195 return -EINVAL;
0196 }
0197
0198 switch (len) {
0199 case 1:
0200 rtw89_info(rtwdev, "reg write8 0x%08x: 0x%02x\n", addr, val);
0201 rtw89_write8(rtwdev, addr, (u8)val);
0202 break;
0203 case 2:
0204 rtw89_info(rtwdev, "reg write16 0x%08x: 0x%04x\n", addr, val);
0205 rtw89_write16(rtwdev, addr, (u16)val);
0206 break;
0207 case 4:
0208 rtw89_info(rtwdev, "reg write32 0x%08x: 0x%08x\n", addr, val);
0209 rtw89_write32(rtwdev, addr, (u32)val);
0210 break;
0211 default:
0212 rtw89_info(rtwdev, "invalid read write len %d\n", len);
0213 break;
0214 }
0215
0216 return count;
0217 }
0218
0219 static ssize_t
0220 rtw89_debug_priv_read_rf_select(struct file *filp,
0221 const char __user *user_buf,
0222 size_t count, loff_t *loff)
0223 {
0224 struct seq_file *m = (struct seq_file *)filp->private_data;
0225 struct rtw89_debugfs_priv *debugfs_priv = m->private;
0226 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
0227 char buf[32];
0228 size_t buf_size;
0229 u32 addr, mask;
0230 u8 path;
0231 int num;
0232
0233 buf_size = min(count, sizeof(buf) - 1);
0234 if (copy_from_user(buf, user_buf, buf_size))
0235 return -EFAULT;
0236
0237 buf[buf_size] = '\0';
0238 num = sscanf(buf, "%hhd %x %x", &path, &addr, &mask);
0239 if (num != 3) {
0240 rtw89_info(rtwdev, "invalid format: <path> <addr> <mask>\n");
0241 return -EINVAL;
0242 }
0243
0244 if (path >= rtwdev->chip->rf_path_num) {
0245 rtw89_info(rtwdev, "wrong rf path\n");
0246 return -EINVAL;
0247 }
0248 debugfs_priv->read_rf.addr = addr;
0249 debugfs_priv->read_rf.mask = mask;
0250 debugfs_priv->read_rf.path = path;
0251
0252 rtw89_info(rtwdev, "select read rf path %d from 0x%08x\n", path, addr);
0253
0254 return count;
0255 }
0256
0257 static int rtw89_debug_priv_read_rf_get(struct seq_file *m, void *v)
0258 {
0259 struct rtw89_debugfs_priv *debugfs_priv = m->private;
0260 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
0261 u32 addr, data, mask;
0262 u8 path;
0263
0264 addr = debugfs_priv->read_rf.addr;
0265 mask = debugfs_priv->read_rf.mask;
0266 path = debugfs_priv->read_rf.path;
0267
0268 data = rtw89_read_rf(rtwdev, path, addr, mask);
0269
0270 seq_printf(m, "path %d, rf register 0x%08x=0x%08x\n", path, addr, data);
0271
0272 return 0;
0273 }
0274
0275 static ssize_t rtw89_debug_priv_write_rf_set(struct file *filp,
0276 const char __user *user_buf,
0277 size_t count, loff_t *loff)
0278 {
0279 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data;
0280 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
0281 char buf[32];
0282 size_t buf_size;
0283 u32 addr, val, mask;
0284 u8 path;
0285 int num;
0286
0287 buf_size = min(count, sizeof(buf) - 1);
0288 if (copy_from_user(buf, user_buf, buf_size))
0289 return -EFAULT;
0290
0291 buf[buf_size] = '\0';
0292 num = sscanf(buf, "%hhd %x %x %x", &path, &addr, &mask, &val);
0293 if (num != 4) {
0294 rtw89_info(rtwdev, "invalid format: <path> <addr> <mask> <val>\n");
0295 return -EINVAL;
0296 }
0297
0298 if (path >= rtwdev->chip->rf_path_num) {
0299 rtw89_info(rtwdev, "wrong rf path\n");
0300 return -EINVAL;
0301 }
0302
0303 rtw89_info(rtwdev, "path %d, rf register write 0x%08x=0x%08x (mask = 0x%08x)\n",
0304 path, addr, val, mask);
0305 rtw89_write_rf(rtwdev, path, addr, mask, val);
0306
0307 return count;
0308 }
0309
0310 static int rtw89_debug_priv_rf_reg_dump_get(struct seq_file *m, void *v)
0311 {
0312 struct rtw89_debugfs_priv *debugfs_priv = m->private;
0313 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
0314 const struct rtw89_chip_info *chip = rtwdev->chip;
0315 u32 addr, offset, data;
0316 u8 path;
0317
0318 for (path = 0; path < chip->rf_path_num; path++) {
0319 seq_printf(m, "RF path %d:\n\n", path);
0320 for (addr = 0; addr < 0x100; addr += 4) {
0321 seq_printf(m, "0x%08x: ", addr);
0322 for (offset = 0; offset < 4; offset++) {
0323 data = rtw89_read_rf(rtwdev, path,
0324 addr + offset, RFREG_MASK);
0325 seq_printf(m, "0x%05x ", data);
0326 }
0327 seq_puts(m, "\n");
0328 }
0329 seq_puts(m, "\n");
0330 }
0331
0332 return 0;
0333 }
0334
0335 struct txpwr_ent {
0336 const char *txt;
0337 u8 len;
0338 };
0339
0340 struct txpwr_map {
0341 const struct txpwr_ent *ent;
0342 u8 size;
0343 u32 addr_from;
0344 u32 addr_to;
0345 };
0346
0347 #define __GEN_TXPWR_ENT2(_t, _e0, _e1) \
0348 { .len = 2, .txt = _t "\t- " _e0 " " _e1 }
0349
0350 #define __GEN_TXPWR_ENT4(_t, _e0, _e1, _e2, _e3) \
0351 { .len = 4, .txt = _t "\t- " _e0 " " _e1 " " _e2 " " _e3 }
0352
0353 #define __GEN_TXPWR_ENT8(_t, _e0, _e1, _e2, _e3, _e4, _e5, _e6, _e7) \
0354 { .len = 8, .txt = _t "\t- " \
0355 _e0 " " _e1 " " _e2 " " _e3 " " \
0356 _e4 " " _e5 " " _e6 " " _e7 }
0357
0358 static const struct txpwr_ent __txpwr_ent_byr[] = {
0359 __GEN_TXPWR_ENT4("CCK ", "1M ", "2M ", "5.5M ", "11M "),
0360 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "),
0361 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "),
0362
0363 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "),
0364 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "),
0365 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"),
0366 __GEN_TXPWR_ENT4("HEDCM_1NSS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "),
0367
0368 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "),
0369 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "),
0370 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"),
0371 __GEN_TXPWR_ENT4("HEDCM_2NSS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "),
0372 };
0373
0374 static_assert((ARRAY_SIZE(__txpwr_ent_byr) * 4) ==
0375 (R_AX_PWR_BY_RATE_MAX - R_AX_PWR_BY_RATE + 4));
0376
0377 static const struct txpwr_map __txpwr_map_byr = {
0378 .ent = __txpwr_ent_byr,
0379 .size = ARRAY_SIZE(__txpwr_ent_byr),
0380 .addr_from = R_AX_PWR_BY_RATE,
0381 .addr_to = R_AX_PWR_BY_RATE_MAX,
0382 };
0383
0384 static const struct txpwr_ent __txpwr_ent_lmt[] = {
0385
0386 __GEN_TXPWR_ENT2("CCK_1TX_20M ", "NON_BF", "BF"),
0387 __GEN_TXPWR_ENT2("CCK_1TX_40M ", "NON_BF", "BF"),
0388 __GEN_TXPWR_ENT2("OFDM_1TX ", "NON_BF", "BF"),
0389 __GEN_TXPWR_ENT2("MCS_1TX_20M_0 ", "NON_BF", "BF"),
0390 __GEN_TXPWR_ENT2("MCS_1TX_20M_1 ", "NON_BF", "BF"),
0391 __GEN_TXPWR_ENT2("MCS_1TX_20M_2 ", "NON_BF", "BF"),
0392 __GEN_TXPWR_ENT2("MCS_1TX_20M_3 ", "NON_BF", "BF"),
0393 __GEN_TXPWR_ENT2("MCS_1TX_20M_4 ", "NON_BF", "BF"),
0394 __GEN_TXPWR_ENT2("MCS_1TX_20M_5 ", "NON_BF", "BF"),
0395 __GEN_TXPWR_ENT2("MCS_1TX_20M_6 ", "NON_BF", "BF"),
0396 __GEN_TXPWR_ENT2("MCS_1TX_20M_7 ", "NON_BF", "BF"),
0397 __GEN_TXPWR_ENT2("MCS_1TX_40M_0 ", "NON_BF", "BF"),
0398 __GEN_TXPWR_ENT2("MCS_1TX_40M_1 ", "NON_BF", "BF"),
0399 __GEN_TXPWR_ENT2("MCS_1TX_40M_2 ", "NON_BF", "BF"),
0400 __GEN_TXPWR_ENT2("MCS_1TX_40M_3 ", "NON_BF", "BF"),
0401 __GEN_TXPWR_ENT2("MCS_1TX_80M_0 ", "NON_BF", "BF"),
0402 __GEN_TXPWR_ENT2("MCS_1TX_80M_1 ", "NON_BF", "BF"),
0403 __GEN_TXPWR_ENT2("MCS_1TX_160M ", "NON_BF", "BF"),
0404 __GEN_TXPWR_ENT2("MCS_1TX_40M_0p5", "NON_BF", "BF"),
0405 __GEN_TXPWR_ENT2("MCS_1TX_40M_2p5", "NON_BF", "BF"),
0406
0407 __GEN_TXPWR_ENT2("CCK_2TX_20M ", "NON_BF", "BF"),
0408 __GEN_TXPWR_ENT2("CCK_2TX_40M ", "NON_BF", "BF"),
0409 __GEN_TXPWR_ENT2("OFDM_2TX ", "NON_BF", "BF"),
0410 __GEN_TXPWR_ENT2("MCS_2TX_20M_0 ", "NON_BF", "BF"),
0411 __GEN_TXPWR_ENT2("MCS_2TX_20M_1 ", "NON_BF", "BF"),
0412 __GEN_TXPWR_ENT2("MCS_2TX_20M_2 ", "NON_BF", "BF"),
0413 __GEN_TXPWR_ENT2("MCS_2TX_20M_3 ", "NON_BF", "BF"),
0414 __GEN_TXPWR_ENT2("MCS_2TX_20M_4 ", "NON_BF", "BF"),
0415 __GEN_TXPWR_ENT2("MCS_2TX_20M_5 ", "NON_BF", "BF"),
0416 __GEN_TXPWR_ENT2("MCS_2TX_20M_6 ", "NON_BF", "BF"),
0417 __GEN_TXPWR_ENT2("MCS_2TX_20M_7 ", "NON_BF", "BF"),
0418 __GEN_TXPWR_ENT2("MCS_2TX_40M_0 ", "NON_BF", "BF"),
0419 __GEN_TXPWR_ENT2("MCS_2TX_40M_1 ", "NON_BF", "BF"),
0420 __GEN_TXPWR_ENT2("MCS_2TX_40M_2 ", "NON_BF", "BF"),
0421 __GEN_TXPWR_ENT2("MCS_2TX_40M_3 ", "NON_BF", "BF"),
0422 __GEN_TXPWR_ENT2("MCS_2TX_80M_0 ", "NON_BF", "BF"),
0423 __GEN_TXPWR_ENT2("MCS_2TX_80M_1 ", "NON_BF", "BF"),
0424 __GEN_TXPWR_ENT2("MCS_2TX_160M ", "NON_BF", "BF"),
0425 __GEN_TXPWR_ENT2("MCS_2TX_40M_0p5", "NON_BF", "BF"),
0426 __GEN_TXPWR_ENT2("MCS_2TX_40M_2p5", "NON_BF", "BF"),
0427 };
0428
0429 static_assert((ARRAY_SIZE(__txpwr_ent_lmt) * 2) ==
0430 (R_AX_PWR_LMT_MAX - R_AX_PWR_LMT + 4));
0431
0432 static const struct txpwr_map __txpwr_map_lmt = {
0433 .ent = __txpwr_ent_lmt,
0434 .size = ARRAY_SIZE(__txpwr_ent_lmt),
0435 .addr_from = R_AX_PWR_LMT,
0436 .addr_to = R_AX_PWR_LMT_MAX,
0437 };
0438
0439 static const struct txpwr_ent __txpwr_ent_lmt_ru[] = {
0440
0441 __GEN_TXPWR_ENT8("1TX", "RU26__0", "RU26__1", "RU26__2", "RU26__3",
0442 "RU26__4", "RU26__5", "RU26__6", "RU26__7"),
0443 __GEN_TXPWR_ENT8("1TX", "RU52__0", "RU52__1", "RU52__2", "RU52__3",
0444 "RU52__4", "RU52__5", "RU52__6", "RU52__7"),
0445 __GEN_TXPWR_ENT8("1TX", "RU106_0", "RU106_1", "RU106_2", "RU106_3",
0446 "RU106_4", "RU106_5", "RU106_6", "RU106_7"),
0447
0448 __GEN_TXPWR_ENT8("2TX", "RU26__0", "RU26__1", "RU26__2", "RU26__3",
0449 "RU26__4", "RU26__5", "RU26__6", "RU26__7"),
0450 __GEN_TXPWR_ENT8("2TX", "RU52__0", "RU52__1", "RU52__2", "RU52__3",
0451 "RU52__4", "RU52__5", "RU52__6", "RU52__7"),
0452 __GEN_TXPWR_ENT8("2TX", "RU106_0", "RU106_1", "RU106_2", "RU106_3",
0453 "RU106_4", "RU106_5", "RU106_6", "RU106_7"),
0454 };
0455
0456 static_assert((ARRAY_SIZE(__txpwr_ent_lmt_ru) * 8) ==
0457 (R_AX_PWR_RU_LMT_MAX - R_AX_PWR_RU_LMT + 4));
0458
0459 static const struct txpwr_map __txpwr_map_lmt_ru = {
0460 .ent = __txpwr_ent_lmt_ru,
0461 .size = ARRAY_SIZE(__txpwr_ent_lmt_ru),
0462 .addr_from = R_AX_PWR_RU_LMT,
0463 .addr_to = R_AX_PWR_RU_LMT_MAX,
0464 };
0465
0466 static u8 __print_txpwr_ent(struct seq_file *m, const struct txpwr_ent *ent,
0467 const u8 *buf, const u8 cur)
0468 {
0469 char *fmt;
0470
0471 switch (ent->len) {
0472 case 2:
0473 fmt = "%s\t| %3d, %3d,\tdBm\n";
0474 seq_printf(m, fmt, ent->txt, buf[cur], buf[cur + 1]);
0475 return 2;
0476 case 4:
0477 fmt = "%s\t| %3d, %3d, %3d, %3d,\tdBm\n";
0478 seq_printf(m, fmt, ent->txt, buf[cur], buf[cur + 1],
0479 buf[cur + 2], buf[cur + 3]);
0480 return 4;
0481 case 8:
0482 fmt = "%s\t| %3d, %3d, %3d, %3d, %3d, %3d, %3d, %3d,\tdBm\n";
0483 seq_printf(m, fmt, ent->txt, buf[cur], buf[cur + 1],
0484 buf[cur + 2], buf[cur + 3], buf[cur + 4],
0485 buf[cur + 5], buf[cur + 6], buf[cur + 7]);
0486 return 8;
0487 default:
0488 return 0;
0489 }
0490 }
0491
0492 static int __print_txpwr_map(struct seq_file *m, struct rtw89_dev *rtwdev,
0493 const struct txpwr_map *map)
0494 {
0495 u8 fct = rtwdev->chip->txpwr_factor_mac;
0496 u8 *buf, cur, i;
0497 u32 val, addr;
0498 int ret;
0499
0500 buf = vzalloc(map->addr_to - map->addr_from + 4);
0501 if (!buf)
0502 return -ENOMEM;
0503
0504 for (addr = map->addr_from; addr <= map->addr_to; addr += 4) {
0505 ret = rtw89_mac_txpwr_read32(rtwdev, RTW89_PHY_0, addr, &val);
0506 if (ret)
0507 val = MASKDWORD;
0508
0509 cur = addr - map->addr_from;
0510 for (i = 0; i < 4; i++, val >>= 8)
0511 buf[cur + i] = FIELD_GET(MASKBYTE0, val) >> fct;
0512 }
0513
0514 for (cur = 0, i = 0; i < map->size; i++)
0515 cur += __print_txpwr_ent(m, &map->ent[i], buf, cur);
0516
0517 vfree(buf);
0518 return 0;
0519 }
0520
0521 #define case_REGD(_regd) \
0522 case RTW89_ ## _regd: \
0523 seq_puts(m, #_regd "\n"); \
0524 break
0525
0526 static void __print_regd(struct seq_file *m, struct rtw89_dev *rtwdev)
0527 {
0528 u8 band = rtwdev->hal.current_band_type;
0529 u8 regd = rtw89_regd_get(rtwdev, band);
0530
0531 switch (regd) {
0532 default:
0533 seq_printf(m, "UNKNOWN: %d\n", regd);
0534 break;
0535 case_REGD(WW);
0536 case_REGD(ETSI);
0537 case_REGD(FCC);
0538 case_REGD(MKK);
0539 case_REGD(NA);
0540 case_REGD(IC);
0541 case_REGD(KCC);
0542 case_REGD(NCC);
0543 case_REGD(CHILE);
0544 case_REGD(ACMA);
0545 case_REGD(MEXICO);
0546 case_REGD(UKRAINE);
0547 case_REGD(CN);
0548 }
0549 }
0550
0551 #undef case_REGD
0552
0553 static int rtw89_debug_priv_txpwr_table_get(struct seq_file *m, void *v)
0554 {
0555 struct rtw89_debugfs_priv *debugfs_priv = m->private;
0556 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
0557 int ret = 0;
0558
0559 mutex_lock(&rtwdev->mutex);
0560 rtw89_leave_ps_mode(rtwdev);
0561
0562 seq_puts(m, "[Regulatory] ");
0563 __print_regd(m, rtwdev);
0564
0565 seq_puts(m, "[SAR]\n");
0566 rtw89_print_sar(m, rtwdev);
0567
0568 seq_puts(m, "\n[TX power byrate]\n");
0569 ret = __print_txpwr_map(m, rtwdev, &__txpwr_map_byr);
0570 if (ret)
0571 goto err;
0572
0573 seq_puts(m, "\n[TX power limit]\n");
0574 ret = __print_txpwr_map(m, rtwdev, &__txpwr_map_lmt);
0575 if (ret)
0576 goto err;
0577
0578 seq_puts(m, "\n[TX power limit_ru]\n");
0579 ret = __print_txpwr_map(m, rtwdev, &__txpwr_map_lmt_ru);
0580 if (ret)
0581 goto err;
0582
0583 err:
0584 mutex_unlock(&rtwdev->mutex);
0585 return ret;
0586 }
0587
0588 static ssize_t
0589 rtw89_debug_priv_mac_reg_dump_select(struct file *filp,
0590 const char __user *user_buf,
0591 size_t count, loff_t *loff)
0592 {
0593 struct seq_file *m = (struct seq_file *)filp->private_data;
0594 struct rtw89_debugfs_priv *debugfs_priv = m->private;
0595 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
0596 char buf[32];
0597 size_t buf_size;
0598 int sel;
0599 int ret;
0600
0601 buf_size = min(count, sizeof(buf) - 1);
0602 if (copy_from_user(buf, user_buf, buf_size))
0603 return -EFAULT;
0604
0605 buf[buf_size] = '\0';
0606 ret = kstrtoint(buf, 0, &sel);
0607 if (ret)
0608 return ret;
0609
0610 if (sel < RTW89_DBG_SEL_MAC_00 || sel > RTW89_DBG_SEL_RFC) {
0611 rtw89_info(rtwdev, "invalid args: %d\n", sel);
0612 return -EINVAL;
0613 }
0614
0615 debugfs_priv->cb_data = sel;
0616 rtw89_info(rtwdev, "select mac page dump %d\n", debugfs_priv->cb_data);
0617
0618 return count;
0619 }
0620
0621 #define RTW89_MAC_PAGE_SIZE 0x100
0622
0623 static int rtw89_debug_priv_mac_reg_dump_get(struct seq_file *m, void *v)
0624 {
0625 struct rtw89_debugfs_priv *debugfs_priv = m->private;
0626 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
0627 enum rtw89_debug_mac_reg_sel reg_sel = debugfs_priv->cb_data;
0628 u32 start, end;
0629 u32 i, j, k, page;
0630 u32 val;
0631
0632 switch (reg_sel) {
0633 case RTW89_DBG_SEL_MAC_00:
0634 seq_puts(m, "Debug selected MAC page 0x00\n");
0635 start = 0x000;
0636 end = 0x014;
0637 break;
0638 case RTW89_DBG_SEL_MAC_30:
0639 seq_puts(m, "Debug selected MAC page 0x30\n");
0640 start = 0x030;
0641 end = 0x033;
0642 break;
0643 case RTW89_DBG_SEL_MAC_40:
0644 seq_puts(m, "Debug selected MAC page 0x40\n");
0645 start = 0x040;
0646 end = 0x07f;
0647 break;
0648 case RTW89_DBG_SEL_MAC_80:
0649 seq_puts(m, "Debug selected MAC page 0x80\n");
0650 start = 0x080;
0651 end = 0x09f;
0652 break;
0653 case RTW89_DBG_SEL_MAC_C0:
0654 seq_puts(m, "Debug selected MAC page 0xc0\n");
0655 start = 0x0c0;
0656 end = 0x0df;
0657 break;
0658 case RTW89_DBG_SEL_MAC_E0:
0659 seq_puts(m, "Debug selected MAC page 0xe0\n");
0660 start = 0x0e0;
0661 end = 0x0ff;
0662 break;
0663 case RTW89_DBG_SEL_BB:
0664 seq_puts(m, "Debug selected BB register\n");
0665 start = 0x100;
0666 end = 0x17f;
0667 break;
0668 case RTW89_DBG_SEL_IQK:
0669 seq_puts(m, "Debug selected IQK register\n");
0670 start = 0x180;
0671 end = 0x1bf;
0672 break;
0673 case RTW89_DBG_SEL_RFC:
0674 seq_puts(m, "Debug selected RFC register\n");
0675 start = 0x1c0;
0676 end = 0x1ff;
0677 break;
0678 default:
0679 seq_puts(m, "Selected invalid register page\n");
0680 return -EINVAL;
0681 }
0682
0683 for (i = start; i <= end; i++) {
0684 page = i << 8;
0685 for (j = page; j < page + RTW89_MAC_PAGE_SIZE; j += 16) {
0686 seq_printf(m, "%08xh : ", 0x18600000 + j);
0687 for (k = 0; k < 4; k++) {
0688 val = rtw89_read32(rtwdev, j + (k << 2));
0689 seq_printf(m, "%08x ", val);
0690 }
0691 seq_puts(m, "\n");
0692 }
0693 }
0694
0695 return 0;
0696 }
0697
0698 static ssize_t
0699 rtw89_debug_priv_mac_mem_dump_select(struct file *filp,
0700 const char __user *user_buf,
0701 size_t count, loff_t *loff)
0702 {
0703 struct seq_file *m = (struct seq_file *)filp->private_data;
0704 struct rtw89_debugfs_priv *debugfs_priv = m->private;
0705 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
0706 char buf[32];
0707 size_t buf_size;
0708 u32 sel, start_addr, len;
0709 int num;
0710
0711 buf_size = min(count, sizeof(buf) - 1);
0712 if (copy_from_user(buf, user_buf, buf_size))
0713 return -EFAULT;
0714
0715 buf[buf_size] = '\0';
0716 num = sscanf(buf, "%x %x %x", &sel, &start_addr, &len);
0717 if (num != 3) {
0718 rtw89_info(rtwdev, "invalid format: <sel> <start> <len>\n");
0719 return -EINVAL;
0720 }
0721
0722 debugfs_priv->mac_mem.sel = sel;
0723 debugfs_priv->mac_mem.start = start_addr;
0724 debugfs_priv->mac_mem.len = len;
0725
0726 rtw89_info(rtwdev, "select mem %d start %d len %d\n",
0727 sel, start_addr, len);
0728
0729 return count;
0730 }
0731
0732 static void rtw89_debug_dump_mac_mem(struct seq_file *m,
0733 struct rtw89_dev *rtwdev,
0734 u8 sel, u32 start_addr, u32 len)
0735 {
0736 u32 base_addr, start_page, residue;
0737 u32 i, j, p, pages;
0738 u32 dump_len, remain;
0739 u32 val;
0740
0741 remain = len;
0742 pages = len / MAC_MEM_DUMP_PAGE_SIZE + 1;
0743 start_page = start_addr / MAC_MEM_DUMP_PAGE_SIZE;
0744 residue = start_addr % MAC_MEM_DUMP_PAGE_SIZE;
0745 base_addr = rtw89_mac_mem_base_addrs[sel];
0746 base_addr += start_page * MAC_MEM_DUMP_PAGE_SIZE;
0747
0748 for (p = 0; p < pages; p++) {
0749 dump_len = min_t(u32, remain, MAC_MEM_DUMP_PAGE_SIZE);
0750 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, base_addr);
0751 for (i = R_AX_INDIR_ACCESS_ENTRY + residue;
0752 i < R_AX_INDIR_ACCESS_ENTRY + dump_len;) {
0753 seq_printf(m, "%08xh:", i);
0754 for (j = 0;
0755 j < 4 && i < R_AX_INDIR_ACCESS_ENTRY + dump_len;
0756 j++, i += 4) {
0757 val = rtw89_read32(rtwdev, i);
0758 seq_printf(m, " %08x", val);
0759 remain -= 4;
0760 }
0761 seq_puts(m, "\n");
0762 }
0763 base_addr += MAC_MEM_DUMP_PAGE_SIZE;
0764 }
0765 }
0766
0767 static int
0768 rtw89_debug_priv_mac_mem_dump_get(struct seq_file *m, void *v)
0769 {
0770 struct rtw89_debugfs_priv *debugfs_priv = m->private;
0771 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
0772
0773 mutex_lock(&rtwdev->mutex);
0774 rtw89_leave_ps_mode(rtwdev);
0775 rtw89_debug_dump_mac_mem(m, rtwdev,
0776 debugfs_priv->mac_mem.sel,
0777 debugfs_priv->mac_mem.start,
0778 debugfs_priv->mac_mem.len);
0779 mutex_unlock(&rtwdev->mutex);
0780
0781 return 0;
0782 }
0783
0784 static ssize_t
0785 rtw89_debug_priv_mac_dbg_port_dump_select(struct file *filp,
0786 const char __user *user_buf,
0787 size_t count, loff_t *loff)
0788 {
0789 struct seq_file *m = (struct seq_file *)filp->private_data;
0790 struct rtw89_debugfs_priv *debugfs_priv = m->private;
0791 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
0792 char buf[32];
0793 size_t buf_size;
0794 int sel, set;
0795 int num;
0796 bool enable;
0797
0798 buf_size = min(count, sizeof(buf) - 1);
0799 if (copy_from_user(buf, user_buf, buf_size))
0800 return -EFAULT;
0801
0802 buf[buf_size] = '\0';
0803 num = sscanf(buf, "%d %d", &sel, &set);
0804 if (num != 2) {
0805 rtw89_info(rtwdev, "invalid format: <sel> <set>\n");
0806 return -EINVAL;
0807 }
0808
0809 enable = set != 0;
0810 switch (sel) {
0811 case 0:
0812 debugfs_priv->dbgpkg_en.ss_dbg = enable;
0813 break;
0814 case 1:
0815 debugfs_priv->dbgpkg_en.dle_dbg = enable;
0816 break;
0817 case 2:
0818 debugfs_priv->dbgpkg_en.dmac_dbg = enable;
0819 break;
0820 case 3:
0821 debugfs_priv->dbgpkg_en.cmac_dbg = enable;
0822 break;
0823 case 4:
0824 debugfs_priv->dbgpkg_en.dbg_port = enable;
0825 break;
0826 default:
0827 rtw89_info(rtwdev, "invalid args: sel %d set %d\n", sel, set);
0828 return -EINVAL;
0829 }
0830
0831 rtw89_info(rtwdev, "%s debug port dump %d\n",
0832 enable ? "Enable" : "Disable", sel);
0833
0834 return count;
0835 }
0836
0837 static int rtw89_debug_mac_dump_ss_dbg(struct rtw89_dev *rtwdev,
0838 struct seq_file *m)
0839 {
0840 return 0;
0841 }
0842
0843 static int rtw89_debug_mac_dump_dle_dbg(struct rtw89_dev *rtwdev,
0844 struct seq_file *m)
0845 {
0846 #define DLE_DFI_DUMP(__type, __target, __sel) \
0847 ({ \
0848 u32 __ctrl; \
0849 u32 __reg_ctrl = R_AX_##__type##_DBG_FUN_INTF_CTL; \
0850 u32 __reg_data = R_AX_##__type##_DBG_FUN_INTF_DATA; \
0851 u32 __data, __val32; \
0852 int __ret; \
0853 \
0854 __ctrl = FIELD_PREP(B_AX_##__type##_DFI_TRGSEL_MASK, \
0855 DLE_DFI_TYPE_##__target) | \
0856 FIELD_PREP(B_AX_##__type##_DFI_ADDR_MASK, __sel) | \
0857 B_AX_WDE_DFI_ACTIVE; \
0858 rtw89_write32(rtwdev, __reg_ctrl, __ctrl); \
0859 __ret = read_poll_timeout(rtw89_read32, __val32, \
0860 !(__val32 & B_AX_##__type##_DFI_ACTIVE), \
0861 1000, 50000, false, \
0862 rtwdev, __reg_ctrl); \
0863 if (__ret) { \
0864 rtw89_err(rtwdev, "failed to dump DLE %s %s %d\n", \
0865 #__type, #__target, __sel); \
0866 return __ret; \
0867 } \
0868 \
0869 __data = rtw89_read32(rtwdev, __reg_data); \
0870 __data; \
0871 })
0872
0873 #define DLE_DFI_FREE_PAGE_DUMP(__m, __type) \
0874 ({ \
0875 u32 __freepg, __pubpg; \
0876 u32 __freepg_head, __freepg_tail, __pubpg_num; \
0877 \
0878 __freepg = DLE_DFI_DUMP(__type, FREEPG, 0); \
0879 __pubpg = DLE_DFI_DUMP(__type, FREEPG, 1); \
0880 __freepg_head = FIELD_GET(B_AX_DLE_FREE_HEADPG, __freepg); \
0881 __freepg_tail = FIELD_GET(B_AX_DLE_FREE_TAILPG, __freepg); \
0882 __pubpg_num = FIELD_GET(B_AX_DLE_PUB_PGNUM, __pubpg); \
0883 seq_printf(__m, "[%s] freepg head: %d\n", \
0884 #__type, __freepg_head); \
0885 seq_printf(__m, "[%s] freepg tail: %d\n", \
0886 #__type, __freepg_tail); \
0887 seq_printf(__m, "[%s] pubpg num : %d\n", \
0888 #__type, __pubpg_num); \
0889 })
0890
0891 #define case_QUOTA(__m, __type, __id) \
0892 case __type##_QTAID_##__id: \
0893 val32 = DLE_DFI_DUMP(__type, QUOTA, __type##_QTAID_##__id); \
0894 rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, val32); \
0895 use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, val32); \
0896 seq_printf(__m, "[%s][%s] rsv_pgnum: %d\n", \
0897 #__type, #__id, rsv_pgnum); \
0898 seq_printf(__m, "[%s][%s] use_pgnum: %d\n", \
0899 #__type, #__id, use_pgnum); \
0900 break
0901 u32 quota_id;
0902 u32 val32;
0903 u16 rsv_pgnum, use_pgnum;
0904 int ret;
0905
0906 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL);
0907 if (ret) {
0908 seq_puts(m, "[DLE] : DMAC not enabled\n");
0909 return ret;
0910 }
0911
0912 DLE_DFI_FREE_PAGE_DUMP(m, WDE);
0913 DLE_DFI_FREE_PAGE_DUMP(m, PLE);
0914 for (quota_id = 0; quota_id <= WDE_QTAID_CPUIO; quota_id++) {
0915 switch (quota_id) {
0916 case_QUOTA(m, WDE, HOST_IF);
0917 case_QUOTA(m, WDE, WLAN_CPU);
0918 case_QUOTA(m, WDE, DATA_CPU);
0919 case_QUOTA(m, WDE, PKTIN);
0920 case_QUOTA(m, WDE, CPUIO);
0921 }
0922 }
0923 for (quota_id = 0; quota_id <= PLE_QTAID_CPUIO; quota_id++) {
0924 switch (quota_id) {
0925 case_QUOTA(m, PLE, B0_TXPL);
0926 case_QUOTA(m, PLE, B1_TXPL);
0927 case_QUOTA(m, PLE, C2H);
0928 case_QUOTA(m, PLE, H2C);
0929 case_QUOTA(m, PLE, WLAN_CPU);
0930 case_QUOTA(m, PLE, MPDU);
0931 case_QUOTA(m, PLE, CMAC0_RX);
0932 case_QUOTA(m, PLE, CMAC1_RX);
0933 case_QUOTA(m, PLE, CMAC1_BBRPT);
0934 case_QUOTA(m, PLE, WDRLS);
0935 case_QUOTA(m, PLE, CPUIO);
0936 }
0937 }
0938
0939 return 0;
0940
0941 #undef case_QUOTA
0942 #undef DLE_DFI_DUMP
0943 #undef DLE_DFI_FREE_PAGE_DUMP
0944 }
0945
0946 static int rtw89_debug_mac_dump_dmac_dbg(struct rtw89_dev *rtwdev,
0947 struct seq_file *m)
0948 {
0949 int ret;
0950
0951 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL);
0952 if (ret) {
0953 seq_puts(m, "[DMAC] : DMAC not enabled\n");
0954 return ret;
0955 }
0956
0957 seq_printf(m, "R_AX_DMAC_ERR_ISR=0x%08x\n",
0958 rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR));
0959 seq_printf(m, "[0]R_AX_WDRLS_ERR_ISR=0x%08x\n",
0960 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR));
0961 seq_printf(m, "[1]R_AX_SEC_ERR_IMR_ISR=0x%08x\n",
0962 rtw89_read32(rtwdev, R_AX_SEC_ERR_IMR_ISR));
0963 seq_printf(m, "[2.1]R_AX_MPDU_TX_ERR_ISR=0x%08x\n",
0964 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR));
0965 seq_printf(m, "[2.2]R_AX_MPDU_RX_ERR_ISR=0x%08x\n",
0966 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR));
0967 seq_printf(m, "[3]R_AX_STA_SCHEDULER_ERR_ISR=0x%08x\n",
0968 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR));
0969 seq_printf(m, "[4]R_AX_WDE_ERR_ISR=0x%08x\n",
0970 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR));
0971 seq_printf(m, "[5.1]R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n",
0972 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR));
0973 seq_printf(m, "[5.2]R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n",
0974 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1));
0975 seq_printf(m, "[6]R_AX_PLE_ERR_FLAG_ISR=0x%08x\n",
0976 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR));
0977 seq_printf(m, "[7]R_AX_PKTIN_ERR_ISR=0x%08x\n",
0978 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR));
0979 seq_printf(m, "[8.1]R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n",
0980 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR));
0981 seq_printf(m, "[8.2]R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n",
0982 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR));
0983 seq_printf(m, "[8.3]R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n",
0984 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR));
0985 seq_printf(m, "[10]R_AX_CPUIO_ERR_ISR=0x%08x\n",
0986 rtw89_read32(rtwdev, R_AX_CPUIO_ERR_ISR));
0987 seq_printf(m, "[11.1]R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n",
0988 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR));
0989 seq_printf(m, "[11.2]R_AX_BBRPT_CHINFO_ERR_IMR_ISR=0x%08x\n",
0990 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR_ISR));
0991 seq_printf(m, "[11.3]R_AX_BBRPT_DFS_ERR_IMR_ISR=0x%08x\n",
0992 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR_ISR));
0993 seq_printf(m, "[11.4]R_AX_LA_ERRFLAG=0x%08x\n",
0994 rtw89_read32(rtwdev, R_AX_LA_ERRFLAG));
0995
0996 return 0;
0997 }
0998
0999 static int rtw89_debug_mac_dump_cmac_dbg(struct rtw89_dev *rtwdev,
1000 struct seq_file *m)
1001 {
1002 int ret;
1003
1004 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_CMAC_SEL);
1005 if (ret) {
1006 seq_puts(m, "[CMAC] : CMAC 0 not enabled\n");
1007 return ret;
1008 }
1009
1010 seq_printf(m, "R_AX_CMAC_ERR_ISR=0x%08x\n",
1011 rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR));
1012 seq_printf(m, "[0]R_AX_SCHEDULE_ERR_ISR=0x%08x\n",
1013 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR));
1014 seq_printf(m, "[1]R_AX_PTCL_ISR0=0x%08x\n",
1015 rtw89_read32(rtwdev, R_AX_PTCL_ISR0));
1016 seq_printf(m, "[3]R_AX_DLE_CTRL=0x%08x\n",
1017 rtw89_read32(rtwdev, R_AX_DLE_CTRL));
1018 seq_printf(m, "[4]R_AX_PHYINFO_ERR_ISR=0x%08x\n",
1019 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR));
1020 seq_printf(m, "[5]R_AX_TXPWR_ISR=0x%08x\n",
1021 rtw89_read32(rtwdev, R_AX_TXPWR_ISR));
1022 seq_printf(m, "[6]R_AX_RMAC_ERR_ISR=0x%08x\n",
1023 rtw89_read32(rtwdev, R_AX_RMAC_ERR_ISR));
1024 seq_printf(m, "[7]R_AX_TMAC_ERR_IMR_ISR=0x%08x\n",
1025 rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR));
1026
1027 ret = rtw89_mac_check_mac_en(rtwdev, 1, RTW89_CMAC_SEL);
1028 if (ret) {
1029 seq_puts(m, "[CMAC] : CMAC 1 not enabled\n");
1030 return ret;
1031 }
1032
1033 seq_printf(m, "R_AX_CMAC_ERR_ISR_C1=0x%08x\n",
1034 rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR_C1));
1035 seq_printf(m, "[0]R_AX_SCHEDULE_ERR_ISR_C1=0x%08x\n",
1036 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR_C1));
1037 seq_printf(m, "[1]R_AX_PTCL_ISR0_C1=0x%08x\n",
1038 rtw89_read32(rtwdev, R_AX_PTCL_ISR0_C1));
1039 seq_printf(m, "[3]R_AX_DLE_CTRL_C1=0x%08x\n",
1040 rtw89_read32(rtwdev, R_AX_DLE_CTRL_C1));
1041 seq_printf(m, "[4]R_AX_PHYINFO_ERR_ISR_C1=0x%02x\n",
1042 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR_C1));
1043 seq_printf(m, "[5]R_AX_TXPWR_ISR_C1=0x%08x\n",
1044 rtw89_read32(rtwdev, R_AX_TXPWR_ISR_C1));
1045 seq_printf(m, "[6]R_AX_RMAC_ERR_ISR_C1=0x%08x\n",
1046 rtw89_read32(rtwdev, R_AX_RMAC_ERR_ISR_C1));
1047 seq_printf(m, "[7]R_AX_TMAC_ERR_IMR_ISR_C1=0x%08x\n",
1048 rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR_C1));
1049
1050 return 0;
1051 }
1052
1053 static const struct rtw89_mac_dbg_port_info dbg_port_ptcl_c0 = {
1054 .sel_addr = R_AX_PTCL_DBG,
1055 .sel_byte = 1,
1056 .sel_msk = B_AX_PTCL_DBG_SEL_MASK,
1057 .srt = 0x00,
1058 .end = 0x3F,
1059 .rd_addr = R_AX_PTCL_DBG_INFO,
1060 .rd_byte = 4,
1061 .rd_msk = B_AX_PTCL_DBG_INFO_MASK
1062 };
1063
1064 static const struct rtw89_mac_dbg_port_info dbg_port_ptcl_c1 = {
1065 .sel_addr = R_AX_PTCL_DBG_C1,
1066 .sel_byte = 1,
1067 .sel_msk = B_AX_PTCL_DBG_SEL_MASK,
1068 .srt = 0x00,
1069 .end = 0x3F,
1070 .rd_addr = R_AX_PTCL_DBG_INFO_C1,
1071 .rd_byte = 4,
1072 .rd_msk = B_AX_PTCL_DBG_INFO_MASK
1073 };
1074
1075 static const struct rtw89_mac_dbg_port_info dbg_port_sch_c0 = {
1076 .sel_addr = R_AX_SCH_DBG_SEL,
1077 .sel_byte = 1,
1078 .sel_msk = B_AX_SCH_DBG_SEL_MASK,
1079 .srt = 0x00,
1080 .end = 0x2F,
1081 .rd_addr = R_AX_SCH_DBG,
1082 .rd_byte = 4,
1083 .rd_msk = B_AX_SCHEDULER_DBG_MASK
1084 };
1085
1086 static const struct rtw89_mac_dbg_port_info dbg_port_sch_c1 = {
1087 .sel_addr = R_AX_SCH_DBG_SEL_C1,
1088 .sel_byte = 1,
1089 .sel_msk = B_AX_SCH_DBG_SEL_MASK,
1090 .srt = 0x00,
1091 .end = 0x2F,
1092 .rd_addr = R_AX_SCH_DBG_C1,
1093 .rd_byte = 4,
1094 .rd_msk = B_AX_SCHEDULER_DBG_MASK
1095 };
1096
1097 static const struct rtw89_mac_dbg_port_info dbg_port_tmac_c0 = {
1098 .sel_addr = R_AX_MACTX_DBG_SEL_CNT,
1099 .sel_byte = 1,
1100 .sel_msk = B_AX_DBGSEL_MACTX_MASK,
1101 .srt = 0x00,
1102 .end = 0x19,
1103 .rd_addr = R_AX_DBG_PORT_SEL,
1104 .rd_byte = 4,
1105 .rd_msk = B_AX_DEBUG_ST_MASK
1106 };
1107
1108 static const struct rtw89_mac_dbg_port_info dbg_port_tmac_c1 = {
1109 .sel_addr = R_AX_MACTX_DBG_SEL_CNT_C1,
1110 .sel_byte = 1,
1111 .sel_msk = B_AX_DBGSEL_MACTX_MASK,
1112 .srt = 0x00,
1113 .end = 0x19,
1114 .rd_addr = R_AX_DBG_PORT_SEL,
1115 .rd_byte = 4,
1116 .rd_msk = B_AX_DEBUG_ST_MASK
1117 };
1118
1119 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_c0 = {
1120 .sel_addr = R_AX_RX_DEBUG_SELECT,
1121 .sel_byte = 1,
1122 .sel_msk = B_AX_DEBUG_SEL_MASK,
1123 .srt = 0x00,
1124 .end = 0x58,
1125 .rd_addr = R_AX_DBG_PORT_SEL,
1126 .rd_byte = 4,
1127 .rd_msk = B_AX_DEBUG_ST_MASK
1128 };
1129
1130 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_c1 = {
1131 .sel_addr = R_AX_RX_DEBUG_SELECT_C1,
1132 .sel_byte = 1,
1133 .sel_msk = B_AX_DEBUG_SEL_MASK,
1134 .srt = 0x00,
1135 .end = 0x58,
1136 .rd_addr = R_AX_DBG_PORT_SEL,
1137 .rd_byte = 4,
1138 .rd_msk = B_AX_DEBUG_ST_MASK
1139 };
1140
1141 static const struct rtw89_mac_dbg_port_info dbg_port_rmacst_c0 = {
1142 .sel_addr = R_AX_RX_STATE_MONITOR,
1143 .sel_byte = 1,
1144 .sel_msk = B_AX_STATE_SEL_MASK,
1145 .srt = 0x00,
1146 .end = 0x17,
1147 .rd_addr = R_AX_RX_STATE_MONITOR,
1148 .rd_byte = 4,
1149 .rd_msk = B_AX_RX_STATE_MONITOR_MASK
1150 };
1151
1152 static const struct rtw89_mac_dbg_port_info dbg_port_rmacst_c1 = {
1153 .sel_addr = R_AX_RX_STATE_MONITOR_C1,
1154 .sel_byte = 1,
1155 .sel_msk = B_AX_STATE_SEL_MASK,
1156 .srt = 0x00,
1157 .end = 0x17,
1158 .rd_addr = R_AX_RX_STATE_MONITOR_C1,
1159 .rd_byte = 4,
1160 .rd_msk = B_AX_RX_STATE_MONITOR_MASK
1161 };
1162
1163 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_plcp_c0 = {
1164 .sel_addr = R_AX_RMAC_PLCP_MON,
1165 .sel_byte = 4,
1166 .sel_msk = B_AX_PCLP_MON_SEL_MASK,
1167 .srt = 0x0,
1168 .end = 0xF,
1169 .rd_addr = R_AX_RMAC_PLCP_MON,
1170 .rd_byte = 4,
1171 .rd_msk = B_AX_RMAC_PLCP_MON_MASK
1172 };
1173
1174 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_plcp_c1 = {
1175 .sel_addr = R_AX_RMAC_PLCP_MON_C1,
1176 .sel_byte = 4,
1177 .sel_msk = B_AX_PCLP_MON_SEL_MASK,
1178 .srt = 0x0,
1179 .end = 0xF,
1180 .rd_addr = R_AX_RMAC_PLCP_MON_C1,
1181 .rd_byte = 4,
1182 .rd_msk = B_AX_RMAC_PLCP_MON_MASK
1183 };
1184
1185 static const struct rtw89_mac_dbg_port_info dbg_port_trxptcl_c0 = {
1186 .sel_addr = R_AX_DBGSEL_TRXPTCL,
1187 .sel_byte = 1,
1188 .sel_msk = B_AX_DBGSEL_TRXPTCL_MASK,
1189 .srt = 0x08,
1190 .end = 0x10,
1191 .rd_addr = R_AX_DBG_PORT_SEL,
1192 .rd_byte = 4,
1193 .rd_msk = B_AX_DEBUG_ST_MASK
1194 };
1195
1196 static const struct rtw89_mac_dbg_port_info dbg_port_trxptcl_c1 = {
1197 .sel_addr = R_AX_DBGSEL_TRXPTCL_C1,
1198 .sel_byte = 1,
1199 .sel_msk = B_AX_DBGSEL_TRXPTCL_MASK,
1200 .srt = 0x08,
1201 .end = 0x10,
1202 .rd_addr = R_AX_DBG_PORT_SEL,
1203 .rd_byte = 4,
1204 .rd_msk = B_AX_DEBUG_ST_MASK
1205 };
1206
1207 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infol_c0 = {
1208 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG,
1209 .sel_byte = 1,
1210 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK,
1211 .srt = 0x00,
1212 .end = 0x07,
1213 .rd_addr = R_AX_WMAC_TX_INFO0_DEBUG,
1214 .rd_byte = 4,
1215 .rd_msk = B_AX_TX_CTRL_INFO_P0_MASK
1216 };
1217
1218 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infoh_c0 = {
1219 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG,
1220 .sel_byte = 1,
1221 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK,
1222 .srt = 0x00,
1223 .end = 0x07,
1224 .rd_addr = R_AX_WMAC_TX_INFO1_DEBUG,
1225 .rd_byte = 4,
1226 .rd_msk = B_AX_TX_CTRL_INFO_P1_MASK
1227 };
1228
1229 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infol_c1 = {
1230 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG_C1,
1231 .sel_byte = 1,
1232 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK,
1233 .srt = 0x00,
1234 .end = 0x07,
1235 .rd_addr = R_AX_WMAC_TX_INFO0_DEBUG_C1,
1236 .rd_byte = 4,
1237 .rd_msk = B_AX_TX_CTRL_INFO_P0_MASK
1238 };
1239
1240 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infoh_c1 = {
1241 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG_C1,
1242 .sel_byte = 1,
1243 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK,
1244 .srt = 0x00,
1245 .end = 0x07,
1246 .rd_addr = R_AX_WMAC_TX_INFO1_DEBUG_C1,
1247 .rd_byte = 4,
1248 .rd_msk = B_AX_TX_CTRL_INFO_P1_MASK
1249 };
1250
1251 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infol_c0 = {
1252 .sel_addr = R_AX_WMAC_TX_TF_INFO_0,
1253 .sel_byte = 1,
1254 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK,
1255 .srt = 0x00,
1256 .end = 0x04,
1257 .rd_addr = R_AX_WMAC_TX_TF_INFO_1,
1258 .rd_byte = 4,
1259 .rd_msk = B_AX_WMAC_TX_TF_INFO_P0_MASK
1260 };
1261
1262 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infoh_c0 = {
1263 .sel_addr = R_AX_WMAC_TX_TF_INFO_0,
1264 .sel_byte = 1,
1265 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK,
1266 .srt = 0x00,
1267 .end = 0x04,
1268 .rd_addr = R_AX_WMAC_TX_TF_INFO_2,
1269 .rd_byte = 4,
1270 .rd_msk = B_AX_WMAC_TX_TF_INFO_P1_MASK
1271 };
1272
1273 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infol_c1 = {
1274 .sel_addr = R_AX_WMAC_TX_TF_INFO_0_C1,
1275 .sel_byte = 1,
1276 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK,
1277 .srt = 0x00,
1278 .end = 0x04,
1279 .rd_addr = R_AX_WMAC_TX_TF_INFO_1_C1,
1280 .rd_byte = 4,
1281 .rd_msk = B_AX_WMAC_TX_TF_INFO_P0_MASK
1282 };
1283
1284 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infoh_c1 = {
1285 .sel_addr = R_AX_WMAC_TX_TF_INFO_0_C1,
1286 .sel_byte = 1,
1287 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK,
1288 .srt = 0x00,
1289 .end = 0x04,
1290 .rd_addr = R_AX_WMAC_TX_TF_INFO_2_C1,
1291 .rd_byte = 4,
1292 .rd_msk = B_AX_WMAC_TX_TF_INFO_P1_MASK
1293 };
1294
1295 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_freepg = {
1296 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL,
1297 .sel_byte = 4,
1298 .sel_msk = B_AX_WDE_DFI_DATA_MASK,
1299 .srt = 0x80000000,
1300 .end = 0x80000001,
1301 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA,
1302 .rd_byte = 4,
1303 .rd_msk = B_AX_WDE_DFI_DATA_MASK
1304 };
1305
1306 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_quota = {
1307 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL,
1308 .sel_byte = 4,
1309 .sel_msk = B_AX_WDE_DFI_DATA_MASK,
1310 .srt = 0x80010000,
1311 .end = 0x80010004,
1312 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA,
1313 .rd_byte = 4,
1314 .rd_msk = B_AX_WDE_DFI_DATA_MASK
1315 };
1316
1317 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_pagellt = {
1318 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL,
1319 .sel_byte = 4,
1320 .sel_msk = B_AX_WDE_DFI_DATA_MASK,
1321 .srt = 0x80020000,
1322 .end = 0x80020FFF,
1323 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA,
1324 .rd_byte = 4,
1325 .rd_msk = B_AX_WDE_DFI_DATA_MASK
1326 };
1327
1328 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_pktinfo = {
1329 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL,
1330 .sel_byte = 4,
1331 .sel_msk = B_AX_WDE_DFI_DATA_MASK,
1332 .srt = 0x80030000,
1333 .end = 0x80030FFF,
1334 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA,
1335 .rd_byte = 4,
1336 .rd_msk = B_AX_WDE_DFI_DATA_MASK
1337 };
1338
1339 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_prepkt = {
1340 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL,
1341 .sel_byte = 4,
1342 .sel_msk = B_AX_WDE_DFI_DATA_MASK,
1343 .srt = 0x80040000,
1344 .end = 0x80040FFF,
1345 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA,
1346 .rd_byte = 4,
1347 .rd_msk = B_AX_WDE_DFI_DATA_MASK
1348 };
1349
1350 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_nxtpkt = {
1351 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL,
1352 .sel_byte = 4,
1353 .sel_msk = B_AX_WDE_DFI_DATA_MASK,
1354 .srt = 0x80050000,
1355 .end = 0x80050FFF,
1356 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA,
1357 .rd_byte = 4,
1358 .rd_msk = B_AX_WDE_DFI_DATA_MASK
1359 };
1360
1361 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_qlnktbl = {
1362 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL,
1363 .sel_byte = 4,
1364 .sel_msk = B_AX_WDE_DFI_DATA_MASK,
1365 .srt = 0x80060000,
1366 .end = 0x80060453,
1367 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA,
1368 .rd_byte = 4,
1369 .rd_msk = B_AX_WDE_DFI_DATA_MASK
1370 };
1371
1372 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_qempty = {
1373 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL,
1374 .sel_byte = 4,
1375 .sel_msk = B_AX_WDE_DFI_DATA_MASK,
1376 .srt = 0x80070000,
1377 .end = 0x80070011,
1378 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA,
1379 .rd_byte = 4,
1380 .rd_msk = B_AX_WDE_DFI_DATA_MASK
1381 };
1382
1383 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_freepg = {
1384 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL,
1385 .sel_byte = 4,
1386 .sel_msk = B_AX_PLE_DFI_DATA_MASK,
1387 .srt = 0x80000000,
1388 .end = 0x80000001,
1389 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA,
1390 .rd_byte = 4,
1391 .rd_msk = B_AX_PLE_DFI_DATA_MASK
1392 };
1393
1394 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_quota = {
1395 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL,
1396 .sel_byte = 4,
1397 .sel_msk = B_AX_PLE_DFI_DATA_MASK,
1398 .srt = 0x80010000,
1399 .end = 0x8001000A,
1400 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA,
1401 .rd_byte = 4,
1402 .rd_msk = B_AX_PLE_DFI_DATA_MASK
1403 };
1404
1405 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_pagellt = {
1406 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL,
1407 .sel_byte = 4,
1408 .sel_msk = B_AX_PLE_DFI_DATA_MASK,
1409 .srt = 0x80020000,
1410 .end = 0x80020DBF,
1411 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA,
1412 .rd_byte = 4,
1413 .rd_msk = B_AX_PLE_DFI_DATA_MASK
1414 };
1415
1416 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_pktinfo = {
1417 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL,
1418 .sel_byte = 4,
1419 .sel_msk = B_AX_PLE_DFI_DATA_MASK,
1420 .srt = 0x80030000,
1421 .end = 0x80030DBF,
1422 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA,
1423 .rd_byte = 4,
1424 .rd_msk = B_AX_PLE_DFI_DATA_MASK
1425 };
1426
1427 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_prepkt = {
1428 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL,
1429 .sel_byte = 4,
1430 .sel_msk = B_AX_PLE_DFI_DATA_MASK,
1431 .srt = 0x80040000,
1432 .end = 0x80040DBF,
1433 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA,
1434 .rd_byte = 4,
1435 .rd_msk = B_AX_PLE_DFI_DATA_MASK
1436 };
1437
1438 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_nxtpkt = {
1439 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL,
1440 .sel_byte = 4,
1441 .sel_msk = B_AX_PLE_DFI_DATA_MASK,
1442 .srt = 0x80050000,
1443 .end = 0x80050DBF,
1444 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA,
1445 .rd_byte = 4,
1446 .rd_msk = B_AX_PLE_DFI_DATA_MASK
1447 };
1448
1449 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_qlnktbl = {
1450 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL,
1451 .sel_byte = 4,
1452 .sel_msk = B_AX_PLE_DFI_DATA_MASK,
1453 .srt = 0x80060000,
1454 .end = 0x80060041,
1455 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA,
1456 .rd_byte = 4,
1457 .rd_msk = B_AX_PLE_DFI_DATA_MASK
1458 };
1459
1460 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_qempty = {
1461 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL,
1462 .sel_byte = 4,
1463 .sel_msk = B_AX_PLE_DFI_DATA_MASK,
1464 .srt = 0x80070000,
1465 .end = 0x80070001,
1466 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA,
1467 .rd_byte = 4,
1468 .rd_msk = B_AX_PLE_DFI_DATA_MASK
1469 };
1470
1471 static const struct rtw89_mac_dbg_port_info dbg_port_pktinfo = {
1472 .sel_addr = R_AX_DBG_FUN_INTF_CTL,
1473 .sel_byte = 4,
1474 .sel_msk = B_AX_DFI_DATA_MASK,
1475 .srt = 0x80000000,
1476 .end = 0x8000017f,
1477 .rd_addr = R_AX_DBG_FUN_INTF_DATA,
1478 .rd_byte = 4,
1479 .rd_msk = B_AX_DFI_DATA_MASK
1480 };
1481
1482 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_txdma = {
1483 .sel_addr = R_AX_PCIE_DBG_CTRL,
1484 .sel_byte = 2,
1485 .sel_msk = B_AX_DBG_SEL_MASK,
1486 .srt = 0x00,
1487 .end = 0x03,
1488 .rd_addr = R_AX_DBG_PORT_SEL,
1489 .rd_byte = 4,
1490 .rd_msk = B_AX_DEBUG_ST_MASK
1491 };
1492
1493 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_rxdma = {
1494 .sel_addr = R_AX_PCIE_DBG_CTRL,
1495 .sel_byte = 2,
1496 .sel_msk = B_AX_DBG_SEL_MASK,
1497 .srt = 0x00,
1498 .end = 0x04,
1499 .rd_addr = R_AX_DBG_PORT_SEL,
1500 .rd_byte = 4,
1501 .rd_msk = B_AX_DEBUG_ST_MASK
1502 };
1503
1504 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_cvt = {
1505 .sel_addr = R_AX_PCIE_DBG_CTRL,
1506 .sel_byte = 2,
1507 .sel_msk = B_AX_DBG_SEL_MASK,
1508 .srt = 0x00,
1509 .end = 0x01,
1510 .rd_addr = R_AX_DBG_PORT_SEL,
1511 .rd_byte = 4,
1512 .rd_msk = B_AX_DEBUG_ST_MASK
1513 };
1514
1515 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_cxpl = {
1516 .sel_addr = R_AX_PCIE_DBG_CTRL,
1517 .sel_byte = 2,
1518 .sel_msk = B_AX_DBG_SEL_MASK,
1519 .srt = 0x00,
1520 .end = 0x05,
1521 .rd_addr = R_AX_DBG_PORT_SEL,
1522 .rd_byte = 4,
1523 .rd_msk = B_AX_DEBUG_ST_MASK
1524 };
1525
1526 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_io = {
1527 .sel_addr = R_AX_PCIE_DBG_CTRL,
1528 .sel_byte = 2,
1529 .sel_msk = B_AX_DBG_SEL_MASK,
1530 .srt = 0x00,
1531 .end = 0x05,
1532 .rd_addr = R_AX_DBG_PORT_SEL,
1533 .rd_byte = 4,
1534 .rd_msk = B_AX_DEBUG_ST_MASK
1535 };
1536
1537 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_misc = {
1538 .sel_addr = R_AX_PCIE_DBG_CTRL,
1539 .sel_byte = 2,
1540 .sel_msk = B_AX_DBG_SEL_MASK,
1541 .srt = 0x00,
1542 .end = 0x06,
1543 .rd_addr = R_AX_DBG_PORT_SEL,
1544 .rd_byte = 4,
1545 .rd_msk = B_AX_DEBUG_ST_MASK
1546 };
1547
1548 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_misc2 = {
1549 .sel_addr = R_AX_DBG_CTRL,
1550 .sel_byte = 1,
1551 .sel_msk = B_AX_DBG_SEL0,
1552 .srt = 0x34,
1553 .end = 0x3C,
1554 .rd_addr = R_AX_DBG_PORT_SEL,
1555 .rd_byte = 4,
1556 .rd_msk = B_AX_DEBUG_ST_MASK
1557 };
1558
1559 static const struct rtw89_mac_dbg_port_info *
1560 rtw89_debug_mac_dbg_port_sel(struct seq_file *m,
1561 struct rtw89_dev *rtwdev, u32 sel)
1562 {
1563 const struct rtw89_mac_dbg_port_info *info;
1564 u32 val32;
1565 u16 val16;
1566 u8 val8;
1567
1568 switch (sel) {
1569 case RTW89_DBG_PORT_SEL_PTCL_C0:
1570 info = &dbg_port_ptcl_c0;
1571 val16 = rtw89_read16(rtwdev, R_AX_PTCL_DBG);
1572 val16 |= B_AX_PTCL_DBG_EN;
1573 rtw89_write16(rtwdev, R_AX_PTCL_DBG, val16);
1574 seq_puts(m, "Enable PTCL C0 dbgport.\n");
1575 break;
1576 case RTW89_DBG_PORT_SEL_PTCL_C1:
1577 info = &dbg_port_ptcl_c1;
1578 val16 = rtw89_read16(rtwdev, R_AX_PTCL_DBG_C1);
1579 val16 |= B_AX_PTCL_DBG_EN;
1580 rtw89_write16(rtwdev, R_AX_PTCL_DBG_C1, val16);
1581 seq_puts(m, "Enable PTCL C1 dbgport.\n");
1582 break;
1583 case RTW89_DBG_PORT_SEL_SCH_C0:
1584 info = &dbg_port_sch_c0;
1585 val32 = rtw89_read32(rtwdev, R_AX_SCH_DBG_SEL);
1586 val32 |= B_AX_SCH_DBG_EN;
1587 rtw89_write32(rtwdev, R_AX_SCH_DBG_SEL, val32);
1588 seq_puts(m, "Enable SCH C0 dbgport.\n");
1589 break;
1590 case RTW89_DBG_PORT_SEL_SCH_C1:
1591 info = &dbg_port_sch_c1;
1592 val32 = rtw89_read32(rtwdev, R_AX_SCH_DBG_SEL_C1);
1593 val32 |= B_AX_SCH_DBG_EN;
1594 rtw89_write32(rtwdev, R_AX_SCH_DBG_SEL_C1, val32);
1595 seq_puts(m, "Enable SCH C1 dbgport.\n");
1596 break;
1597 case RTW89_DBG_PORT_SEL_TMAC_C0:
1598 info = &dbg_port_tmac_c0;
1599 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL);
1600 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_TMAC,
1601 B_AX_DBGSEL_TRXPTCL_MASK);
1602 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL, val32);
1603
1604 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
1605 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C0, B_AX_DBG_SEL0);
1606 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C0, B_AX_DBG_SEL1);
1607 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
1608
1609 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1);
1610 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK);
1611 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32);
1612 seq_puts(m, "Enable TMAC C0 dbgport.\n");
1613 break;
1614 case RTW89_DBG_PORT_SEL_TMAC_C1:
1615 info = &dbg_port_tmac_c1;
1616 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1);
1617 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_TMAC,
1618 B_AX_DBGSEL_TRXPTCL_MASK);
1619 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val32);
1620
1621 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
1622 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C1, B_AX_DBG_SEL0);
1623 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C1, B_AX_DBG_SEL1);
1624 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
1625
1626 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1);
1627 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK);
1628 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32);
1629 seq_puts(m, "Enable TMAC C1 dbgport.\n");
1630 break;
1631 case RTW89_DBG_PORT_SEL_RMAC_C0:
1632 info = &dbg_port_rmac_c0;
1633 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL);
1634 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_RMAC,
1635 B_AX_DBGSEL_TRXPTCL_MASK);
1636 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL, val32);
1637
1638 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
1639 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C0, B_AX_DBG_SEL0);
1640 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C0, B_AX_DBG_SEL1);
1641 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
1642
1643 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1);
1644 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK);
1645 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32);
1646
1647 val8 = rtw89_read8(rtwdev, R_AX_DBGSEL_TRXPTCL);
1648 val8 = u8_replace_bits(val8, RMAC_CMAC_DBG_SEL,
1649 B_AX_DBGSEL_TRXPTCL_MASK);
1650 rtw89_write8(rtwdev, R_AX_DBGSEL_TRXPTCL, val8);
1651 seq_puts(m, "Enable RMAC C0 dbgport.\n");
1652 break;
1653 case RTW89_DBG_PORT_SEL_RMAC_C1:
1654 info = &dbg_port_rmac_c1;
1655 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1);
1656 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_RMAC,
1657 B_AX_DBGSEL_TRXPTCL_MASK);
1658 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val32);
1659
1660 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
1661 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C1, B_AX_DBG_SEL0);
1662 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C1, B_AX_DBG_SEL1);
1663 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
1664
1665 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1);
1666 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK);
1667 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32);
1668
1669 val8 = rtw89_read8(rtwdev, R_AX_DBGSEL_TRXPTCL_C1);
1670 val8 = u8_replace_bits(val8, RMAC_CMAC_DBG_SEL,
1671 B_AX_DBGSEL_TRXPTCL_MASK);
1672 rtw89_write8(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val8);
1673 seq_puts(m, "Enable RMAC C1 dbgport.\n");
1674 break;
1675 case RTW89_DBG_PORT_SEL_RMACST_C0:
1676 info = &dbg_port_rmacst_c0;
1677 seq_puts(m, "Enable RMAC state C0 dbgport.\n");
1678 break;
1679 case RTW89_DBG_PORT_SEL_RMACST_C1:
1680 info = &dbg_port_rmacst_c1;
1681 seq_puts(m, "Enable RMAC state C1 dbgport.\n");
1682 break;
1683 case RTW89_DBG_PORT_SEL_RMAC_PLCP_C0:
1684 info = &dbg_port_rmac_plcp_c0;
1685 seq_puts(m, "Enable RMAC PLCP C0 dbgport.\n");
1686 break;
1687 case RTW89_DBG_PORT_SEL_RMAC_PLCP_C1:
1688 info = &dbg_port_rmac_plcp_c1;
1689 seq_puts(m, "Enable RMAC PLCP C1 dbgport.\n");
1690 break;
1691 case RTW89_DBG_PORT_SEL_TRXPTCL_C0:
1692 info = &dbg_port_trxptcl_c0;
1693 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
1694 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C0, B_AX_DBG_SEL0);
1695 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C0, B_AX_DBG_SEL1);
1696 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
1697
1698 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1);
1699 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK);
1700 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32);
1701 seq_puts(m, "Enable TRXPTCL C0 dbgport.\n");
1702 break;
1703 case RTW89_DBG_PORT_SEL_TRXPTCL_C1:
1704 info = &dbg_port_trxptcl_c1;
1705 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
1706 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C1, B_AX_DBG_SEL0);
1707 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C1, B_AX_DBG_SEL1);
1708 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
1709
1710 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1);
1711 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK);
1712 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32);
1713 seq_puts(m, "Enable TRXPTCL C1 dbgport.\n");
1714 break;
1715 case RTW89_DBG_PORT_SEL_TX_INFOL_C0:
1716 info = &dbg_port_tx_infol_c0;
1717 val32 = rtw89_read32(rtwdev, R_AX_TCR1);
1718 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO;
1719 rtw89_write32(rtwdev, R_AX_TCR1, val32);
1720 seq_puts(m, "Enable tx infol dump.\n");
1721 break;
1722 case RTW89_DBG_PORT_SEL_TX_INFOH_C0:
1723 info = &dbg_port_tx_infoh_c0;
1724 val32 = rtw89_read32(rtwdev, R_AX_TCR1);
1725 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO;
1726 rtw89_write32(rtwdev, R_AX_TCR1, val32);
1727 seq_puts(m, "Enable tx infoh dump.\n");
1728 break;
1729 case RTW89_DBG_PORT_SEL_TX_INFOL_C1:
1730 info = &dbg_port_tx_infol_c1;
1731 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1);
1732 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO;
1733 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32);
1734 seq_puts(m, "Enable tx infol dump.\n");
1735 break;
1736 case RTW89_DBG_PORT_SEL_TX_INFOH_C1:
1737 info = &dbg_port_tx_infoh_c1;
1738 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1);
1739 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO;
1740 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32);
1741 seq_puts(m, "Enable tx infoh dump.\n");
1742 break;
1743 case RTW89_DBG_PORT_SEL_TXTF_INFOL_C0:
1744 info = &dbg_port_txtf_infol_c0;
1745 val32 = rtw89_read32(rtwdev, R_AX_TCR1);
1746 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO;
1747 rtw89_write32(rtwdev, R_AX_TCR1, val32);
1748 seq_puts(m, "Enable tx tf infol dump.\n");
1749 break;
1750 case RTW89_DBG_PORT_SEL_TXTF_INFOH_C0:
1751 info = &dbg_port_txtf_infoh_c0;
1752 val32 = rtw89_read32(rtwdev, R_AX_TCR1);
1753 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO;
1754 rtw89_write32(rtwdev, R_AX_TCR1, val32);
1755 seq_puts(m, "Enable tx tf infoh dump.\n");
1756 break;
1757 case RTW89_DBG_PORT_SEL_TXTF_INFOL_C1:
1758 info = &dbg_port_txtf_infol_c1;
1759 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1);
1760 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO;
1761 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32);
1762 seq_puts(m, "Enable tx tf infol dump.\n");
1763 break;
1764 case RTW89_DBG_PORT_SEL_TXTF_INFOH_C1:
1765 info = &dbg_port_txtf_infoh_c1;
1766 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1);
1767 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO;
1768 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32);
1769 seq_puts(m, "Enable tx tf infoh dump.\n");
1770 break;
1771 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG:
1772 info = &dbg_port_wde_bufmgn_freepg;
1773 seq_puts(m, "Enable wde bufmgn freepg dump.\n");
1774 break;
1775 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_QUOTA:
1776 info = &dbg_port_wde_bufmgn_quota;
1777 seq_puts(m, "Enable wde bufmgn quota dump.\n");
1778 break;
1779 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_PAGELLT:
1780 info = &dbg_port_wde_bufmgn_pagellt;
1781 seq_puts(m, "Enable wde bufmgn pagellt dump.\n");
1782 break;
1783 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_PKTINFO:
1784 info = &dbg_port_wde_bufmgn_pktinfo;
1785 seq_puts(m, "Enable wde bufmgn pktinfo dump.\n");
1786 break;
1787 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_PREPKT:
1788 info = &dbg_port_wde_quemgn_prepkt;
1789 seq_puts(m, "Enable wde quemgn prepkt dump.\n");
1790 break;
1791 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_NXTPKT:
1792 info = &dbg_port_wde_quemgn_nxtpkt;
1793 seq_puts(m, "Enable wde quemgn nxtpkt dump.\n");
1794 break;
1795 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_QLNKTBL:
1796 info = &dbg_port_wde_quemgn_qlnktbl;
1797 seq_puts(m, "Enable wde quemgn qlnktbl dump.\n");
1798 break;
1799 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_QEMPTY:
1800 info = &dbg_port_wde_quemgn_qempty;
1801 seq_puts(m, "Enable wde quemgn qempty dump.\n");
1802 break;
1803 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_FREEPG:
1804 info = &dbg_port_ple_bufmgn_freepg;
1805 seq_puts(m, "Enable ple bufmgn freepg dump.\n");
1806 break;
1807 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_QUOTA:
1808 info = &dbg_port_ple_bufmgn_quota;
1809 seq_puts(m, "Enable ple bufmgn quota dump.\n");
1810 break;
1811 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_PAGELLT:
1812 info = &dbg_port_ple_bufmgn_pagellt;
1813 seq_puts(m, "Enable ple bufmgn pagellt dump.\n");
1814 break;
1815 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_PKTINFO:
1816 info = &dbg_port_ple_bufmgn_pktinfo;
1817 seq_puts(m, "Enable ple bufmgn pktinfo dump.\n");
1818 break;
1819 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_PREPKT:
1820 info = &dbg_port_ple_quemgn_prepkt;
1821 seq_puts(m, "Enable ple quemgn prepkt dump.\n");
1822 break;
1823 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_NXTPKT:
1824 info = &dbg_port_ple_quemgn_nxtpkt;
1825 seq_puts(m, "Enable ple quemgn nxtpkt dump.\n");
1826 break;
1827 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_QLNKTBL:
1828 info = &dbg_port_ple_quemgn_qlnktbl;
1829 seq_puts(m, "Enable ple quemgn qlnktbl dump.\n");
1830 break;
1831 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_QEMPTY:
1832 info = &dbg_port_ple_quemgn_qempty;
1833 seq_puts(m, "Enable ple quemgn qempty dump.\n");
1834 break;
1835 case RTW89_DBG_PORT_SEL_PKTINFO:
1836 info = &dbg_port_pktinfo;
1837 seq_puts(m, "Enable pktinfo dump.\n");
1838 break;
1839 case RTW89_DBG_PORT_SEL_PCIE_TXDMA:
1840 info = &dbg_port_pcie_txdma;
1841 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
1842 val32 = u32_replace_bits(val32, PCIE_TXDMA_DBG_SEL, B_AX_DBG_SEL0);
1843 val32 = u32_replace_bits(val32, PCIE_TXDMA_DBG_SEL, B_AX_DBG_SEL1);
1844 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
1845 seq_puts(m, "Enable pcie txdma dump.\n");
1846 break;
1847 case RTW89_DBG_PORT_SEL_PCIE_RXDMA:
1848 info = &dbg_port_pcie_rxdma;
1849 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
1850 val32 = u32_replace_bits(val32, PCIE_RXDMA_DBG_SEL, B_AX_DBG_SEL0);
1851 val32 = u32_replace_bits(val32, PCIE_RXDMA_DBG_SEL, B_AX_DBG_SEL1);
1852 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
1853 seq_puts(m, "Enable pcie rxdma dump.\n");
1854 break;
1855 case RTW89_DBG_PORT_SEL_PCIE_CVT:
1856 info = &dbg_port_pcie_cvt;
1857 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
1858 val32 = u32_replace_bits(val32, PCIE_CVT_DBG_SEL, B_AX_DBG_SEL0);
1859 val32 = u32_replace_bits(val32, PCIE_CVT_DBG_SEL, B_AX_DBG_SEL1);
1860 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
1861 seq_puts(m, "Enable pcie cvt dump.\n");
1862 break;
1863 case RTW89_DBG_PORT_SEL_PCIE_CXPL:
1864 info = &dbg_port_pcie_cxpl;
1865 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
1866 val32 = u32_replace_bits(val32, PCIE_CXPL_DBG_SEL, B_AX_DBG_SEL0);
1867 val32 = u32_replace_bits(val32, PCIE_CXPL_DBG_SEL, B_AX_DBG_SEL1);
1868 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
1869 seq_puts(m, "Enable pcie cxpl dump.\n");
1870 break;
1871 case RTW89_DBG_PORT_SEL_PCIE_IO:
1872 info = &dbg_port_pcie_io;
1873 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
1874 val32 = u32_replace_bits(val32, PCIE_IO_DBG_SEL, B_AX_DBG_SEL0);
1875 val32 = u32_replace_bits(val32, PCIE_IO_DBG_SEL, B_AX_DBG_SEL1);
1876 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
1877 seq_puts(m, "Enable pcie io dump.\n");
1878 break;
1879 case RTW89_DBG_PORT_SEL_PCIE_MISC:
1880 info = &dbg_port_pcie_misc;
1881 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
1882 val32 = u32_replace_bits(val32, PCIE_MISC_DBG_SEL, B_AX_DBG_SEL0);
1883 val32 = u32_replace_bits(val32, PCIE_MISC_DBG_SEL, B_AX_DBG_SEL1);
1884 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
1885 seq_puts(m, "Enable pcie misc dump.\n");
1886 break;
1887 case RTW89_DBG_PORT_SEL_PCIE_MISC2:
1888 info = &dbg_port_pcie_misc2;
1889 val16 = rtw89_read16(rtwdev, R_AX_PCIE_DBG_CTRL);
1890 val16 = u16_replace_bits(val16, PCIE_MISC2_DBG_SEL,
1891 B_AX_DBG_SEL_MASK);
1892 rtw89_write16(rtwdev, R_AX_PCIE_DBG_CTRL, val16);
1893 seq_puts(m, "Enable pcie misc2 dump.\n");
1894 break;
1895 default:
1896 seq_puts(m, "Dbg port select err\n");
1897 return NULL;
1898 }
1899
1900 return info;
1901 }
1902
1903 static bool is_dbg_port_valid(struct rtw89_dev *rtwdev, u32 sel)
1904 {
1905 if (rtwdev->hci.type != RTW89_HCI_TYPE_PCIE &&
1906 sel >= RTW89_DBG_PORT_SEL_PCIE_TXDMA &&
1907 sel <= RTW89_DBG_PORT_SEL_PCIE_MISC2)
1908 return false;
1909 if (rtwdev->chip->chip_id == RTL8852B &&
1910 sel >= RTW89_DBG_PORT_SEL_PTCL_C1 &&
1911 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C1)
1912 return false;
1913 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL) &&
1914 sel >= RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG &&
1915 sel <= RTW89_DBG_PORT_SEL_PKTINFO)
1916 return false;
1917 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_CMAC_SEL) &&
1918 sel >= RTW89_DBG_PORT_SEL_PTCL_C0 &&
1919 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C0)
1920 return false;
1921 if (rtw89_mac_check_mac_en(rtwdev, 1, RTW89_CMAC_SEL) &&
1922 sel >= RTW89_DBG_PORT_SEL_PTCL_C1 &&
1923 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C1)
1924 return false;
1925
1926 return true;
1927 }
1928
1929 static int rtw89_debug_mac_dbg_port_dump(struct rtw89_dev *rtwdev,
1930 struct seq_file *m, u32 sel)
1931 {
1932 const struct rtw89_mac_dbg_port_info *info;
1933 u8 val8;
1934 u16 val16;
1935 u32 val32;
1936 u32 i;
1937
1938 info = rtw89_debug_mac_dbg_port_sel(m, rtwdev, sel);
1939 if (!info) {
1940 rtw89_err(rtwdev, "failed to select debug port %d\n", sel);
1941 return -EINVAL;
1942 }
1943
1944 #define case_DBG_SEL(__sel) \
1945 case RTW89_DBG_PORT_SEL_##__sel: \
1946 seq_puts(m, "Dump debug port " #__sel ":\n"); \
1947 break
1948
1949 switch (sel) {
1950 case_DBG_SEL(PTCL_C0);
1951 case_DBG_SEL(PTCL_C1);
1952 case_DBG_SEL(SCH_C0);
1953 case_DBG_SEL(SCH_C1);
1954 case_DBG_SEL(TMAC_C0);
1955 case_DBG_SEL(TMAC_C1);
1956 case_DBG_SEL(RMAC_C0);
1957 case_DBG_SEL(RMAC_C1);
1958 case_DBG_SEL(RMACST_C0);
1959 case_DBG_SEL(RMACST_C1);
1960 case_DBG_SEL(TRXPTCL_C0);
1961 case_DBG_SEL(TRXPTCL_C1);
1962 case_DBG_SEL(TX_INFOL_C0);
1963 case_DBG_SEL(TX_INFOH_C0);
1964 case_DBG_SEL(TX_INFOL_C1);
1965 case_DBG_SEL(TX_INFOH_C1);
1966 case_DBG_SEL(TXTF_INFOL_C0);
1967 case_DBG_SEL(TXTF_INFOH_C0);
1968 case_DBG_SEL(TXTF_INFOL_C1);
1969 case_DBG_SEL(TXTF_INFOH_C1);
1970 case_DBG_SEL(WDE_BUFMGN_FREEPG);
1971 case_DBG_SEL(WDE_BUFMGN_QUOTA);
1972 case_DBG_SEL(WDE_BUFMGN_PAGELLT);
1973 case_DBG_SEL(WDE_BUFMGN_PKTINFO);
1974 case_DBG_SEL(WDE_QUEMGN_PREPKT);
1975 case_DBG_SEL(WDE_QUEMGN_NXTPKT);
1976 case_DBG_SEL(WDE_QUEMGN_QLNKTBL);
1977 case_DBG_SEL(WDE_QUEMGN_QEMPTY);
1978 case_DBG_SEL(PLE_BUFMGN_FREEPG);
1979 case_DBG_SEL(PLE_BUFMGN_QUOTA);
1980 case_DBG_SEL(PLE_BUFMGN_PAGELLT);
1981 case_DBG_SEL(PLE_BUFMGN_PKTINFO);
1982 case_DBG_SEL(PLE_QUEMGN_PREPKT);
1983 case_DBG_SEL(PLE_QUEMGN_NXTPKT);
1984 case_DBG_SEL(PLE_QUEMGN_QLNKTBL);
1985 case_DBG_SEL(PLE_QUEMGN_QEMPTY);
1986 case_DBG_SEL(PKTINFO);
1987 case_DBG_SEL(PCIE_TXDMA);
1988 case_DBG_SEL(PCIE_RXDMA);
1989 case_DBG_SEL(PCIE_CVT);
1990 case_DBG_SEL(PCIE_CXPL);
1991 case_DBG_SEL(PCIE_IO);
1992 case_DBG_SEL(PCIE_MISC);
1993 case_DBG_SEL(PCIE_MISC2);
1994 }
1995
1996 #undef case_DBG_SEL
1997
1998 seq_printf(m, "Sel addr = 0x%X\n", info->sel_addr);
1999 seq_printf(m, "Read addr = 0x%X\n", info->rd_addr);
2000
2001 for (i = info->srt; i <= info->end; i++) {
2002 switch (info->sel_byte) {
2003 case 1:
2004 default:
2005 rtw89_write8_mask(rtwdev, info->sel_addr,
2006 info->sel_msk, i);
2007 seq_printf(m, "0x%02X: ", i);
2008 break;
2009 case 2:
2010 rtw89_write16_mask(rtwdev, info->sel_addr,
2011 info->sel_msk, i);
2012 seq_printf(m, "0x%04X: ", i);
2013 break;
2014 case 4:
2015 rtw89_write32_mask(rtwdev, info->sel_addr,
2016 info->sel_msk, i);
2017 seq_printf(m, "0x%04X: ", i);
2018 break;
2019 }
2020
2021 udelay(10);
2022
2023 switch (info->rd_byte) {
2024 case 1:
2025 default:
2026 val8 = rtw89_read8_mask(rtwdev,
2027 info->rd_addr, info->rd_msk);
2028 seq_printf(m, "0x%02X\n", val8);
2029 break;
2030 case 2:
2031 val16 = rtw89_read16_mask(rtwdev,
2032 info->rd_addr, info->rd_msk);
2033 seq_printf(m, "0x%04X\n", val16);
2034 break;
2035 case 4:
2036 val32 = rtw89_read32_mask(rtwdev,
2037 info->rd_addr, info->rd_msk);
2038 seq_printf(m, "0x%08X\n", val32);
2039 break;
2040 }
2041 }
2042
2043 return 0;
2044 }
2045
2046 static int rtw89_debug_mac_dump_dbg_port(struct rtw89_dev *rtwdev,
2047 struct seq_file *m)
2048 {
2049 u32 sel;
2050 int ret = 0;
2051
2052 for (sel = RTW89_DBG_PORT_SEL_PTCL_C0;
2053 sel < RTW89_DBG_PORT_SEL_LAST; sel++) {
2054 if (!is_dbg_port_valid(rtwdev, sel))
2055 continue;
2056 ret = rtw89_debug_mac_dbg_port_dump(rtwdev, m, sel);
2057 if (ret) {
2058 rtw89_err(rtwdev,
2059 "failed to dump debug port %d\n", sel);
2060 break;
2061 }
2062 }
2063
2064 return ret;
2065 }
2066
2067 static int
2068 rtw89_debug_priv_mac_dbg_port_dump_get(struct seq_file *m, void *v)
2069 {
2070 struct rtw89_debugfs_priv *debugfs_priv = m->private;
2071 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
2072
2073 if (debugfs_priv->dbgpkg_en.ss_dbg)
2074 rtw89_debug_mac_dump_ss_dbg(rtwdev, m);
2075 if (debugfs_priv->dbgpkg_en.dle_dbg)
2076 rtw89_debug_mac_dump_dle_dbg(rtwdev, m);
2077 if (debugfs_priv->dbgpkg_en.dmac_dbg)
2078 rtw89_debug_mac_dump_dmac_dbg(rtwdev, m);
2079 if (debugfs_priv->dbgpkg_en.cmac_dbg)
2080 rtw89_debug_mac_dump_cmac_dbg(rtwdev, m);
2081 if (debugfs_priv->dbgpkg_en.dbg_port)
2082 rtw89_debug_mac_dump_dbg_port(rtwdev, m);
2083
2084 return 0;
2085 };
2086
2087 static u8 *rtw89_hex2bin_user(struct rtw89_dev *rtwdev,
2088 const char __user *user_buf, size_t count)
2089 {
2090 char *buf;
2091 u8 *bin;
2092 int num;
2093 int err = 0;
2094
2095 buf = memdup_user(user_buf, count);
2096 if (IS_ERR(buf))
2097 return buf;
2098
2099 num = count / 2;
2100 bin = kmalloc(num, GFP_KERNEL);
2101 if (!bin) {
2102 err = -EFAULT;
2103 goto out;
2104 }
2105
2106 if (hex2bin(bin, buf, num)) {
2107 rtw89_info(rtwdev, "valid format: H1H2H3...\n");
2108 kfree(bin);
2109 err = -EINVAL;
2110 }
2111
2112 out:
2113 kfree(buf);
2114
2115 return err ? ERR_PTR(err) : bin;
2116 }
2117
2118 static ssize_t rtw89_debug_priv_send_h2c_set(struct file *filp,
2119 const char __user *user_buf,
2120 size_t count, loff_t *loff)
2121 {
2122 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data;
2123 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
2124 u8 *h2c;
2125 u16 h2c_len = count / 2;
2126
2127 h2c = rtw89_hex2bin_user(rtwdev, user_buf, count);
2128 if (IS_ERR(h2c))
2129 return -EFAULT;
2130
2131 rtw89_fw_h2c_raw(rtwdev, h2c, h2c_len);
2132
2133 kfree(h2c);
2134
2135 return count;
2136 }
2137
2138 static int
2139 rtw89_debug_priv_early_h2c_get(struct seq_file *m, void *v)
2140 {
2141 struct rtw89_debugfs_priv *debugfs_priv = m->private;
2142 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
2143 struct rtw89_early_h2c *early_h2c;
2144 int seq = 0;
2145
2146 mutex_lock(&rtwdev->mutex);
2147 list_for_each_entry(early_h2c, &rtwdev->early_h2c_list, list)
2148 seq_printf(m, "%d: %*ph\n", ++seq, early_h2c->h2c_len, early_h2c->h2c);
2149 mutex_unlock(&rtwdev->mutex);
2150
2151 return 0;
2152 }
2153
2154 static ssize_t
2155 rtw89_debug_priv_early_h2c_set(struct file *filp, const char __user *user_buf,
2156 size_t count, loff_t *loff)
2157 {
2158 struct seq_file *m = (struct seq_file *)filp->private_data;
2159 struct rtw89_debugfs_priv *debugfs_priv = m->private;
2160 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
2161 struct rtw89_early_h2c *early_h2c;
2162 u8 *h2c;
2163 u16 h2c_len = count / 2;
2164
2165 h2c = rtw89_hex2bin_user(rtwdev, user_buf, count);
2166 if (IS_ERR(h2c))
2167 return -EFAULT;
2168
2169 if (h2c_len >= 2 && h2c[0] == 0x00 && h2c[1] == 0x00) {
2170 kfree(h2c);
2171 rtw89_fw_free_all_early_h2c(rtwdev);
2172 goto out;
2173 }
2174
2175 early_h2c = kmalloc(sizeof(*early_h2c), GFP_KERNEL);
2176 if (!early_h2c) {
2177 kfree(h2c);
2178 return -EFAULT;
2179 }
2180
2181 early_h2c->h2c = h2c;
2182 early_h2c->h2c_len = h2c_len;
2183
2184 mutex_lock(&rtwdev->mutex);
2185 list_add_tail(&early_h2c->list, &rtwdev->early_h2c_list);
2186 mutex_unlock(&rtwdev->mutex);
2187
2188 out:
2189 return count;
2190 }
2191
2192 static int
2193 rtw89_debug_priv_fw_crash_get(struct seq_file *m, void *v)
2194 {
2195 struct rtw89_debugfs_priv *debugfs_priv = m->private;
2196 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
2197
2198 seq_printf(m, "%d\n",
2199 test_bit(RTW89_FLAG_RESTART_TRIGGER, rtwdev->flags));
2200 return 0;
2201 }
2202
2203 static ssize_t
2204 rtw89_debug_priv_fw_crash_set(struct file *filp, const char __user *user_buf,
2205 size_t count, loff_t *loff)
2206 {
2207 struct seq_file *m = (struct seq_file *)filp->private_data;
2208 struct rtw89_debugfs_priv *debugfs_priv = m->private;
2209 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
2210 bool fw_crash;
2211 int ret;
2212
2213 if (!RTW89_CHK_FW_FEATURE(CRASH_TRIGGER, &rtwdev->fw))
2214 return -EOPNOTSUPP;
2215
2216 ret = kstrtobool_from_user(user_buf, count, &fw_crash);
2217 if (ret)
2218 return -EINVAL;
2219
2220 if (!fw_crash)
2221 return -EINVAL;
2222
2223 mutex_lock(&rtwdev->mutex);
2224 set_bit(RTW89_FLAG_RESTART_TRIGGER, rtwdev->flags);
2225 ret = rtw89_fw_h2c_trigger_cpu_exception(rtwdev);
2226 mutex_unlock(&rtwdev->mutex);
2227
2228 if (ret)
2229 return ret;
2230
2231 return count;
2232 }
2233
2234 static int rtw89_debug_priv_btc_info_get(struct seq_file *m, void *v)
2235 {
2236 struct rtw89_debugfs_priv *debugfs_priv = m->private;
2237 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
2238
2239 rtw89_btc_dump_info(rtwdev, m);
2240
2241 return 0;
2242 }
2243
2244 static ssize_t rtw89_debug_priv_btc_manual_set(struct file *filp,
2245 const char __user *user_buf,
2246 size_t count, loff_t *loff)
2247 {
2248 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data;
2249 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
2250 struct rtw89_btc *btc = &rtwdev->btc;
2251 bool btc_manual;
2252
2253 if (kstrtobool_from_user(user_buf, count, &btc_manual))
2254 goto out;
2255
2256 btc->ctrl.manual = btc_manual;
2257 out:
2258 return count;
2259 }
2260
2261 static ssize_t rtw89_debug_fw_log_btc_manual_set(struct file *filp,
2262 const char __user *user_buf,
2263 size_t count, loff_t *loff)
2264 {
2265 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data;
2266 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
2267 struct rtw89_fw_info *fw_info = &rtwdev->fw;
2268 bool fw_log_manual;
2269
2270 if (kstrtobool_from_user(user_buf, count, &fw_log_manual))
2271 goto out;
2272
2273 mutex_lock(&rtwdev->mutex);
2274 fw_info->fw_log_enable = fw_log_manual;
2275 rtw89_fw_h2c_fw_log(rtwdev, fw_log_manual);
2276 mutex_unlock(&rtwdev->mutex);
2277 out:
2278 return count;
2279 }
2280
2281 static void rtw89_sta_info_get_iter(void *data, struct ieee80211_sta *sta)
2282 {
2283 static const char * const he_gi_str[] = {
2284 [NL80211_RATE_INFO_HE_GI_0_8] = "0.8",
2285 [NL80211_RATE_INFO_HE_GI_1_6] = "1.6",
2286 [NL80211_RATE_INFO_HE_GI_3_2] = "3.2",
2287 };
2288 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv;
2289 struct rate_info *rate = &rtwsta->ra_report.txrate;
2290 struct ieee80211_rx_status *status = &rtwsta->rx_status;
2291 struct seq_file *m = (struct seq_file *)data;
2292 u8 rssi;
2293
2294 seq_printf(m, "TX rate [%d]: ", rtwsta->mac_id);
2295
2296 if (rate->flags & RATE_INFO_FLAGS_MCS)
2297 seq_printf(m, "HT MCS-%d%s", rate->mcs,
2298 rate->flags & RATE_INFO_FLAGS_SHORT_GI ? " SGI" : "");
2299 else if (rate->flags & RATE_INFO_FLAGS_VHT_MCS)
2300 seq_printf(m, "VHT %dSS MCS-%d%s", rate->nss, rate->mcs,
2301 rate->flags & RATE_INFO_FLAGS_SHORT_GI ? " SGI" : "");
2302 else if (rate->flags & RATE_INFO_FLAGS_HE_MCS)
2303 seq_printf(m, "HE %dSS MCS-%d GI:%s", rate->nss, rate->mcs,
2304 rate->he_gi <= NL80211_RATE_INFO_HE_GI_3_2 ?
2305 he_gi_str[rate->he_gi] : "N/A");
2306 else
2307 seq_printf(m, "Legacy %d", rate->legacy);
2308 seq_printf(m, "\t(hw_rate=0x%x)", rtwsta->ra_report.hw_rate);
2309 seq_printf(m, "\t==> agg_wait=%d (%d)\n", rtwsta->max_agg_wait,
2310 sta->max_rc_amsdu_len);
2311
2312 seq_printf(m, "RX rate [%d]: ", rtwsta->mac_id);
2313
2314 switch (status->encoding) {
2315 case RX_ENC_LEGACY:
2316 seq_printf(m, "Legacy %d", status->rate_idx +
2317 (status->band != NL80211_BAND_2GHZ ? 4 : 0));
2318 break;
2319 case RX_ENC_HT:
2320 seq_printf(m, "HT MCS-%d%s", status->rate_idx,
2321 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? " SGI" : "");
2322 break;
2323 case RX_ENC_VHT:
2324 seq_printf(m, "VHT %dSS MCS-%d%s", status->nss, status->rate_idx,
2325 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? " SGI" : "");
2326 break;
2327 case RX_ENC_HE:
2328 seq_printf(m, "HE %dSS MCS-%d GI:%s", status->nss, status->rate_idx,
2329 status->he_gi <= NL80211_RATE_INFO_HE_GI_3_2 ?
2330 he_gi_str[rate->he_gi] : "N/A");
2331 break;
2332 }
2333 seq_printf(m, "\t(hw_rate=0x%x)\n", rtwsta->rx_hw_rate);
2334
2335 rssi = ewma_rssi_read(&rtwsta->avg_rssi);
2336 seq_printf(m, "RSSI: %d dBm (raw=%d, prev=%d)\n",
2337 RTW89_RSSI_RAW_TO_DBM(rssi), rssi, rtwsta->prev_rssi);
2338 }
2339
2340 static void
2341 rtw89_debug_append_rx_rate(struct seq_file *m, struct rtw89_pkt_stat *pkt_stat,
2342 enum rtw89_hw_rate first_rate, int len)
2343 {
2344 int i;
2345
2346 for (i = 0; i < len; i++)
2347 seq_printf(m, "%s%u", i == 0 ? "" : ", ",
2348 pkt_stat->rx_rate_cnt[first_rate + i]);
2349 }
2350
2351 static const struct rtw89_rx_rate_cnt_info {
2352 enum rtw89_hw_rate first_rate;
2353 int len;
2354 int ext;
2355 const char *rate_mode;
2356 } rtw89_rx_rate_cnt_infos[] = {
2357 {RTW89_HW_RATE_CCK1, 4, 0, "Legacy:"},
2358 {RTW89_HW_RATE_OFDM6, 8, 0, "OFDM:"},
2359 {RTW89_HW_RATE_MCS0, 8, 0, "HT 0:"},
2360 {RTW89_HW_RATE_MCS8, 8, 0, "HT 1:"},
2361 {RTW89_HW_RATE_VHT_NSS1_MCS0, 10, 2, "VHT 1SS:"},
2362 {RTW89_HW_RATE_VHT_NSS2_MCS0, 10, 2, "VHT 2SS:"},
2363 {RTW89_HW_RATE_HE_NSS1_MCS0, 12, 0, "HE 1SS:"},
2364 {RTW89_HW_RATE_HE_NSS2_MCS0, 12, 0, "HE 2ss:"},
2365 };
2366
2367 static int rtw89_debug_priv_phy_info_get(struct seq_file *m, void *v)
2368 {
2369 struct rtw89_debugfs_priv *debugfs_priv = m->private;
2370 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
2371 struct rtw89_traffic_stats *stats = &rtwdev->stats;
2372 struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.last_pkt_stat;
2373 const struct rtw89_rx_rate_cnt_info *info;
2374 int i;
2375
2376 seq_printf(m, "TP TX: %u [%u] Mbps (lv: %d), RX: %u [%u] Mbps (lv: %d)\n",
2377 stats->tx_throughput, stats->tx_throughput_raw, stats->tx_tfc_lv,
2378 stats->rx_throughput, stats->rx_throughput_raw, stats->rx_tfc_lv);
2379 seq_printf(m, "Beacon: %u, TF: %u\n", pkt_stat->beacon_nr,
2380 stats->rx_tf_periodic);
2381 seq_printf(m, "Avg packet length: TX=%u, RX=%u\n", stats->tx_avg_len,
2382 stats->rx_avg_len);
2383
2384 seq_puts(m, "RX count:\n");
2385 for (i = 0; i < ARRAY_SIZE(rtw89_rx_rate_cnt_infos); i++) {
2386 info = &rtw89_rx_rate_cnt_infos[i];
2387 seq_printf(m, "%10s [", info->rate_mode);
2388 rtw89_debug_append_rx_rate(m, pkt_stat,
2389 info->first_rate, info->len);
2390 if (info->ext) {
2391 seq_puts(m, "][");
2392 rtw89_debug_append_rx_rate(m, pkt_stat,
2393 info->first_rate + info->len, info->ext);
2394 }
2395 seq_puts(m, "]\n");
2396 }
2397
2398 ieee80211_iterate_stations_atomic(rtwdev->hw, rtw89_sta_info_get_iter, m);
2399
2400 return 0;
2401 }
2402
2403 static void rtw89_dump_addr_cam(struct seq_file *m,
2404 struct rtw89_addr_cam_entry *addr_cam)
2405 {
2406 struct rtw89_sec_cam_entry *sec_entry;
2407 int i;
2408
2409 seq_printf(m, "\taddr_cam_idx=%u\n", addr_cam->addr_cam_idx);
2410 seq_printf(m, "\t-> bssid_cam_idx=%u\n", addr_cam->bssid_cam_idx);
2411 seq_printf(m, "\tsec_cam_bitmap=%*ph\n", (int)sizeof(addr_cam->sec_cam_map),
2412 addr_cam->sec_cam_map);
2413 for (i = 0; i < RTW89_SEC_CAM_IN_ADDR_CAM; i++) {
2414 sec_entry = addr_cam->sec_entries[i];
2415 if (!sec_entry)
2416 continue;
2417 seq_printf(m, "\tsec[%d]: sec_cam_idx %u", i, sec_entry->sec_cam_idx);
2418 if (sec_entry->ext_key)
2419 seq_printf(m, ", %u", sec_entry->sec_cam_idx + 1);
2420 seq_puts(m, "\n");
2421 }
2422 }
2423
2424 static
2425 void rtw89_vif_ids_get_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
2426 {
2427 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
2428 struct seq_file *m = (struct seq_file *)data;
2429 struct rtw89_bssid_cam_entry *bssid_cam = &rtwvif->bssid_cam;
2430
2431 seq_printf(m, "VIF [%d] %pM\n", rtwvif->mac_id, rtwvif->mac_addr);
2432 seq_printf(m, "\tbssid_cam_idx=%u\n", bssid_cam->bssid_cam_idx);
2433 rtw89_dump_addr_cam(m, &rtwvif->addr_cam);
2434 }
2435
2436 static void rtw89_sta_ids_get_iter(void *data, struct ieee80211_sta *sta)
2437 {
2438 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv;
2439 struct seq_file *m = (struct seq_file *)data;
2440
2441 seq_printf(m, "STA [%d] %pM %s\n", rtwsta->mac_id, sta->addr,
2442 sta->tdls ? "(TDLS)" : "");
2443 rtw89_dump_addr_cam(m, &rtwsta->addr_cam);
2444 }
2445
2446 static int rtw89_debug_priv_stations_get(struct seq_file *m, void *v)
2447 {
2448 struct rtw89_debugfs_priv *debugfs_priv = m->private;
2449 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
2450 struct rtw89_cam_info *cam_info = &rtwdev->cam_info;
2451
2452 seq_puts(m, "map:\n");
2453 seq_printf(m, "\tmac_id: %*ph\n", (int)sizeof(rtwdev->mac_id_map),
2454 rtwdev->mac_id_map);
2455 seq_printf(m, "\taddr_cam: %*ph\n", (int)sizeof(cam_info->addr_cam_map),
2456 cam_info->addr_cam_map);
2457 seq_printf(m, "\tbssid_cam: %*ph\n", (int)sizeof(cam_info->bssid_cam_map),
2458 cam_info->bssid_cam_map);
2459 seq_printf(m, "\tsec_cam: %*ph\n", (int)sizeof(cam_info->sec_cam_map),
2460 cam_info->sec_cam_map);
2461
2462 ieee80211_iterate_active_interfaces_atomic(rtwdev->hw,
2463 IEEE80211_IFACE_ITER_NORMAL, rtw89_vif_ids_get_iter, m);
2464
2465 ieee80211_iterate_stations_atomic(rtwdev->hw, rtw89_sta_ids_get_iter, m);
2466
2467 return 0;
2468 }
2469
2470 static struct rtw89_debugfs_priv rtw89_debug_priv_read_reg = {
2471 .cb_read = rtw89_debug_priv_read_reg_get,
2472 .cb_write = rtw89_debug_priv_read_reg_select,
2473 };
2474
2475 static struct rtw89_debugfs_priv rtw89_debug_priv_write_reg = {
2476 .cb_write = rtw89_debug_priv_write_reg_set,
2477 };
2478
2479 static struct rtw89_debugfs_priv rtw89_debug_priv_read_rf = {
2480 .cb_read = rtw89_debug_priv_read_rf_get,
2481 .cb_write = rtw89_debug_priv_read_rf_select,
2482 };
2483
2484 static struct rtw89_debugfs_priv rtw89_debug_priv_write_rf = {
2485 .cb_write = rtw89_debug_priv_write_rf_set,
2486 };
2487
2488 static struct rtw89_debugfs_priv rtw89_debug_priv_rf_reg_dump = {
2489 .cb_read = rtw89_debug_priv_rf_reg_dump_get,
2490 };
2491
2492 static struct rtw89_debugfs_priv rtw89_debug_priv_txpwr_table = {
2493 .cb_read = rtw89_debug_priv_txpwr_table_get,
2494 };
2495
2496 static struct rtw89_debugfs_priv rtw89_debug_priv_mac_reg_dump = {
2497 .cb_read = rtw89_debug_priv_mac_reg_dump_get,
2498 .cb_write = rtw89_debug_priv_mac_reg_dump_select,
2499 };
2500
2501 static struct rtw89_debugfs_priv rtw89_debug_priv_mac_mem_dump = {
2502 .cb_read = rtw89_debug_priv_mac_mem_dump_get,
2503 .cb_write = rtw89_debug_priv_mac_mem_dump_select,
2504 };
2505
2506 static struct rtw89_debugfs_priv rtw89_debug_priv_mac_dbg_port_dump = {
2507 .cb_read = rtw89_debug_priv_mac_dbg_port_dump_get,
2508 .cb_write = rtw89_debug_priv_mac_dbg_port_dump_select,
2509 };
2510
2511 static struct rtw89_debugfs_priv rtw89_debug_priv_send_h2c = {
2512 .cb_write = rtw89_debug_priv_send_h2c_set,
2513 };
2514
2515 static struct rtw89_debugfs_priv rtw89_debug_priv_early_h2c = {
2516 .cb_read = rtw89_debug_priv_early_h2c_get,
2517 .cb_write = rtw89_debug_priv_early_h2c_set,
2518 };
2519
2520 static struct rtw89_debugfs_priv rtw89_debug_priv_fw_crash = {
2521 .cb_read = rtw89_debug_priv_fw_crash_get,
2522 .cb_write = rtw89_debug_priv_fw_crash_set,
2523 };
2524
2525 static struct rtw89_debugfs_priv rtw89_debug_priv_btc_info = {
2526 .cb_read = rtw89_debug_priv_btc_info_get,
2527 };
2528
2529 static struct rtw89_debugfs_priv rtw89_debug_priv_btc_manual = {
2530 .cb_write = rtw89_debug_priv_btc_manual_set,
2531 };
2532
2533 static struct rtw89_debugfs_priv rtw89_debug_priv_fw_log_manual = {
2534 .cb_write = rtw89_debug_fw_log_btc_manual_set,
2535 };
2536
2537 static struct rtw89_debugfs_priv rtw89_debug_priv_phy_info = {
2538 .cb_read = rtw89_debug_priv_phy_info_get,
2539 };
2540
2541 static struct rtw89_debugfs_priv rtw89_debug_priv_stations = {
2542 .cb_read = rtw89_debug_priv_stations_get,
2543 };
2544
2545 #define rtw89_debugfs_add(name, mode, fopname, parent) \
2546 do { \
2547 rtw89_debug_priv_ ##name.rtwdev = rtwdev; \
2548 if (!debugfs_create_file(#name, mode, \
2549 parent, &rtw89_debug_priv_ ##name, \
2550 &file_ops_ ##fopname)) \
2551 pr_debug("Unable to initialize debugfs:%s\n", #name); \
2552 } while (0)
2553
2554 #define rtw89_debugfs_add_w(name) \
2555 rtw89_debugfs_add(name, S_IFREG | 0222, single_w, debugfs_topdir)
2556 #define rtw89_debugfs_add_rw(name) \
2557 rtw89_debugfs_add(name, S_IFREG | 0666, common_rw, debugfs_topdir)
2558 #define rtw89_debugfs_add_r(name) \
2559 rtw89_debugfs_add(name, S_IFREG | 0444, single_r, debugfs_topdir)
2560
2561 void rtw89_debugfs_init(struct rtw89_dev *rtwdev)
2562 {
2563 struct dentry *debugfs_topdir;
2564
2565 debugfs_topdir = debugfs_create_dir("rtw89",
2566 rtwdev->hw->wiphy->debugfsdir);
2567
2568 rtw89_debugfs_add_rw(read_reg);
2569 rtw89_debugfs_add_w(write_reg);
2570 rtw89_debugfs_add_rw(read_rf);
2571 rtw89_debugfs_add_w(write_rf);
2572 rtw89_debugfs_add_r(rf_reg_dump);
2573 rtw89_debugfs_add_r(txpwr_table);
2574 rtw89_debugfs_add_rw(mac_reg_dump);
2575 rtw89_debugfs_add_rw(mac_mem_dump);
2576 rtw89_debugfs_add_rw(mac_dbg_port_dump);
2577 rtw89_debugfs_add_w(send_h2c);
2578 rtw89_debugfs_add_rw(early_h2c);
2579 rtw89_debugfs_add_rw(fw_crash);
2580 rtw89_debugfs_add_r(btc_info);
2581 rtw89_debugfs_add_w(btc_manual);
2582 rtw89_debugfs_add_w(fw_log_manual);
2583 rtw89_debugfs_add_r(phy_info);
2584 rtw89_debugfs_add_r(stations);
2585 }
2586 #endif
2587
2588 #ifdef CONFIG_RTW89_DEBUGMSG
2589 void __rtw89_debug(struct rtw89_dev *rtwdev,
2590 enum rtw89_debug_mask mask,
2591 const char *fmt, ...)
2592 {
2593 struct va_format vaf = {
2594 .fmt = fmt,
2595 };
2596
2597 va_list args;
2598
2599 va_start(args, fmt);
2600 vaf.va = &args;
2601
2602 if (rtw89_debug_mask & mask)
2603 dev_printk(KERN_DEBUG, rtwdev->dev, "%pV", &vaf);
2604
2605 va_end(args);
2606 }
2607 EXPORT_SYMBOL(__rtw89_debug);
2608 #endif
