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0005 #ifndef __RTW_TX_H_
0006 #define __RTW_TX_H_
0007
0008 #define RTK_TX_MAX_AGG_NUM_MASK 0x1f
0009
0010 #define RTW_TX_PROBE_TIMEOUT msecs_to_jiffies(500)
0011
0012 #define SET_TX_DESC_TXPKTSIZE(txdesc, value) \
0013 le32p_replace_bits((__le32 *)(txdesc) + 0x00, value, GENMASK(15, 0))
0014 #define SET_TX_DESC_OFFSET(txdesc, value) \
0015 le32p_replace_bits((__le32 *)(txdesc) + 0x00, value, GENMASK(23, 16))
0016 #define SET_TX_DESC_PKT_OFFSET(txdesc, value) \
0017 le32p_replace_bits((__le32 *)(txdesc) + 0x01, value, GENMASK(28, 24))
0018 #define SET_TX_DESC_QSEL(txdesc, value) \
0019 le32p_replace_bits((__le32 *)(txdesc) + 0x01, value, GENMASK(12, 8))
0020 #define SET_TX_DESC_BMC(txdesc, value) \
0021 le32p_replace_bits((__le32 *)(txdesc) + 0x00, value, BIT(24))
0022 #define SET_TX_DESC_RATE_ID(txdesc, value) \
0023 le32p_replace_bits((__le32 *)(txdesc) + 0x01, value, GENMASK(20, 16))
0024 #define SET_TX_DESC_DATARATE(txdesc, value) \
0025 le32p_replace_bits((__le32 *)(txdesc) + 0x04, value, GENMASK(6, 0))
0026 #define SET_TX_DESC_DISDATAFB(txdesc, value) \
0027 le32p_replace_bits((__le32 *)(txdesc) + 0x03, value, BIT(10))
0028 #define SET_TX_DESC_USE_RATE(txdesc, value) \
0029 le32p_replace_bits((__le32 *)(txdesc) + 0x03, value, BIT(8))
0030 #define SET_TX_DESC_SEC_TYPE(txdesc, value) \
0031 le32p_replace_bits((__le32 *)(txdesc) + 0x01, value, GENMASK(23, 22))
0032 #define SET_TX_DESC_DATA_BW(txdesc, value) \
0033 le32p_replace_bits((__le32 *)(txdesc) + 0x05, value, GENMASK(6, 5))
0034 #define SET_TX_DESC_SW_SEQ(txdesc, value) \
0035 le32p_replace_bits((__le32 *)(txdesc) + 0x09, value, GENMASK(23, 12))
0036 #define SET_TX_DESC_TIM_EN(txdesc, value) \
0037 le32p_replace_bits((__le32 *)(txdesc) + 0x09, value, BIT(7))
0038 #define SET_TX_DESC_TIM_OFFSET(txdesc, value) \
0039 le32p_replace_bits((__le32 *)(txdesc) + 0x09, value, GENMASK(6, 0))
0040 #define SET_TX_DESC_MAX_AGG_NUM(txdesc, value) \
0041 le32p_replace_bits((__le32 *)(txdesc) + 0x03, value, GENMASK(21, 17))
0042 #define SET_TX_DESC_USE_RTS(tx_desc, value) \
0043 le32p_replace_bits((__le32 *)(txdesc) + 0x03, value, BIT(12))
0044 #define SET_TX_DESC_RTSRATE(txdesc, value) \
0045 le32p_replace_bits((__le32 *)(txdesc) + 0x04, value, GENMASK(28, 24))
0046 #define SET_TX_DESC_DATA_RTS_SHORT(txdesc, value) \
0047 le32p_replace_bits((__le32 *)(txdesc) + 0x05, value, BIT(12))
0048 #define SET_TX_DESC_AMPDU_DENSITY(txdesc, value) \
0049 le32p_replace_bits((__le32 *)(txdesc) + 0x02, value, GENMASK(22, 20))
0050 #define SET_TX_DESC_DATA_STBC(txdesc, value) \
0051 le32p_replace_bits((__le32 *)(txdesc) + 0x05, value, GENMASK(9, 8))
0052 #define SET_TX_DESC_DATA_LDPC(txdesc, value) \
0053 le32p_replace_bits((__le32 *)(txdesc) + 0x05, value, BIT(7))
0054 #define SET_TX_DESC_AGG_EN(txdesc, value) \
0055 le32p_replace_bits((__le32 *)(txdesc) + 0x02, value, BIT(12))
0056 #define SET_TX_DESC_LS(txdesc, value) \
0057 le32p_replace_bits((__le32 *)(txdesc) + 0x00, value, BIT(26))
0058 #define SET_TX_DESC_DATA_SHORT(txdesc, value) \
0059 le32p_replace_bits((__le32 *)(txdesc) + 0x05, value, BIT(4))
0060 #define SET_TX_DESC_SPE_RPT(tx_desc, value) \
0061 le32p_replace_bits((__le32 *)(txdesc) + 0x02, value, BIT(19))
0062 #define SET_TX_DESC_SW_DEFINE(tx_desc, value) \
0063 le32p_replace_bits((__le32 *)(txdesc) + 0x06, value, GENMASK(11, 0))
0064 #define SET_TX_DESC_DISQSELSEQ(txdesc, value) \
0065 le32p_replace_bits((__le32 *)(txdesc) + 0x00, value, BIT(31))
0066 #define SET_TX_DESC_EN_HWSEQ(txdesc, value) \
0067 le32p_replace_bits((__le32 *)(txdesc) + 0x08, value, BIT(15))
0068 #define SET_TX_DESC_HW_SSN_SEL(txdesc, value) \
0069 le32p_replace_bits((__le32 *)(txdesc) + 0x03, value, GENMASK(7, 6))
0070 #define SET_TX_DESC_NAVUSEHDR(txdesc, value) \
0071 le32p_replace_bits((__le32 *)(txdesc) + 0x03, value, BIT(15))
0072 #define SET_TX_DESC_BT_NULL(txdesc, value) \
0073 le32p_replace_bits((__le32 *)(txdesc) + 0x02, value, BIT(23))
0074
0075 enum rtw_tx_desc_queue_select {
0076 TX_DESC_QSEL_TID0 = 0,
0077 TX_DESC_QSEL_TID1 = 1,
0078 TX_DESC_QSEL_TID2 = 2,
0079 TX_DESC_QSEL_TID3 = 3,
0080 TX_DESC_QSEL_TID4 = 4,
0081 TX_DESC_QSEL_TID5 = 5,
0082 TX_DESC_QSEL_TID6 = 6,
0083 TX_DESC_QSEL_TID7 = 7,
0084 TX_DESC_QSEL_TID8 = 8,
0085 TX_DESC_QSEL_TID9 = 9,
0086 TX_DESC_QSEL_TID10 = 10,
0087 TX_DESC_QSEL_TID11 = 11,
0088 TX_DESC_QSEL_TID12 = 12,
0089 TX_DESC_QSEL_TID13 = 13,
0090 TX_DESC_QSEL_TID14 = 14,
0091 TX_DESC_QSEL_TID15 = 15,
0092 TX_DESC_QSEL_BEACON = 16,
0093 TX_DESC_QSEL_HIGH = 17,
0094 TX_DESC_QSEL_MGMT = 18,
0095 TX_DESC_QSEL_H2C = 19,
0096 };
0097
0098 enum rtw_rsvd_packet_type;
0099
0100 void rtw_tx(struct rtw_dev *rtwdev,
0101 struct ieee80211_tx_control *control,
0102 struct sk_buff *skb);
0103 void rtw_txq_init(struct rtw_dev *rtwdev, struct ieee80211_txq *txq);
0104 void rtw_txq_cleanup(struct rtw_dev *rtwdev, struct ieee80211_txq *txq);
0105 void rtw_tx_work(struct work_struct *w);
0106 void rtw_tx_pkt_info_update(struct rtw_dev *rtwdev,
0107 struct rtw_tx_pkt_info *pkt_info,
0108 struct ieee80211_sta *sta,
0109 struct sk_buff *skb);
0110 void rtw_tx_fill_tx_desc(struct rtw_tx_pkt_info *pkt_info, struct sk_buff *skb);
0111 void rtw_tx_report_enqueue(struct rtw_dev *rtwdev, struct sk_buff *skb, u8 sn);
0112 void rtw_tx_report_handle(struct rtw_dev *rtwdev, struct sk_buff *skb, int src);
0113 void rtw_tx_rsvd_page_pkt_info_update(struct rtw_dev *rtwdev,
0114 struct rtw_tx_pkt_info *pkt_info,
0115 struct sk_buff *skb,
0116 enum rtw_rsvd_packet_type type);
0117 struct sk_buff *
0118 rtw_tx_write_data_rsvd_page_get(struct rtw_dev *rtwdev,
0119 struct rtw_tx_pkt_info *pkt_info,
0120 u8 *buf, u32 size);
0121 struct sk_buff *
0122 rtw_tx_write_data_h2c_get(struct rtw_dev *rtwdev,
0123 struct rtw_tx_pkt_info *pkt_info,
0124 u8 *buf, u32 size);
0125
0126 #endif
