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0005 #ifndef __RTW_RX_H_
0006 #define __RTW_RX_H_
0007
0008 enum rtw_rx_desc_enc {
0009 RX_DESC_ENC_NONE = 0,
0010 RX_DESC_ENC_WEP40 = 1,
0011 RX_DESC_ENC_TKIP_WO_MIC = 2,
0012 RX_DESC_ENC_TKIP_MIC = 3,
0013 RX_DESC_ENC_AES = 4,
0014 RX_DESC_ENC_WEP104 = 5,
0015 };
0016
0017 #define GET_RX_DESC_PHYST(rxdesc) \
0018 le32_get_bits(*((__le32 *)(rxdesc) + 0x00), BIT(26))
0019 #define GET_RX_DESC_ICV_ERR(rxdesc) \
0020 le32_get_bits(*((__le32 *)(rxdesc) + 0x00), BIT(15))
0021 #define GET_RX_DESC_CRC32(rxdesc) \
0022 le32_get_bits(*((__le32 *)(rxdesc) + 0x00), BIT(14))
0023 #define GET_RX_DESC_SWDEC(rxdesc) \
0024 le32_get_bits(*((__le32 *)(rxdesc) + 0x00), BIT(27))
0025 #define GET_RX_DESC_C2H(rxdesc) \
0026 le32_get_bits(*((__le32 *)(rxdesc) + 0x02), BIT(28))
0027 #define GET_RX_DESC_PKT_LEN(rxdesc) \
0028 le32_get_bits(*((__le32 *)(rxdesc) + 0x00), GENMASK(13, 0))
0029 #define GET_RX_DESC_DRV_INFO_SIZE(rxdesc) \
0030 le32_get_bits(*((__le32 *)(rxdesc) + 0x00), GENMASK(19, 16))
0031 #define GET_RX_DESC_SHIFT(rxdesc) \
0032 le32_get_bits(*((__le32 *)(rxdesc) + 0x00), GENMASK(25, 24))
0033 #define GET_RX_DESC_ENC_TYPE(rxdesc) \
0034 le32_get_bits(*((__le32 *)(rxdesc) + 0x00), GENMASK(22, 20))
0035 #define GET_RX_DESC_RX_RATE(rxdesc) \
0036 le32_get_bits(*((__le32 *)(rxdesc) + 0x03), GENMASK(6, 0))
0037 #define GET_RX_DESC_MACID(rxdesc) \
0038 le32_get_bits(*((__le32 *)(rxdesc) + 0x01), GENMASK(6, 0))
0039 #define GET_RX_DESC_PPDU_CNT(rxdesc) \
0040 le32_get_bits(*((__le32 *)(rxdesc) + 0x02), GENMASK(30, 29))
0041 #define GET_RX_DESC_TSFL(rxdesc) \
0042 le32_get_bits(*((__le32 *)(rxdesc) + 0x05), GENMASK(31, 0))
0043
0044 void rtw_rx_stats(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
0045 struct sk_buff *skb);
0046 void rtw_rx_fill_rx_status(struct rtw_dev *rtwdev,
0047 struct rtw_rx_pkt_stat *pkt_stat,
0048 struct ieee80211_hdr *hdr,
0049 struct ieee80211_rx_status *rx_status,
0050 u8 *phy_status);
0051
0052 #endif