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0001 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
0002 /* Copyright(c) 2018-2019  Realtek Corporation
0003  */
0004 
0005 #ifndef __RTW8822C_H__
0006 #define __RTW8822C_H__
0007 
0008 #include <asm/byteorder.h>
0009 
0010 struct rtw8822cu_efuse {
0011     u8 res0[0x30];          /* 0x120 */
0012     u8 vid[2];          /* 0x150 */
0013     u8 pid[2];
0014     u8 res1[3];
0015     u8 mac_addr[ETH_ALEN];      /* 0x157 */
0016     u8 res2[0x3d];
0017 };
0018 
0019 struct rtw8822ce_efuse {
0020     u8 mac_addr[ETH_ALEN];      /* 0x120 */
0021     u8 vender_id[2];
0022     u8 device_id[2];
0023     u8 sub_vender_id[2];
0024     u8 sub_device_id[2];
0025     u8 pmc[2];
0026     u8 exp_device_cap[2];
0027     u8 msi_cap;
0028     u8 ltr_cap;         /* 0x133 */
0029     u8 exp_link_control[2];
0030     u8 link_cap[4];
0031     u8 link_control[2];
0032     u8 serial_number[8];
0033     u8 res0:2;          /* 0x144 */
0034     u8 ltr_en:1;
0035     u8 res1:2;
0036     u8 obff:2;
0037     u8 res2:3;
0038     u8 obff_cap:2;
0039     u8 res3:4;
0040     u8 class_code[3];
0041     u8 res4;
0042     u8 pci_pm_L1_2_supp:1;
0043     u8 pci_pm_L1_1_supp:1;
0044     u8 aspm_pm_L1_2_supp:1;
0045     u8 aspm_pm_L1_1_supp:1;
0046     u8 L1_pm_substates_supp:1;
0047     u8 res5:3;
0048     u8 port_common_mode_restore_time;
0049     u8 port_t_power_on_scale:2;
0050     u8 res6:1;
0051     u8 port_t_power_on_value:5;
0052     u8 res7;
0053 };
0054 
0055 struct rtw8822c_efuse {
0056     __le16 rtl_id;
0057     u8 res0[0x0e];
0058 
0059     /* power index for four RF paths */
0060     struct rtw_txpwr_idx txpwr_idx_table[4];
0061 
0062     u8 channel_plan;        /* 0xb8 */
0063     u8 xtal_k;
0064     u8 res1;
0065     u8 iqk_lck;
0066     u8 res2[5];         /* 0xbc */
0067     u8 rf_board_option;
0068     u8 rf_feature_option;
0069     u8 rf_bt_setting;
0070     u8 eeprom_version;
0071     u8 eeprom_customer_id;
0072     u8 tx_bb_swing_setting_2g;
0073     u8 tx_bb_swing_setting_5g;
0074     u8 tx_pwr_calibrate_rate;
0075     u8 rf_antenna_option;       /* 0xc9 */
0076     u8 rfe_option;
0077     u8 country_code[2];
0078     u8 res3[3];
0079     u8 path_a_thermal;      /* 0xd0 */
0080     u8 path_b_thermal;
0081     u8 res4[2];
0082     u8 rx_gain_gap_2g_ofdm;
0083     u8 res5;
0084     u8 rx_gain_gap_2g_cck;
0085     u8 res6;
0086     u8 rx_gain_gap_5gl;
0087     u8 res7;
0088     u8 rx_gain_gap_5gm;
0089     u8 res8;
0090     u8 rx_gain_gap_5gh;
0091     u8 res9;
0092     u8 res10[0x42];
0093     union {
0094         struct rtw8822cu_efuse u;
0095         struct rtw8822ce_efuse e;
0096     };
0097 };
0098 
0099 enum rtw8822c_dpk_agc_phase {
0100     RTW_DPK_GAIN_CHECK,
0101     RTW_DPK_GAIN_LARGE,
0102     RTW_DPK_GAIN_LESS,
0103     RTW_DPK_GL_LARGE,
0104     RTW_DPK_GL_LESS,
0105     RTW_DPK_LOSS_CHECK,
0106     RTW_DPK_AGC_OUT,
0107 };
0108 
0109 enum rtw8822c_dpk_one_shot_action {
0110     RTW_DPK_CAL_PWR,
0111     RTW_DPK_GAIN_LOSS,
0112     RTW_DPK_DO_DPK,
0113     RTW_DPK_DPK_ON,
0114     RTW_DPK_DAGC,
0115     RTW_DPK_ACTION_MAX
0116 };
0117 
0118 void rtw8822c_parse_tbl_dpk(struct rtw_dev *rtwdev,
0119                 const struct rtw_table *tbl);
0120 
0121 extern const struct rtw_chip_info rtw8822c_hw_spec;
0122 
0123 #define RTW_DECL_TABLE_DPK(name)            \
0124 const struct rtw_table name ## _tbl = {         \
0125     .data = name,                   \
0126     .size = ARRAY_SIZE(name),           \
0127     .parse = rtw8822c_parse_tbl_dpk,        \
0128 }
0129 
0130 #define DACK_PATH_8822C     2
0131 #define DACK_REG_8822C      16
0132 #define DACK_RF_8822C       1
0133 #define DACK_SN_8822C       100
0134 
0135 /* phy status page0 */
0136 #define GET_PHY_STAT_P0_PWDB_A(phy_stat)                                       \
0137     le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
0138 #define GET_PHY_STAT_P0_PWDB_B(phy_stat)                                       \
0139     le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(7, 0))
0140 #define GET_PHY_STAT_P0_GAIN_A(phy_stat)                                       \
0141     le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(21, 16))
0142 #define GET_PHY_STAT_P0_CHANNEL(phy_stat)                      \
0143     le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(23, 16))
0144 #define GET_PHY_STAT_P0_GAIN_B(phy_stat)                                       \
0145     le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(29, 24))
0146 
0147 /* phy status page1 */
0148 #define GET_PHY_STAT_P1_PWDB_A(phy_stat)                                       \
0149     le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
0150 #define GET_PHY_STAT_P1_PWDB_B(phy_stat)                                       \
0151     le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(23, 16))
0152 #define GET_PHY_STAT_P1_L_RXSC(phy_stat)                                       \
0153     le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(11, 8))
0154 #define GET_PHY_STAT_P1_HT_RXSC(phy_stat)                                      \
0155     le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(15, 12))
0156 #define GET_PHY_STAT_P1_CHANNEL(phy_stat)                      \
0157     le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(23, 16))
0158 #define GET_PHY_STAT_P1_RXEVM_A(phy_stat)                                      \
0159     le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(7, 0))
0160 #define GET_PHY_STAT_P1_RXEVM_B(phy_stat)                                      \
0161     le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(15, 8))
0162 #define GET_PHY_STAT_P1_CFO_TAIL_A(phy_stat)                                 \
0163     le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(7, 0))
0164 #define GET_PHY_STAT_P1_CFO_TAIL_B(phy_stat)                                 \
0165     le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(15, 8))
0166 #define GET_PHY_STAT_P1_RXSNR_A(phy_stat)                                      \
0167     le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(7, 0))
0168 #define GET_PHY_STAT_P1_RXSNR_B(phy_stat)                                      \
0169     le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(15, 8))
0170 
0171 #define RTW8822C_EDCCA_MAX  0x7f
0172 #define REG_ANAPARLDO_POW_MAC   0x0029
0173 #define BIT_LDOE25_PON      BIT(0)
0174 #define XCAP_MASK       GENMASK(6, 0)
0175 #define CFO_TRK_ENABLE_TH   20
0176 #define CFO_TRK_STOP_TH     10
0177 #define CFO_TRK_ADJ_TH      10
0178 
0179 #define REG_TXDFIR0     0x808
0180 #define REG_DFIRBW      0x810
0181 #define REG_ANTMAP0     0x820
0182 #define BIT_ANT_PATH        GENMASK(1, 0)
0183 #define REG_ANTMAP      0x824
0184 #define REG_EDCCA_DECISION  0x844
0185 #define BIT_EDCCA_OPTION    GENMASK(30, 29)
0186 #define REG_DYMPRITH        0x86c
0187 #define REG_DYMENTH0        0x870
0188 #define REG_DYMENTH     0x874
0189 #define REG_SBD         0x88c
0190 #define BITS_SUBTUNE        GENMASK(15, 12)
0191 #define REG_DYMTHMIN        0x8a4
0192 
0193 #define REG_TXBWCTL     0x9b0
0194 #define REG_TXCLK       0x9b4
0195 
0196 #define REG_SCOTRK      0xc30
0197 #define REG_MRCM        0xc38
0198 #define REG_AGCSWSH     0xc44
0199 #define REG_ANTWTPD     0xc54
0200 #define REG_PT_CHSMO        0xcbc
0201 #define BIT_PT_OPT      BIT(21)
0202 
0203 #define REG_ORITXCODE       0x1800
0204 #define BIT_PATH_EN     BIT(31)
0205 #define REG_3WIRE       0x180c
0206 #define BIT_DIS_SHARERX_TXGAT   BIT(27)
0207 #define BIT_3WIRE_TX_EN     BIT(0)
0208 #define BIT_3WIRE_RX_EN     BIT(1)
0209 #define BIT_3WIRE_EN        GENMASK(1, 0)
0210 #define BIT_3WIRE_PI_ON     BIT(28)
0211 #define REG_ANAPAR_A        0x1830
0212 #define BIT_ANAPAR_UPDATE   BIT(29)
0213 #define REG_RFTXEN_GCK_A    0x1864
0214 #define BIT_RFTXEN_GCK_FORCE_ON BIT(31)
0215 #define REG_DIS_SHARE_RX_A  0x186c
0216 #define BIT_TX_SCALE_0DB    BIT(7)
0217 #define REG_RXAGCCTL0       0x18ac
0218 #define BITS_RXAGC_CCK      GENMASK(15, 12)
0219 #define BITS_RXAGC_OFDM     GENMASK(8, 4)
0220 #define REG_DCKA_I_0        0x18bc
0221 #define REG_DCKA_I_1        0x18c0
0222 #define REG_DCKA_Q_0        0x18d8
0223 #define REG_DCKA_Q_1        0x18dc
0224 
0225 #define REG_CCKSB       0x1a00
0226 #define BIT_BBMODE      GENMASK(2, 1)
0227 #define REG_RXCCKSEL        0x1a04
0228 #define REG_BGCTRL      0x1a14
0229 #define BITS_RX_IQ_WEIGHT   (BIT(8) | BIT(9))
0230 #define REG_TXF0        0x1a20
0231 #define REG_TXF1        0x1a24
0232 #define REG_TXF2        0x1a28
0233 #define REG_CCANRX      0x1a2c
0234 #define BIT_CCK_FA_RST      (BIT(14) | BIT(15))
0235 #define BIT_OFDM_FA_RST     (BIT(12) | BIT(13))
0236 #define REG_CCK_FACNT       0x1a5c
0237 #define REG_CCKTXONLY       0x1a80
0238 #define BIT_BB_CCK_CHECK_EN BIT(18)
0239 #define REG_TXF3        0x1a98
0240 #define REG_TXF4        0x1a9c
0241 #define REG_TXF5        0x1aa0
0242 #define REG_TXF6        0x1aac
0243 #define REG_TXF7        0x1ab0
0244 #define REG_CCK_SOURCE      0x1abc
0245 #define BIT_NBI_EN      BIT(30)
0246 
0247 #define REG_NCTL0       0x1b00
0248 #define BIT_SEL_PATH        GENMASK(2, 1)
0249 #define BIT_SUBPAGE     GENMASK(3, 0)
0250 #define REG_DPD_CTL0_S0     0x1b04
0251 #define BIT_GS_PWSF     GENMASK(27, 0)
0252 #define REG_DPD_CTL1_S0     0x1b08
0253 #define BIT_DPD_EN      BIT(31)
0254 #define BIT_PS_EN       BIT(7)
0255 #define REG_IQKSTAT     0x1b10
0256 #define REG_IQK_CTL1        0x1b20
0257 #define BIT_TX_CFIR     GENMASK(31, 30)
0258 #define BIT_CFIR_EN     GENMASK(26, 24)
0259 #define BIT_BYPASS_DPD      BIT(25)
0260 
0261 #define REG_TX_TONE_IDX     0x1b2c
0262 #define REG_DPD_LUT0        0x1b44
0263 #define BIT_GLOSS_DB        GENMASK(14, 12)
0264 #define REG_DPD_CTL0_S1     0x1b5c
0265 #define REG_DPD_CTL1_S1     0x1b60
0266 #define REG_DPD_AGC     0x1b67
0267 #define REG_TABLE_SEL       0x1b98
0268 #define BIT_I_GAIN      GENMASK(19, 16)
0269 #define BIT_GAIN_RST        BIT(15)
0270 #define BIT_Q_GAIN_SEL      GENMASK(14, 12)
0271 #define BIT_Q_GAIN      GENMASK(11, 0)
0272 #define REG_TX_GAIN_SET     0x1b9c
0273 #define BIT_GAPK_RPT_IDX    GENMASK(11, 8)
0274 #define REG_DPD_CTL0        0x1bb4
0275 #define REG_SINGLE_TONE_SW  0x1bb8
0276 #define BIT_IRQ_TEST_MODE   BIT(20)
0277 #define REG_R_CONFIG        0x1bcc
0278 #define BIT_INNER_LB        BIT(21)
0279 #define BIT_IQ_SWITCH       GENMASK(5, 0)
0280 #define BIT_2G_SWING        0x2d
0281 #define BIT_5G_SWING        0x36
0282 #define REG_RXSRAM_CTL      0x1bd4
0283 #define BIT_RPT_EN      BIT(21)
0284 #define BIT_RPT_SEL     GENMASK(20, 16)
0285 #define BIT_DPD_CLK     GENMASK(7, 4)
0286 #define REG_DPD_CTL11       0x1be4
0287 #define REG_DPD_CTL12       0x1be8
0288 #define REG_DPD_CTL15       0x1bf4
0289 #define REG_DPD_CTL16       0x1bf8
0290 #define REG_STAT_RPT        0x1bfc
0291 #define BIT_RPT_DGAIN       GENMASK(27, 16)
0292 #define BIT_GAPK_RPT0       GENMASK(3, 0)
0293 #define BIT_GAPK_RPT1       GENMASK(7, 4)
0294 #define BIT_GAPK_RPT2       GENMASK(11, 8)
0295 #define BIT_GAPK_RPT3       GENMASK(15, 12)
0296 #define BIT_GAPK_RPT4       GENMASK(19, 16)
0297 #define BIT_GAPK_RPT5       GENMASK(23, 20)
0298 #define BIT_GAPK_RPT6       GENMASK(27, 24)
0299 #define BIT_GAPK_RPT7       GENMASK(31, 28)
0300 
0301 #define REG_TXANT       0x1c28
0302 #define REG_IQK_CTRL        0x1c38
0303 #define REG_ENCCK       0x1c3c
0304 #define BIT_CCK_BLK_EN      BIT(1)
0305 #define BIT_CCK_OFDM_BLK_EN (BIT(0) | BIT(1))
0306 #define REG_CCAMSK      0x1c80
0307 #define REG_RSTB        0x1c90
0308 #define BIT_RSTB_3WIRE      BIT(8)
0309 #define REG_CH_DELAY_EXTR2  0x1cd0
0310 #define BIT_TST_IQK2SET_SRC BIT(31)
0311 #define BIT_EN_IOQ_IQK_DPK  BIT(30)
0312 #define BIT_IQK_DPK_RESET_SRC   BIT(29)
0313 #define BIT_IQK_DPK_CLOCK_SRC   BIT(28)
0314 
0315 #define REG_RX_BREAK        0x1d2c
0316 #define BIT_COM_RX_GCK_EN   BIT(31)
0317 #define REG_RXFNCTL     0x1d30
0318 #define REG_CCA_OFF     0x1d58
0319 #define BIT_CCA_ON_BY_PW    GENMASK(11, 3)
0320 #define REG_RXIGI       0x1d70
0321 
0322 #define REG_ENFN        0x1e24
0323 #define BIT_IQK_DPK_EN      BIT(17)
0324 #define REG_TXANTSEG        0x1e28
0325 #define BIT_ANTSEG      GENMASK(3, 0)
0326 #define REG_TXLGMAP     0x1e2c
0327 #define REG_CCKPATH     0x1e5c
0328 #define REG_TX_FIFO     0x1e70
0329 #define BIT_STOP_TX     GENMASK(3, 0)
0330 #define REG_CNT_CTRL        0x1eb4
0331 #define BIT_ALL_CNT_RST     BIT(25)
0332 
0333 #define REG_OFDM_FACNT      0x2d00
0334 #define REG_OFDM_FACNT1     0x2d04
0335 #define REG_OFDM_FACNT2     0x2d08
0336 #define REG_OFDM_FACNT3     0x2d0c
0337 #define REG_OFDM_FACNT4     0x2d10
0338 #define REG_OFDM_FACNT5     0x2d20
0339 #define REG_RPT_CIP     0x2d9c
0340 #define BIT_RPT_CIP_STATUS  GENMASK(7, 0)
0341 #define REG_OFDM_TXCNT      0x2de0
0342 
0343 #define REG_ORITXCODE2      0x4100
0344 #define REG_3WIRE2      0x410c
0345 #define REG_ANAPAR_B        0x4130
0346 #define REG_RFTXEN_GCK_B    0x4164
0347 #define REG_DIS_SHARE_RX_B  0x416c
0348 #define BIT_EXT_TIA_BW      BIT(1)
0349 #define REG_RXAGCCTL        0x41ac
0350 #define REG_DCKB_I_0        0x41bc
0351 #define REG_DCKB_I_1        0x41c0
0352 #define REG_DCKB_Q_0        0x41d8
0353 #define REG_DCKB_Q_1        0x41dc
0354 
0355 #define RF_MODE_TRXAGC      0x00
0356 #define BIT_RF_MODE     GENMASK(19, 16)
0357 #define BIT_RXAGC       GENMASK(9, 5)
0358 #define BIT_TXAGC       GENMASK(4, 0)
0359 #define RF_RXAGC_OFFSET     0x19
0360 #define RF_BW_TRXBB     0x1a
0361 #define BIT_TX_CCK_IND      BIT(16)
0362 #define BIT_BW_TXBB     GENMASK(14, 12)
0363 #define BIT_BW_RXBB     GENMASK(11, 10)
0364 #define BIT_DBG_CCK_CCA     BIT(1)
0365 #define RF_TX_GAIN_OFFSET   0x55
0366 #define BIT_BB_GAIN     GENMASK(18, 14)
0367 #define BIT_RF_GAIN     GENMASK(4, 2)
0368 #define RF_TX_GAIN      0x56
0369 #define BIT_GAIN_TXBB       GENMASK(4, 0)
0370 #define RF_IDAC         0x58
0371 #define BIT_TX_MODE     GENMASK(19, 8)
0372 #define RF_TX_RESULT        0x5f
0373 #define BIT_GAIN_TX_PAD_H   GENMASK(11, 8)
0374 #define BIT_GAIN_TX_PAD_L   GENMASK(7, 4)
0375 #define RF_PA           0x60
0376 #define RF_PABIAS_2G_MASK   GENMASK(15, 12)
0377 #define RF_PABIAS_5G_MASK   GENMASK(19, 16)
0378 #define RF_TXA_LB_SW        0x63
0379 #define BIT_TXA_LB_ATT      GENMASK(15, 14)
0380 #define BIT_LB_SW       GENMASK(13, 12)
0381 #define BIT_LB_ATT      GENMASK(4, 2)
0382 #define RF_RXG_GAIN     0x87
0383 #define BIT_RXG_GAIN        BIT(18)
0384 #define RF_RXA_MIX_GAIN     0x8a
0385 #define BIT_RXA_MIX_GAIN    GENMASK(4, 3)
0386 #define RF_EXT_TIA_BW       0x8f
0387 #define BIT_PW_EXT_TIA      BIT(1)
0388 #define RF_DIS_BYPASS_TXBB  0x9e
0389 #define BIT_TXBB        BIT(10)
0390 #define BIT_TIA_BYPASS      BIT(5)
0391 #define RF_DEBUG        0xde
0392 #define BIT_DE_PWR_TRIM     BIT(19)
0393 #define BIT_DE_TX_GAIN      BIT(16)
0394 #define BIT_DE_TRXBW        BIT(2)
0395 
0396 #define PPG_THERMAL_B       0x1b0
0397 #define RF_THEMAL_MASK      GENMASK(19, 16)
0398 #define PPG_2GH_TXAB        0x1d2
0399 #define PPG_2G_A_MASK       GENMASK(3, 0)
0400 #define PPG_2G_B_MASK       GENMASK(7, 4)
0401 #define PPG_2GL_TXAB        0x1d4
0402 #define PPG_PABIAS_2GB      0x1d5
0403 #define PPG_PABIAS_2GA      0x1d6
0404 #define PPG_PABIAS_MASK     GENMASK(3, 0)
0405 #define PPG_PABIAS_5GB      0x1d7
0406 #define PPG_PABIAS_5GA      0x1d8
0407 #define PPG_5G_MASK     GENMASK(4, 0)
0408 #define PPG_5GH1_TXB        0x1db
0409 #define PPG_5GH1_TXA        0x1dc
0410 #define PPG_5GM2_TXB        0x1df
0411 #define PPG_5GM2_TXA        0x1e0
0412 #define PPG_5GM1_TXB        0x1e3
0413 #define PPG_5GM1_TXA        0x1e4
0414 #define PPG_5GL2_TXB        0x1e7
0415 #define PPG_5GL2_TXA        0x1e8
0416 #define PPG_5GL1_TXB        0x1eb
0417 #define PPG_5GL1_TXA        0x1ec
0418 #define PPG_2GM_TXAB        0x1ee
0419 #define PPG_THERMAL_A       0x1ef
0420 #endif
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