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0001 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
0002 /* Copyright(c) 2018-2019  Realtek Corporation
0003  */
0004 
0005 #ifndef __RTW8822B_H__
0006 #define __RTW8822B_H__
0007 
0008 #include <asm/byteorder.h>
0009 
0010 #define RCR_VHT_ACK     BIT(26)
0011 
0012 struct rtw8822bu_efuse {
0013     u8 res4[4];         /* 0xd0 */
0014     u8 usb_optional_function;
0015     u8 res5[0x1e];
0016     u8 res6[2];
0017     u8 serial[0x0b];        /* 0xf5 */
0018     u8 vid;             /* 0x100 */
0019     u8 res7;
0020     u8 pid;
0021     u8 res8[4];
0022     u8 mac_addr[ETH_ALEN];      /* 0x107 */
0023     u8 res9[2];
0024     u8 vendor_name[0x07];
0025     u8 res10[2];
0026     u8 device_name[0x14];
0027     u8 res11[0xcf];
0028     u8 package_type;        /* 0x1fb */
0029     u8 res12[0x4];
0030 };
0031 
0032 struct rtw8822be_efuse {
0033     u8 mac_addr[ETH_ALEN];      /* 0xd0 */
0034     u8 vender_id[2];
0035     u8 device_id[2];
0036     u8 sub_vender_id[2];
0037     u8 sub_device_id[2];
0038     u8 pmc[2];
0039     u8 exp_device_cap[2];
0040     u8 msi_cap;
0041     u8 ltr_cap;         /* 0xe3 */
0042     u8 exp_link_control[2];
0043     u8 link_cap[4];
0044     u8 link_control[2];
0045     u8 serial_number[8];
0046     u8 res0:2;          /* 0xf4 */
0047     u8 ltr_en:1;
0048     u8 res1:2;
0049     u8 obff:2;
0050     u8 res2:3;
0051     u8 obff_cap:2;
0052     u8 res3:4;
0053     u8 res4[3];
0054     u8 class_code[3];
0055     u8 pci_pm_L1_2_supp:1;
0056     u8 pci_pm_L1_1_supp:1;
0057     u8 aspm_pm_L1_2_supp:1;
0058     u8 aspm_pm_L1_1_supp:1;
0059     u8 L1_pm_substates_supp:1;
0060     u8 res5:3;
0061     u8 port_common_mode_restore_time;
0062     u8 port_t_power_on_scale:2;
0063     u8 res6:1;
0064     u8 port_t_power_on_value:5;
0065     u8 res7;
0066 };
0067 
0068 struct rtw8822b_efuse {
0069     __le16 rtl_id;
0070     u8 res0[0x0e];
0071 
0072     /* power index for four RF paths */
0073     struct rtw_txpwr_idx txpwr_idx_table[4];
0074 
0075     u8 channel_plan;        /* 0xb8 */
0076     u8 xtal_k;
0077     u8 thermal_meter;
0078     u8 iqk_lck;
0079     u8 pa_type;         /* 0xbc */
0080     u8 lna_type_2g[2];      /* 0xbd */
0081     u8 lna_type_5g[2];
0082     u8 rf_board_option;
0083     u8 rf_feature_option;
0084     u8 rf_bt_setting;
0085     u8 eeprom_version;
0086     u8 eeprom_customer_id;
0087     u8 tx_bb_swing_setting_2g;
0088     u8 tx_bb_swing_setting_5g;
0089     u8 tx_pwr_calibrate_rate;
0090     u8 rf_antenna_option;       /* 0xc9 */
0091     u8 rfe_option;
0092     u8 country_code[2];
0093     u8 res[3];
0094     union {
0095         struct rtw8822bu_efuse u;
0096         struct rtw8822be_efuse e;
0097     };
0098 };
0099 
0100 static inline void
0101 _rtw_write32s_mask(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 data)
0102 {
0103     /* 0xC00-0xCFF and 0xE00-0xEFF have the same layout */
0104     rtw_write32_mask(rtwdev, addr, mask, data);
0105     rtw_write32_mask(rtwdev, addr + 0x200, mask, data);
0106 }
0107 
0108 #define rtw_write32s_mask(rtwdev, addr, mask, data)                \
0109     do {                                       \
0110         BUILD_BUG_ON((addr) < 0xC00 || (addr) >= 0xD00);           \
0111                                            \
0112         _rtw_write32s_mask(rtwdev, addr, mask, data);              \
0113     } while (0)
0114 
0115 /* phy status page0 */
0116 #define GET_PHY_STAT_P0_PWDB(phy_stat)                                         \
0117     le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
0118 
0119 /* phy status page1 */
0120 #define GET_PHY_STAT_P1_PWDB_A(phy_stat)                                       \
0121     le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
0122 #define GET_PHY_STAT_P1_PWDB_B(phy_stat)                                       \
0123     le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(23, 16))
0124 #define GET_PHY_STAT_P1_RF_MODE(phy_stat)                                      \
0125     le32_get_bits(*((__le32 *)(phy_stat) + 0x03), GENMASK(29, 28))
0126 #define GET_PHY_STAT_P1_L_RXSC(phy_stat)                                       \
0127     le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(11, 8))
0128 #define GET_PHY_STAT_P1_HT_RXSC(phy_stat)                                      \
0129     le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(15, 12))
0130 #define GET_PHY_STAT_P1_RXEVM_A(phy_stat)                                      \
0131     le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(7, 0))
0132 #define GET_PHY_STAT_P1_RXEVM_B(phy_stat)                                      \
0133     le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(15, 8))
0134 #define GET_PHY_STAT_P1_CFO_TAIL_A(phy_stat)                                 \
0135     le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(7, 0))
0136 #define GET_PHY_STAT_P1_CFO_TAIL_B(phy_stat)                                 \
0137     le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(15, 8))
0138 #define GET_PHY_STAT_P1_RXSNR_A(phy_stat)                                      \
0139     le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(7, 0))
0140 #define GET_PHY_STAT_P1_RXSNR_B(phy_stat)                                      \
0141     le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(15, 8))
0142 
0143 #define RTW8822B_EDCCA_MAX  0x7f
0144 #define RTW8822B_EDCCA_SRC_DEF  1
0145 #define REG_HTSTFWT 0x800
0146 #define REG_RXPSEL  0x808
0147 #define BIT_RX_PSEL_RST     (BIT(28) | BIT(29))
0148 #define REG_TXPSEL  0x80c
0149 #define REG_RXCCAMSK    0x814
0150 #define REG_CCASEL  0x82c
0151 #define REG_PDMFTH  0x830
0152 #define REG_CCA2ND  0x838
0153 #define REG_L1WT    0x83c
0154 #define REG_L1PKWT  0x840
0155 #define REG_MRC     0x850
0156 #define REG_CLKTRK  0x860
0157 #define REG_EDCCA_POW_MA    0x8a0
0158 #define BIT_MA_LEVEL    GENMASK(1, 0)
0159 #define REG_ADCCLK  0x8ac
0160 #define REG_ADC160  0x8c4
0161 #define REG_ADC40   0x8c8
0162 #define REG_EDCCA_DECISION  0x8dc
0163 #define BIT_EDCCA_OPTION    BIT(5)
0164 #define REG_CDDTXP  0x93c
0165 #define REG_TXPSEL1 0x940
0166 #define REG_EDCCA_SOURCE    0x944
0167 #define BIT_SOURCE_OPTION   GENMASK(29, 28)
0168 #define REG_ACBB0   0x948
0169 #define REG_ACBBRXFIR   0x94c
0170 #define REG_ACGG2TBL    0x958
0171 #define REG_RXSB    0xa00
0172 #define REG_ADCINI  0xa04
0173 #define REG_TXSF2   0xa24
0174 #define REG_TXSF6   0xa28
0175 #define REG_RXDESC  0xa2c
0176 #define REG_ENTXCCK 0xa80
0177 #define REG_AGCTR_A 0xc08
0178 #define REG_TXDFIR  0xc20
0179 #define REG_RXIGI_A 0xc50
0180 #define REG_TRSW    0xca0
0181 #define REG_RFESEL0 0xcb0
0182 #define REG_RFESEL8 0xcb4
0183 #define REG_RFECTL  0xcb8
0184 #define REG_RFEINV  0xcbc
0185 #define REG_AGCTR_B 0xe08
0186 #define REG_RXIGI_B 0xe50
0187 #define REG_ANTWT   0x1904
0188 #define REG_IQKFAILMSK  0x1bf0
0189 
0190 extern const struct rtw_chip_info rtw8822b_hw_spec;
0191 
0192 #endif
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