realtek/rtw88/rtw8821c.h

0001 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
0002 /* Copyright(c) 2018-2019  Realtek Corporation
0003  */
0004
0005 #ifndef __RTW8821C_H__
0006 #define __RTW8821C_H__
0007
0008 #include <asm/byteorder.h>
0009
0010 #define RCR_VHT_ACK     BIT(26)
0011
0012 struct rtw8821ce_efuse {
0013     u8 mac_addr[ETH_ALEN];      /* 0xd0 */
0014     u8 vender_id[2];
0015     u8 device_id[2];
0016     u8 sub_vender_id[2];
0017     u8 sub_device_id[2];
0018     u8 pmc[2];
0019     u8 exp_device_cap[2];
0020     u8 msi_cap;
0021     u8 ltr_cap;         /* 0xe3 */
0022     u8 exp_link_control[2];
0023     u8 link_cap[4];
0024     u8 link_control[2];
0025     u8 serial_number[8];
0026     u8 res0:2;          /* 0xf4 */
0027     u8 ltr_en:1;
0028     u8 res1:2;
0029     u8 obff:2;
0030     u8 res2:3;
0031     u8 obff_cap:2;
0032     u8 res3:4;
0033     u8 res4[3];
0034     u8 class_code[3];
0035     u8 pci_pm_L1_2_supp:1;
0036     u8 pci_pm_L1_1_supp:1;
0037     u8 aspm_pm_L1_2_supp:1;
0038     u8 aspm_pm_L1_1_supp:1;
0039     u8 L1_pm_substates_supp:1;
0040     u8 res5:3;
0041     u8 port_common_mode_restore_time;
0042     u8 port_t_power_on_scale:2;
0043     u8 res6:1;
0044     u8 port_t_power_on_value:5;
0045     u8 res7;
0046 };
0047
0048 struct rtw8821c_efuse {
0049     __le16 rtl_id;
0050     u8 res0[0x0e];
0051
0052     /* power index for four RF paths */
0053     struct rtw_txpwr_idx txpwr_idx_table[4];
0054
0055     u8 channel_plan;        /* 0xb8 */
0056     u8 xtal_k;
0057     u8 thermal_meter;
0058     u8 iqk_lck;
0059     u8 pa_type;         /* 0xbc */
0060     u8 lna_type_2g[2];      /* 0xbd */
0061     u8 lna_type_5g[2];
0062     u8 rf_board_option;
0063     u8 rf_feature_option;
0064     u8 rf_bt_setting;
0065     u8 eeprom_version;
0066     u8 eeprom_customer_id;
0067     u8 tx_bb_swing_setting_2g;
0068     u8 tx_bb_swing_setting_5g;
0069     u8 tx_pwr_calibrate_rate;
0070     u8 rf_antenna_option;       /* 0xc9 */
0071     u8 rfe_option;
0072     u8 country_code[2];
0073     u8 res[3];
0074     union {
0075         struct rtw8821ce_efuse e;
0076     };
0077 };
0078
0079 static inline void
0080 _rtw_write32s_mask(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 data)
0081 {
0082     /* 0xC00-0xCFF and 0xE00-0xEFF have the same layout */
0083     rtw_write32_mask(rtwdev, addr, mask, data);
0084     rtw_write32_mask(rtwdev, addr + 0x200, mask, data);
0085 }
0086
0087 extern const struct rtw_chip_info rtw8821c_hw_spec;
0088
0089 #define rtw_write32s_mask(rtwdev, addr, mask, data)                \
0090     do {                                       \
0091         BUILD_BUG_ON((addr) < 0xC00 || (addr) >= 0xD00);           \
0092                                            \
0093         _rtw_write32s_mask(rtwdev, addr, mask, data);              \
0094     } while (0)
0095
0096 #define BIT_FEN_PCIEA BIT(6)
0097 #define WLAN_SLOT_TIME      0x09
0098 #define WLAN_PIFS_TIME      0x19
0099 #define WLAN_SIFS_CCK_CONT_TX   0xA
0100 #define WLAN_SIFS_OFDM_CONT_TX  0xE
0101 #define WLAN_SIFS_CCK_TRX   0x10
0102 #define WLAN_SIFS_OFDM_TRX  0x10
0103 #define WLAN_VO_TXOP_LIMIT  0x186
0104 #define WLAN_VI_TXOP_LIMIT  0x3BC
0105 #define WLAN_RDG_NAV        0x05
0106 #define WLAN_TXOP_NAV       0x1B
0107 #define WLAN_CCK_RX_TSF     0x30
0108 #define WLAN_OFDM_RX_TSF    0x30
0109 #define WLAN_TBTT_PROHIBIT  0x04
0110 #define WLAN_TBTT_HOLD_TIME 0x064
0111 #define WLAN_DRV_EARLY_INT  0x04
0112 #define WLAN_BCN_DMA_TIME   0x02
0113
0114 #define WLAN_RX_FILTER0     0x0FFFFFFF
0115 #define WLAN_RX_FILTER2     0xFFFF
0116 #define WLAN_RCR_CFG        0xE400220E
0117 #define WLAN_RXPKT_MAX_SZ   12288
0118 #define WLAN_RXPKT_MAX_SZ_512   (WLAN_RXPKT_MAX_SZ >> 9)
0119
0120 #define WLAN_AMPDU_MAX_TIME     0x70
0121 #define WLAN_RTS_LEN_TH         0xFF
0122 #define WLAN_RTS_TX_TIME_TH     0x08
0123 #define WLAN_MAX_AGG_PKT_LIMIT      0x20
0124 #define WLAN_RTS_MAX_AGG_PKT_LIMIT  0x20
0125 #define FAST_EDCA_VO_TH     0x06
0126 #define FAST_EDCA_VI_TH     0x06
0127 #define FAST_EDCA_BE_TH     0x06
0128 #define FAST_EDCA_BK_TH     0x06
0129 #define WLAN_BAR_RETRY_LIMIT        0x01
0130 #define WLAN_RA_TRY_RATE_AGG_LIMIT  0x08
0131
0132 #define WLAN_TX_FUNC_CFG1       0x30
0133 #define WLAN_TX_FUNC_CFG2       0x30
0134 #define WLAN_MAC_OPT_NORM_FUNC1     0x98
0135 #define WLAN_MAC_OPT_LB_FUNC1       0x80
0136 #define WLAN_MAC_OPT_FUNC2      0xb0810041
0137
0138 #define WLAN_SIFS_CFG   (WLAN_SIFS_CCK_CONT_TX | \
0139             (WLAN_SIFS_OFDM_CONT_TX << BIT_SHIFT_SIFS_OFDM_CTX) | \
0140             (WLAN_SIFS_CCK_TRX << BIT_SHIFT_SIFS_CCK_TRX) | \
0141             (WLAN_SIFS_OFDM_TRX << BIT_SHIFT_SIFS_OFDM_TRX))
0142
0143 #define WLAN_TBTT_TIME  (WLAN_TBTT_PROHIBIT |\
0144             (WLAN_TBTT_HOLD_TIME << BIT_SHIFT_TBTT_HOLD_TIME_AP))
0145
0146 #define WLAN_NAV_CFG        (WLAN_RDG_NAV | (WLAN_TXOP_NAV << 16))
0147 #define WLAN_RX_TSF_CFG     (WLAN_CCK_RX_TSF | (WLAN_OFDM_RX_TSF) << 8)
0148 #define WLAN_PRE_TXCNT_TIME_TH      0x1E4
0149
0150 /* phy status page0 */
0151 #define GET_PHY_STAT_P0_PWDB(phy_stat)                                         \
0152     le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
0153 #define GET_PHY_STAT_P0_VGA(phy_stat)                                          \
0154     le32_get_bits(*((__le32 *)(phy_stat) + 0x03), GENMASK(12, 8))
0155 #define GET_PHY_STAT_P0_LNA_L(phy_stat)                                        \
0156     le32_get_bits(*((__le32 *)(phy_stat) + 0x03), GENMASK(15, 13))
0157 #define GET_PHY_STAT_P0_LNA_H(phy_stat)                                        \
0158     le32_get_bits(*((__le32 *)(phy_stat) + 0x03), BIT(23))
0159 #define BIT_LNA_H_MASK BIT(3)
0160 #define BIT_LNA_L_MASK GENMASK(2, 0)
0161
0162 /* phy status page1 */
0163 #define GET_PHY_STAT_P1_PWDB_A(phy_stat)                                       \
0164     le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
0165 #define GET_PHY_STAT_P1_PWDB_B(phy_stat)                                       \
0166     le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(23, 16))
0167 #define GET_PHY_STAT_P1_RF_MODE(phy_stat)                                      \
0168     le32_get_bits(*((__le32 *)(phy_stat) + 0x03), GENMASK(29, 28))
0169 #define GET_PHY_STAT_P1_L_RXSC(phy_stat)                                       \
0170     le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(11, 8))
0171 #define GET_PHY_STAT_P1_HT_RXSC(phy_stat)                                      \
0172     le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(15, 12))
0173 #define GET_PHY_STAT_P1_RXEVM_A(phy_stat)                                      \
0174     le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(7, 0))
0175 #define GET_PHY_STAT_P1_RXEVM_B(phy_stat)                                      \
0176     le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(15, 8))
0177 #define GET_PHY_STAT_P1_CFO_TAIL_A(phy_stat)                                 \
0178     le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(7, 0))
0179 #define GET_PHY_STAT_P1_CFO_TAIL_B(phy_stat)                                 \
0180     le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(15, 8))
0181 #define GET_PHY_STAT_P1_RXSNR_A(phy_stat)                                      \
0182     le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(7, 0))
0183 #define GET_PHY_STAT_P1_RXSNR_B(phy_stat)                                      \
0184     le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(15, 8))
0185
0186 #define REG_SYS_CTRL    0x000
0187 #define BIT_FEN_EN  BIT(26)
0188 #define REG_INIRTS_RATE_SEL 0x0480
0189 #define REG_HTSTFWT 0x800
0190 #define REG_RXPSEL  0x808
0191 #define BIT_RX_PSEL_RST     (BIT(28) | BIT(29))
0192 #define REG_TXPSEL  0x80c
0193 #define REG_RXCCAMSK    0x814
0194 #define REG_CCASEL  0x82c
0195 #define REG_PDMFTH  0x830
0196 #define REG_CCA2ND  0x838
0197 #define REG_L1WT    0x83c
0198 #define REG_L1PKWT  0x840
0199 #define REG_MRC     0x850
0200 #define REG_CLKTRK  0x860
0201 #define REG_ADCCLK  0x8ac
0202 #define REG_ADC160  0x8c4
0203 #define REG_ADC40   0x8c8
0204 #define REG_CHFIR   0x8f0
0205 #define REG_CDDTXP  0x93c
0206 #define REG_TXPSEL1 0x940
0207 #define REG_ACBB0   0x948
0208 #define REG_ACBBRXFIR   0x94c
0209 #define REG_ACGG2TBL    0x958
0210 #define REG_FAS     0x9a4
0211 #define REG_RXSB    0xa00
0212 #define REG_ADCINI  0xa04
0213 #define REG_PWRTH   0xa08
0214 #define REG_TXSF2   0xa24
0215 #define REG_TXSF6   0xa28
0216 #define REG_FA_CCK  0xa5c
0217 #define REG_RXDESC  0xa2c
0218 #define REG_ENTXCCK 0xa80
0219 #define BTG_LNA     0xfc84
0220 #define WLG_LNA     0x7532
0221 #define REG_ENRXCCA 0xa84
0222 #define BTG_CCA     0x0e
0223 #define WLG_CCA     0x12
0224 #define REG_PWRTH2  0xaa8
0225 #define REG_CSRATIO 0xaaa
0226 #define REG_TXFILTER    0xaac
0227 #define REG_CNTRST  0xb58
0228 #define REG_AGCTR_A 0xc08
0229 #define REG_TXSCALE_A   0xc1c
0230 #define REG_TXDFIR  0xc20
0231 #define REG_RXIGI_A 0xc50
0232 #define REG_TXAGCIDX    0xc94
0233 #define REG_TRSW    0xca0
0234 #define REG_RFESEL0 0xcb0
0235 #define REG_RFESEL8 0xcb4
0236 #define REG_RFECTL  0xcb8
0237 #define B_BTG_SWITCH    BIT(16)
0238 #define B_CTRL_SWITCH   BIT(18)
0239 #define B_WL_SWITCH (BIT(20) | BIT(22))
0240 #define B_WLG_SWITCH    BIT(21)
0241 #define B_WLA_SWITCH    BIT(23)
0242 #define REG_RFEINV  0xcbc
0243 #define REG_AGCTR_B 0xe08
0244 #define REG_RXIGI_B 0xe50
0245 #define REG_CRC_CCK 0xf04
0246 #define REG_CRC_OFDM    0xf14
0247 #define REG_CRC_HT  0xf10
0248 #define REG_CRC_VHT 0xf0c
0249 #define REG_CCA_OFDM    0xf08
0250 #define REG_FA_OFDM 0xf48
0251 #define REG_CCA_CCK 0xfcc
0252 #define REG_DMEM_CTRL   0x1080
0253 #define BIT_WL_RST  BIT(16)
0254 #define REG_ANTWT   0x1904
0255 #define REG_IQKFAILMSK  0x1bf0
0256 #define BIT_MASK_R_RFE_SEL_15   GENMASK(31, 28)
0257 #define BIT_SDIO_INT BIT(18)
0258 #define BT_CNT_ENABLE   0x1
0259 #define BIT_BCN_QUEUE   BIT(3)
0260 #define BCN_PRI_EN  0x1
0261 #define PTA_CTRL_PIN    0x66
0262 #define DPDT_CTRL_PIN   0x77
0263 #define ANTDIC_CTRL_PIN 0x88
0264 #define REG_CTRL_TYPE   0x67
0265 #define BIT_CTRL_TYPE1  BIT(5)
0266 #define BIT_CTRL_TYPE2  BIT(4)
0267 #define CTRL_TYPE_MASK  GENMASK(15, 8)
0268
0269 #define RF18_BAND_MASK      (BIT(16) | BIT(9) | BIT(8))
0270 #define RF18_BAND_2G        (0)
0271 #define RF18_BAND_5G        (BIT(16) | BIT(8))
0272 #define RF18_CHANNEL_MASK   (MASKBYTE0)
0273 #define RF18_RFSI_MASK      (BIT(18) | BIT(17))
0274 #define RF18_RFSI_GE        (BIT(17))
0275 #define RF18_RFSI_GT        (BIT(18))
0276 #define RF18_BW_MASK        (BIT(11) | BIT(10))
0277 #define RF18_BW_20M     (BIT(11) | BIT(10))
0278 #define RF18_BW_40M     (BIT(11))
0279 #define RF18_BW_80M     (BIT(10))
0280
0281 #endif