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0001 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
0002 /* Copyright(c) 2018-2019  Realtek Corporation
0003  */
0004 
0005 #include "main.h"
0006 #include "coex.h"
0007 #include "fw.h"
0008 #include "tx.h"
0009 #include "rx.h"
0010 #include "phy.h"
0011 #include "rtw8821c.h"
0012 #include "rtw8821c_table.h"
0013 #include "mac.h"
0014 #include "reg.h"
0015 #include "debug.h"
0016 #include "bf.h"
0017 #include "regd.h"
0018 
0019 static const s8 lna_gain_table_0[8] = {22, 8, -6, -22, -31, -40, -46, -52};
0020 static const s8 lna_gain_table_1[16] = {10, 6, 2, -2, -6, -10, -14, -17,
0021                     -20, -24, -28, -31, -34, -37, -40, -44};
0022 
0023 static void rtw8821ce_efuse_parsing(struct rtw_efuse *efuse,
0024                     struct rtw8821c_efuse *map)
0025 {
0026     ether_addr_copy(efuse->addr, map->e.mac_addr);
0027 }
0028 
0029 enum rtw8821ce_rf_set {
0030     SWITCH_TO_BTG,
0031     SWITCH_TO_WLG,
0032     SWITCH_TO_WLA,
0033     SWITCH_TO_BT,
0034 };
0035 
0036 static int rtw8821c_read_efuse(struct rtw_dev *rtwdev, u8 *log_map)
0037 {
0038     struct rtw_efuse *efuse = &rtwdev->efuse;
0039     struct rtw8821c_efuse *map;
0040     int i;
0041 
0042     map = (struct rtw8821c_efuse *)log_map;
0043 
0044     efuse->rfe_option = map->rfe_option;
0045     efuse->rf_board_option = map->rf_board_option;
0046     efuse->crystal_cap = map->xtal_k;
0047     efuse->pa_type_2g = map->pa_type;
0048     efuse->pa_type_5g = map->pa_type;
0049     efuse->lna_type_2g = map->lna_type_2g[0];
0050     efuse->lna_type_5g = map->lna_type_5g[0];
0051     efuse->channel_plan = map->channel_plan;
0052     efuse->country_code[0] = map->country_code[0];
0053     efuse->country_code[1] = map->country_code[1];
0054     efuse->bt_setting = map->rf_bt_setting;
0055     efuse->regd = map->rf_board_option & 0x7;
0056     efuse->thermal_meter[0] = map->thermal_meter;
0057     efuse->thermal_meter_k = map->thermal_meter;
0058     efuse->tx_bb_swing_setting_2g = map->tx_bb_swing_setting_2g;
0059     efuse->tx_bb_swing_setting_5g = map->tx_bb_swing_setting_5g;
0060 
0061     for (i = 0; i < 4; i++)
0062         efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i];
0063 
0064     if (rtwdev->efuse.rfe_option == 2 || rtwdev->efuse.rfe_option == 4)
0065         efuse->txpwr_idx_table[0].pwr_idx_2g = map->txpwr_idx_table[1].pwr_idx_2g;
0066 
0067     switch (rtw_hci_type(rtwdev)) {
0068     case RTW_HCI_TYPE_PCIE:
0069         rtw8821ce_efuse_parsing(efuse, map);
0070         break;
0071     default:
0072         /* unsupported now */
0073         return -ENOTSUPP;
0074     }
0075 
0076     return 0;
0077 }
0078 
0079 static const u32 rtw8821c_txscale_tbl[] = {
0080     0x081, 0x088, 0x090, 0x099, 0x0a2, 0x0ac, 0x0b6, 0x0c0, 0x0cc, 0x0d8,
0081     0x0e5, 0x0f2, 0x101, 0x110, 0x120, 0x131, 0x143, 0x156, 0x16a, 0x180,
0082     0x197, 0x1af, 0x1c8, 0x1e3, 0x200, 0x21e, 0x23e, 0x261, 0x285, 0x2ab,
0083     0x2d3, 0x2fe, 0x32b, 0x35c, 0x38e, 0x3c4, 0x3fe
0084 };
0085 
0086 static u8 rtw8821c_get_swing_index(struct rtw_dev *rtwdev)
0087 {
0088     u8 i = 0;
0089     u32 swing, table_value;
0090 
0091     swing = rtw_read32_mask(rtwdev, REG_TXSCALE_A, 0xffe00000);
0092     for (i = 0; i < ARRAY_SIZE(rtw8821c_txscale_tbl); i++) {
0093         table_value = rtw8821c_txscale_tbl[i];
0094         if (swing == table_value)
0095             break;
0096     }
0097 
0098     return i;
0099 }
0100 
0101 static void rtw8821c_pwrtrack_init(struct rtw_dev *rtwdev)
0102 {
0103     struct rtw_dm_info *dm_info = &rtwdev->dm_info;
0104     u8 swing_idx = rtw8821c_get_swing_index(rtwdev);
0105 
0106     if (swing_idx >= ARRAY_SIZE(rtw8821c_txscale_tbl))
0107         dm_info->default_ofdm_index = 24;
0108     else
0109         dm_info->default_ofdm_index = swing_idx;
0110 
0111     ewma_thermal_init(&dm_info->avg_thermal[RF_PATH_A]);
0112     dm_info->delta_power_index[RF_PATH_A] = 0;
0113     dm_info->delta_power_index_last[RF_PATH_A] = 0;
0114     dm_info->pwr_trk_triggered = false;
0115     dm_info->pwr_trk_init_trigger = true;
0116     dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k;
0117 }
0118 
0119 static void rtw8821c_phy_bf_init(struct rtw_dev *rtwdev)
0120 {
0121     rtw_bf_phy_init(rtwdev);
0122     /* Grouping bitmap parameters */
0123     rtw_write32(rtwdev, 0x1C94, 0xAFFFAFFF);
0124 }
0125 
0126 static void rtw8821c_phy_set_param(struct rtw_dev *rtwdev)
0127 {
0128     struct rtw_hal *hal = &rtwdev->hal;
0129     u8 crystal_cap, val;
0130 
0131     /* power on BB/RF domain */
0132     val = rtw_read8(rtwdev, REG_SYS_FUNC_EN);
0133     val |= BIT_FEN_PCIEA;
0134     rtw_write8(rtwdev, REG_SYS_FUNC_EN, val);
0135 
0136     /* toggle BB reset */
0137     val |= BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST;
0138     rtw_write8(rtwdev, REG_SYS_FUNC_EN, val);
0139     val &= ~(BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST);
0140     rtw_write8(rtwdev, REG_SYS_FUNC_EN, val);
0141     val |= BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST;
0142     rtw_write8(rtwdev, REG_SYS_FUNC_EN, val);
0143 
0144     rtw_write8(rtwdev, REG_RF_CTRL,
0145            BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB);
0146     usleep_range(10, 11);
0147     rtw_write8(rtwdev, REG_WLRF1 + 3,
0148            BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB);
0149     usleep_range(10, 11);
0150 
0151     /* pre init before header files config */
0152     rtw_write32_clr(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST);
0153 
0154     rtw_phy_load_tables(rtwdev);
0155 
0156     crystal_cap = rtwdev->efuse.crystal_cap & 0x3F;
0157     rtw_write32_mask(rtwdev, REG_AFE_XTAL_CTRL, 0x7e000000, crystal_cap);
0158     rtw_write32_mask(rtwdev, REG_AFE_PLL_CTRL, 0x7e, crystal_cap);
0159     rtw_write32_mask(rtwdev, REG_CCK0_FAREPORT, BIT(18) | BIT(22), 0);
0160 
0161     /* post init after header files config */
0162     rtw_write32_set(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST);
0163     hal->ch_param[0] = rtw_read32_mask(rtwdev, REG_TXSF2, MASKDWORD);
0164     hal->ch_param[1] = rtw_read32_mask(rtwdev, REG_TXSF6, MASKDWORD);
0165     hal->ch_param[2] = rtw_read32_mask(rtwdev, REG_TXFILTER, MASKDWORD);
0166 
0167     rtw_phy_init(rtwdev);
0168     rtwdev->dm_info.cck_pd_default = rtw_read8(rtwdev, REG_CSRATIO) & 0x1f;
0169 
0170     rtw8821c_pwrtrack_init(rtwdev);
0171 
0172     rtw8821c_phy_bf_init(rtwdev);
0173 }
0174 
0175 static int rtw8821c_mac_init(struct rtw_dev *rtwdev)
0176 {
0177     u32 value32;
0178     u16 pre_txcnt;
0179 
0180     /* protocol configuration */
0181     rtw_write8(rtwdev, REG_AMPDU_MAX_TIME_V1, WLAN_AMPDU_MAX_TIME);
0182     rtw_write8_set(rtwdev, REG_TX_HANG_CTRL, BIT_EN_EOF_V1);
0183     pre_txcnt = WLAN_PRE_TXCNT_TIME_TH | BIT_EN_PRECNT;
0184     rtw_write8(rtwdev, REG_PRECNT_CTRL, (u8)(pre_txcnt & 0xFF));
0185     rtw_write8(rtwdev, REG_PRECNT_CTRL + 1, (u8)(pre_txcnt >> 8));
0186     value32 = WLAN_RTS_LEN_TH | (WLAN_RTS_TX_TIME_TH << 8) |
0187           (WLAN_MAX_AGG_PKT_LIMIT << 16) |
0188           (WLAN_RTS_MAX_AGG_PKT_LIMIT << 24);
0189     rtw_write32(rtwdev, REG_PROT_MODE_CTRL, value32);
0190     rtw_write16(rtwdev, REG_BAR_MODE_CTRL + 2,
0191             WLAN_BAR_RETRY_LIMIT | WLAN_RA_TRY_RATE_AGG_LIMIT << 8);
0192     rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING, FAST_EDCA_VO_TH);
0193     rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING + 2, FAST_EDCA_VI_TH);
0194     rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING, FAST_EDCA_BE_TH);
0195     rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING + 2, FAST_EDCA_BK_TH);
0196     rtw_write8_set(rtwdev, REG_INIRTS_RATE_SEL, BIT(5));
0197 
0198     /* EDCA configuration */
0199     rtw_write8_clr(rtwdev, REG_TIMER0_SRC_SEL, BIT_TSFT_SEL_TIMER0);
0200     rtw_write16(rtwdev, REG_TXPAUSE, 0);
0201     rtw_write8(rtwdev, REG_SLOT, WLAN_SLOT_TIME);
0202     rtw_write8(rtwdev, REG_PIFS, WLAN_PIFS_TIME);
0203     rtw_write32(rtwdev, REG_SIFS, WLAN_SIFS_CFG);
0204     rtw_write16(rtwdev, REG_EDCA_VO_PARAM + 2, WLAN_VO_TXOP_LIMIT);
0205     rtw_write16(rtwdev, REG_EDCA_VI_PARAM + 2, WLAN_VI_TXOP_LIMIT);
0206     rtw_write32(rtwdev, REG_RD_NAV_NXT, WLAN_NAV_CFG);
0207     rtw_write16(rtwdev, REG_RXTSF_OFFSET_CCK, WLAN_RX_TSF_CFG);
0208 
0209     /* Set beacon cotnrol - enable TSF and other related functions */
0210     rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION);
0211 
0212     /* Set send beacon related registers */
0213     rtw_write32(rtwdev, REG_TBTT_PROHIBIT, WLAN_TBTT_TIME);
0214     rtw_write8(rtwdev, REG_DRVERLYINT, WLAN_DRV_EARLY_INT);
0215     rtw_write8(rtwdev, REG_BCNDMATIM, WLAN_BCN_DMA_TIME);
0216     rtw_write8_clr(rtwdev, REG_TX_PTCL_CTRL + 1, BIT_SIFS_BK_EN >> 8);
0217 
0218     /* WMAC configuration */
0219     rtw_write32(rtwdev, REG_RXFLTMAP0, WLAN_RX_FILTER0);
0220     rtw_write16(rtwdev, REG_RXFLTMAP2, WLAN_RX_FILTER2);
0221     rtw_write32(rtwdev, REG_RCR, WLAN_RCR_CFG);
0222     rtw_write8(rtwdev, REG_RX_PKT_LIMIT, WLAN_RXPKT_MAX_SZ_512);
0223     rtw_write8(rtwdev, REG_TCR + 2, WLAN_TX_FUNC_CFG2);
0224     rtw_write8(rtwdev, REG_TCR + 1, WLAN_TX_FUNC_CFG1);
0225     rtw_write8(rtwdev, REG_ACKTO_CCK, 0x40);
0226     rtw_write8_set(rtwdev, REG_WMAC_TRXPTCL_CTL_H, BIT(1));
0227     rtw_write8_set(rtwdev, REG_SND_PTCL_CTRL,
0228                BIT_DIS_CHK_VHTSIGB_CRC);
0229     rtw_write32(rtwdev, REG_WMAC_OPTION_FUNCTION + 8, WLAN_MAC_OPT_FUNC2);
0230     rtw_write8(rtwdev, REG_WMAC_OPTION_FUNCTION + 4, WLAN_MAC_OPT_NORM_FUNC1);
0231 
0232     return 0;
0233 }
0234 
0235 static void rtw8821c_cfg_ldo25(struct rtw_dev *rtwdev, bool enable)
0236 {
0237     u8 ldo_pwr;
0238 
0239     ldo_pwr = rtw_read8(rtwdev, REG_LDO_EFUSE_CTRL + 3);
0240     ldo_pwr = enable ? ldo_pwr | BIT(7) : ldo_pwr & ~BIT(7);
0241     rtw_write8(rtwdev, REG_LDO_EFUSE_CTRL + 3, ldo_pwr);
0242 }
0243 
0244 static void rtw8821c_switch_rf_set(struct rtw_dev *rtwdev, u8 rf_set)
0245 {
0246     u32 reg;
0247 
0248     rtw_write32_set(rtwdev, REG_DMEM_CTRL, BIT_WL_RST);
0249     rtw_write32_set(rtwdev, REG_SYS_CTRL, BIT_FEN_EN);
0250 
0251     reg = rtw_read32(rtwdev, REG_RFECTL);
0252     switch (rf_set) {
0253     case SWITCH_TO_BTG:
0254         reg |= B_BTG_SWITCH;
0255         reg &= ~(B_CTRL_SWITCH | B_WL_SWITCH | B_WLG_SWITCH |
0256              B_WLA_SWITCH);
0257         rtw_write32_mask(rtwdev, REG_ENRXCCA, MASKBYTE2, BTG_CCA);
0258         rtw_write32_mask(rtwdev, REG_ENTXCCK, MASKLWORD, BTG_LNA);
0259         break;
0260     case SWITCH_TO_WLG:
0261         reg |= B_WL_SWITCH | B_WLG_SWITCH;
0262         reg &= ~(B_BTG_SWITCH | B_CTRL_SWITCH | B_WLA_SWITCH);
0263         rtw_write32_mask(rtwdev, REG_ENRXCCA, MASKBYTE2, WLG_CCA);
0264         rtw_write32_mask(rtwdev, REG_ENTXCCK, MASKLWORD, WLG_LNA);
0265         break;
0266     case SWITCH_TO_WLA:
0267         reg |= B_WL_SWITCH | B_WLA_SWITCH;
0268         reg &= ~(B_BTG_SWITCH | B_CTRL_SWITCH | B_WLG_SWITCH);
0269         break;
0270     case SWITCH_TO_BT:
0271     default:
0272         break;
0273     }
0274 
0275     rtw_write32(rtwdev, REG_RFECTL, reg);
0276 }
0277 
0278 static void rtw8821c_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw)
0279 {
0280     u32 rf_reg18;
0281 
0282     rf_reg18 = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK);
0283 
0284     rf_reg18 &= ~(RF18_BAND_MASK | RF18_CHANNEL_MASK | RF18_RFSI_MASK |
0285               RF18_BW_MASK);
0286 
0287     rf_reg18 |= (channel <= 14 ? RF18_BAND_2G : RF18_BAND_5G);
0288     rf_reg18 |= (channel & RF18_CHANNEL_MASK);
0289 
0290     if (channel >= 100 && channel <= 140)
0291         rf_reg18 |= RF18_RFSI_GE;
0292     else if (channel > 140)
0293         rf_reg18 |= RF18_RFSI_GT;
0294 
0295     switch (bw) {
0296     case RTW_CHANNEL_WIDTH_5:
0297     case RTW_CHANNEL_WIDTH_10:
0298     case RTW_CHANNEL_WIDTH_20:
0299     default:
0300         rf_reg18 |= RF18_BW_20M;
0301         break;
0302     case RTW_CHANNEL_WIDTH_40:
0303         rf_reg18 |= RF18_BW_40M;
0304         break;
0305     case RTW_CHANNEL_WIDTH_80:
0306         rf_reg18 |= RF18_BW_80M;
0307         break;
0308     }
0309 
0310     if (channel <= 14) {
0311         if (rtwdev->efuse.rfe_option == 0)
0312             rtw8821c_switch_rf_set(rtwdev, SWITCH_TO_WLG);
0313         else if (rtwdev->efuse.rfe_option == 2 ||
0314              rtwdev->efuse.rfe_option == 4)
0315             rtw8821c_switch_rf_set(rtwdev, SWITCH_TO_BTG);
0316         rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(6), 0x1);
0317         rtw_write_rf(rtwdev, RF_PATH_A, 0x64, 0xf, 0xf);
0318     } else {
0319         rtw8821c_switch_rf_set(rtwdev, SWITCH_TO_WLA);
0320         rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(6), 0x0);
0321     }
0322 
0323     rtw_write_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK, rf_reg18);
0324 
0325     rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 0);
0326     rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 1);
0327 }
0328 
0329 static void rtw8821c_set_channel_rxdfir(struct rtw_dev *rtwdev, u8 bw)
0330 {
0331     if (bw == RTW_CHANNEL_WIDTH_40) {
0332         /* RX DFIR for BW40 */
0333         rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2);
0334         rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2);
0335         rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0);
0336         rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x0);
0337     } else if (bw == RTW_CHANNEL_WIDTH_80) {
0338         /* RX DFIR for BW80 */
0339         rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2);
0340         rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x1);
0341         rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0);
0342         rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x1);
0343     } else {
0344         /* RX DFIR for BW20, BW10 and BW5 */
0345         rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2);
0346         rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2);
0347         rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x1);
0348         rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x0);
0349     }
0350 }
0351 
0352 static void rtw8821c_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw,
0353                     u8 primary_ch_idx)
0354 {
0355     struct rtw_hal *hal = &rtwdev->hal;
0356     u32 val32;
0357 
0358     if (channel <= 14) {
0359         rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x1);
0360         rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x0);
0361         rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x0);
0362         rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 15);
0363 
0364         rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x0);
0365         rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x96a);
0366         if (channel == 14) {
0367             rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x0000b81c);
0368             rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x0000);
0369             rtw_write32_mask(rtwdev, REG_TXFILTER, MASKDWORD, 0x00003667);
0370         } else {
0371             rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD,
0372                      hal->ch_param[0]);
0373             rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD,
0374                      hal->ch_param[1] & MASKLWORD);
0375             rtw_write32_mask(rtwdev, REG_TXFILTER, MASKDWORD,
0376                      hal->ch_param[2]);
0377         }
0378     } else if (channel > 35) {
0379         rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x1);
0380         rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x1);
0381         rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x0);
0382         rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 15);
0383 
0384         if (channel >= 36 && channel <= 64)
0385             rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x1);
0386         else if (channel >= 100 && channel <= 144)
0387             rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x2);
0388         else if (channel >= 149)
0389             rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x3);
0390 
0391         if (channel >= 36 && channel <= 48)
0392             rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x494);
0393         else if (channel >= 52 && channel <= 64)
0394             rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x453);
0395         else if (channel >= 100 && channel <= 116)
0396             rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x452);
0397         else if (channel >= 118 && channel <= 177)
0398             rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x412);
0399     }
0400 
0401     switch (bw) {
0402     case RTW_CHANNEL_WIDTH_20:
0403     default:
0404         val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
0405         val32 &= 0xffcffc00;
0406         val32 |= 0x10010000;
0407         rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
0408 
0409         rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1);
0410         break;
0411     case RTW_CHANNEL_WIDTH_40:
0412         if (primary_ch_idx == 1)
0413             rtw_write32_set(rtwdev, REG_RXSB, BIT(4));
0414         else
0415             rtw_write32_clr(rtwdev, REG_RXSB, BIT(4));
0416 
0417         val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
0418         val32 &= 0xff3ff300;
0419         val32 |= 0x20020000 | ((primary_ch_idx & 0xf) << 2) |
0420              RTW_CHANNEL_WIDTH_40;
0421         rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
0422 
0423         rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1);
0424         break;
0425     case RTW_CHANNEL_WIDTH_80:
0426         val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
0427         val32 &= 0xfcffcf00;
0428         val32 |= 0x40040000 | ((primary_ch_idx & 0xf) << 2) |
0429              RTW_CHANNEL_WIDTH_80;
0430         rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
0431 
0432         rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1);
0433         break;
0434     case RTW_CHANNEL_WIDTH_5:
0435         val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
0436         val32 &= 0xefcefc00;
0437         val32 |= 0x200240;
0438         rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
0439 
0440         rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0);
0441         rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1);
0442         break;
0443     case RTW_CHANNEL_WIDTH_10:
0444         val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
0445         val32 &= 0xefcefc00;
0446         val32 |= 0x300380;
0447         rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
0448 
0449         rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0);
0450         rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1);
0451         break;
0452     }
0453 }
0454 
0455 static u32 rtw8821c_get_bb_swing(struct rtw_dev *rtwdev, u8 channel)
0456 {
0457     struct rtw_efuse efuse = rtwdev->efuse;
0458     u8 tx_bb_swing;
0459     u32 swing2setting[4] = {0x200, 0x16a, 0x101, 0x0b6};
0460 
0461     tx_bb_swing = channel <= 14 ? efuse.tx_bb_swing_setting_2g :
0462                       efuse.tx_bb_swing_setting_5g;
0463     if (tx_bb_swing > 9)
0464         tx_bb_swing = 0;
0465 
0466     return swing2setting[(tx_bb_swing / 3)];
0467 }
0468 
0469 static void rtw8821c_set_channel_bb_swing(struct rtw_dev *rtwdev, u8 channel,
0470                       u8 bw, u8 primary_ch_idx)
0471 {
0472     rtw_write32_mask(rtwdev, REG_TXSCALE_A, GENMASK(31, 21),
0473              rtw8821c_get_bb_swing(rtwdev, channel));
0474     rtw8821c_pwrtrack_init(rtwdev);
0475 }
0476 
0477 static void rtw8821c_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw,
0478                  u8 primary_chan_idx)
0479 {
0480     rtw8821c_set_channel_bb(rtwdev, channel, bw, primary_chan_idx);
0481     rtw8821c_set_channel_bb_swing(rtwdev, channel, bw, primary_chan_idx);
0482     rtw_set_channel_mac(rtwdev, channel, bw, primary_chan_idx);
0483     rtw8821c_set_channel_rf(rtwdev, channel, bw);
0484     rtw8821c_set_channel_rxdfir(rtwdev, bw);
0485 }
0486 
0487 static s8 get_cck_rx_pwr(struct rtw_dev *rtwdev, u8 lna_idx, u8 vga_idx)
0488 {
0489     struct rtw_efuse *efuse = &rtwdev->efuse;
0490     const s8 *lna_gain_table;
0491     int lna_gain_table_size;
0492     s8 rx_pwr_all = 0;
0493     s8 lna_gain = 0;
0494 
0495     if (efuse->rfe_option == 0) {
0496         lna_gain_table = lna_gain_table_0;
0497         lna_gain_table_size = ARRAY_SIZE(lna_gain_table_0);
0498     } else {
0499         lna_gain_table = lna_gain_table_1;
0500         lna_gain_table_size = ARRAY_SIZE(lna_gain_table_1);
0501     }
0502 
0503     if (lna_idx >= lna_gain_table_size) {
0504         rtw_warn(rtwdev, "incorrect lna index (%d)\n", lna_idx);
0505         return -120;
0506     }
0507 
0508     lna_gain = lna_gain_table[lna_idx];
0509     rx_pwr_all = lna_gain - 2 * vga_idx;
0510 
0511     return rx_pwr_all;
0512 }
0513 
0514 static void query_phy_status_page0(struct rtw_dev *rtwdev, u8 *phy_status,
0515                    struct rtw_rx_pkt_stat *pkt_stat)
0516 {
0517     struct rtw_dm_info *dm_info = &rtwdev->dm_info;
0518     s8 rx_power;
0519     u8 lna_idx = 0;
0520     u8 vga_idx = 0;
0521 
0522     vga_idx = GET_PHY_STAT_P0_VGA(phy_status);
0523     lna_idx = FIELD_PREP(BIT_LNA_H_MASK, GET_PHY_STAT_P0_LNA_H(phy_status)) |
0524           FIELD_PREP(BIT_LNA_L_MASK, GET_PHY_STAT_P0_LNA_L(phy_status));
0525     rx_power = get_cck_rx_pwr(rtwdev, lna_idx, vga_idx);
0526 
0527     pkt_stat->rx_power[RF_PATH_A] = rx_power;
0528     pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1);
0529     dm_info->rssi[RF_PATH_A] = pkt_stat->rssi;
0530     pkt_stat->bw = RTW_CHANNEL_WIDTH_20;
0531     pkt_stat->signal_power = rx_power;
0532 }
0533 
0534 static void query_phy_status_page1(struct rtw_dev *rtwdev, u8 *phy_status,
0535                    struct rtw_rx_pkt_stat *pkt_stat)
0536 {
0537     struct rtw_dm_info *dm_info = &rtwdev->dm_info;
0538     u8 rxsc, bw;
0539     s8 min_rx_power = -120;
0540 
0541     if (pkt_stat->rate > DESC_RATE11M && pkt_stat->rate < DESC_RATEMCS0)
0542         rxsc = GET_PHY_STAT_P1_L_RXSC(phy_status);
0543     else
0544         rxsc = GET_PHY_STAT_P1_HT_RXSC(phy_status);
0545 
0546     if (rxsc >= 1 && rxsc <= 8)
0547         bw = RTW_CHANNEL_WIDTH_20;
0548     else if (rxsc >= 9 && rxsc <= 12)
0549         bw = RTW_CHANNEL_WIDTH_40;
0550     else if (rxsc >= 13)
0551         bw = RTW_CHANNEL_WIDTH_80;
0552     else
0553         bw = GET_PHY_STAT_P1_RF_MODE(phy_status);
0554 
0555     pkt_stat->rx_power[RF_PATH_A] = GET_PHY_STAT_P1_PWDB_A(phy_status) - 110;
0556     pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1);
0557     dm_info->rssi[RF_PATH_A] = pkt_stat->rssi;
0558     pkt_stat->bw = bw;
0559     pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A],
0560                      min_rx_power);
0561 }
0562 
0563 static void query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status,
0564                  struct rtw_rx_pkt_stat *pkt_stat)
0565 {
0566     u8 page;
0567 
0568     page = *phy_status & 0xf;
0569 
0570     switch (page) {
0571     case 0:
0572         query_phy_status_page0(rtwdev, phy_status, pkt_stat);
0573         break;
0574     case 1:
0575         query_phy_status_page1(rtwdev, phy_status, pkt_stat);
0576         break;
0577     default:
0578         rtw_warn(rtwdev, "unused phy status page (%d)\n", page);
0579         return;
0580     }
0581 }
0582 
0583 static void rtw8821c_query_rx_desc(struct rtw_dev *rtwdev, u8 *rx_desc,
0584                    struct rtw_rx_pkt_stat *pkt_stat,
0585                    struct ieee80211_rx_status *rx_status)
0586 {
0587     struct ieee80211_hdr *hdr;
0588     u32 desc_sz = rtwdev->chip->rx_pkt_desc_sz;
0589     u8 *phy_status = NULL;
0590 
0591     memset(pkt_stat, 0, sizeof(*pkt_stat));
0592 
0593     pkt_stat->phy_status = GET_RX_DESC_PHYST(rx_desc);
0594     pkt_stat->icv_err = GET_RX_DESC_ICV_ERR(rx_desc);
0595     pkt_stat->crc_err = GET_RX_DESC_CRC32(rx_desc);
0596     pkt_stat->decrypted = !GET_RX_DESC_SWDEC(rx_desc) &&
0597                   GET_RX_DESC_ENC_TYPE(rx_desc) != RX_DESC_ENC_NONE;
0598     pkt_stat->is_c2h = GET_RX_DESC_C2H(rx_desc);
0599     pkt_stat->pkt_len = GET_RX_DESC_PKT_LEN(rx_desc);
0600     pkt_stat->drv_info_sz = GET_RX_DESC_DRV_INFO_SIZE(rx_desc);
0601     pkt_stat->shift = GET_RX_DESC_SHIFT(rx_desc);
0602     pkt_stat->rate = GET_RX_DESC_RX_RATE(rx_desc);
0603     pkt_stat->cam_id = GET_RX_DESC_MACID(rx_desc);
0604     pkt_stat->ppdu_cnt = GET_RX_DESC_PPDU_CNT(rx_desc);
0605     pkt_stat->tsf_low = GET_RX_DESC_TSFL(rx_desc);
0606 
0607     /* drv_info_sz is in unit of 8-bytes */
0608     pkt_stat->drv_info_sz *= 8;
0609 
0610     /* c2h cmd pkt's rx/phy status is not interested */
0611     if (pkt_stat->is_c2h)
0612         return;
0613 
0614     hdr = (struct ieee80211_hdr *)(rx_desc + desc_sz + pkt_stat->shift +
0615                        pkt_stat->drv_info_sz);
0616     if (pkt_stat->phy_status) {
0617         phy_status = rx_desc + desc_sz + pkt_stat->shift;
0618         query_phy_status(rtwdev, phy_status, pkt_stat);
0619     }
0620 
0621     rtw_rx_fill_rx_status(rtwdev, pkt_stat, hdr, rx_status, phy_status);
0622 }
0623 
0624 static void
0625 rtw8821c_set_tx_power_index_by_rate(struct rtw_dev *rtwdev, u8 path, u8 rs)
0626 {
0627     struct rtw_hal *hal = &rtwdev->hal;
0628     static const u32 offset_txagc[2] = {0x1d00, 0x1d80};
0629     static u32 phy_pwr_idx;
0630     u8 rate, rate_idx, pwr_index, shift;
0631     int j;
0632 
0633     for (j = 0; j < rtw_rate_size[rs]; j++) {
0634         rate = rtw_rate_section[rs][j];
0635         pwr_index = hal->tx_pwr_tbl[path][rate];
0636         shift = rate & 0x3;
0637         phy_pwr_idx |= ((u32)pwr_index << (shift * 8));
0638         if (shift == 0x3 || rate == DESC_RATEVHT1SS_MCS9) {
0639             rate_idx = rate & 0xfc;
0640             rtw_write32(rtwdev, offset_txagc[path] + rate_idx,
0641                     phy_pwr_idx);
0642             phy_pwr_idx = 0;
0643         }
0644     }
0645 }
0646 
0647 static void rtw8821c_set_tx_power_index(struct rtw_dev *rtwdev)
0648 {
0649     struct rtw_hal *hal = &rtwdev->hal;
0650     int rs, path;
0651 
0652     for (path = 0; path < hal->rf_path_num; path++) {
0653         for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++) {
0654             if (rs == RTW_RATE_SECTION_HT_2S ||
0655                 rs == RTW_RATE_SECTION_VHT_2S)
0656                 continue;
0657             rtw8821c_set_tx_power_index_by_rate(rtwdev, path, rs);
0658         }
0659     }
0660 }
0661 
0662 static void rtw8821c_false_alarm_statistics(struct rtw_dev *rtwdev)
0663 {
0664     struct rtw_dm_info *dm_info = &rtwdev->dm_info;
0665     u32 cck_enable;
0666     u32 cck_fa_cnt;
0667     u32 ofdm_fa_cnt;
0668     u32 crc32_cnt;
0669     u32 cca32_cnt;
0670 
0671     cck_enable = rtw_read32(rtwdev, REG_RXPSEL) & BIT(28);
0672     cck_fa_cnt = rtw_read16(rtwdev, REG_FA_CCK);
0673     ofdm_fa_cnt = rtw_read16(rtwdev, REG_FA_OFDM);
0674 
0675     dm_info->cck_fa_cnt = cck_fa_cnt;
0676     dm_info->ofdm_fa_cnt = ofdm_fa_cnt;
0677     if (cck_enable)
0678         dm_info->total_fa_cnt += cck_fa_cnt;
0679     dm_info->total_fa_cnt = ofdm_fa_cnt;
0680 
0681     crc32_cnt = rtw_read32(rtwdev, REG_CRC_CCK);
0682     dm_info->cck_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt);
0683     dm_info->cck_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt);
0684 
0685     crc32_cnt = rtw_read32(rtwdev, REG_CRC_OFDM);
0686     dm_info->ofdm_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt);
0687     dm_info->ofdm_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt);
0688 
0689     crc32_cnt = rtw_read32(rtwdev, REG_CRC_HT);
0690     dm_info->ht_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt);
0691     dm_info->ht_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt);
0692 
0693     crc32_cnt = rtw_read32(rtwdev, REG_CRC_VHT);
0694     dm_info->vht_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt);
0695     dm_info->vht_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt);
0696 
0697     cca32_cnt = rtw_read32(rtwdev, REG_CCA_OFDM);
0698     dm_info->ofdm_cca_cnt = FIELD_GET(GENMASK(31, 16), cca32_cnt);
0699     dm_info->total_cca_cnt = dm_info->ofdm_cca_cnt;
0700     if (cck_enable) {
0701         cca32_cnt = rtw_read32(rtwdev, REG_CCA_CCK);
0702         dm_info->cck_cca_cnt = FIELD_GET(GENMASK(15, 0), cca32_cnt);
0703         dm_info->total_cca_cnt += dm_info->cck_cca_cnt;
0704     }
0705 
0706     rtw_write32_set(rtwdev, REG_FAS, BIT(17));
0707     rtw_write32_clr(rtwdev, REG_FAS, BIT(17));
0708     rtw_write32_clr(rtwdev, REG_RXDESC, BIT(15));
0709     rtw_write32_set(rtwdev, REG_RXDESC, BIT(15));
0710     rtw_write32_set(rtwdev, REG_CNTRST, BIT(0));
0711     rtw_write32_clr(rtwdev, REG_CNTRST, BIT(0));
0712 }
0713 
0714 static void rtw8821c_do_iqk(struct rtw_dev *rtwdev)
0715 {
0716     static int do_iqk_cnt;
0717     struct rtw_iqk_para para = {.clear = 0, .segment_iqk = 0};
0718     u32 rf_reg, iqk_fail_mask;
0719     int counter;
0720     bool reload;
0721 
0722     if (rtw_is_assoc(rtwdev))
0723         para.segment_iqk = 1;
0724 
0725     rtw_fw_do_iqk(rtwdev, &para);
0726 
0727     for (counter = 0; counter < 300; counter++) {
0728         rf_reg = rtw_read_rf(rtwdev, RF_PATH_A, RF_DTXLOK, RFREG_MASK);
0729         if (rf_reg == 0xabcde)
0730             break;
0731         msleep(20);
0732     }
0733     rtw_write_rf(rtwdev, RF_PATH_A, RF_DTXLOK, RFREG_MASK, 0x0);
0734 
0735     reload = !!rtw_read32_mask(rtwdev, REG_IQKFAILMSK, BIT(16));
0736     iqk_fail_mask = rtw_read32_mask(rtwdev, REG_IQKFAILMSK, GENMASK(7, 0));
0737     rtw_dbg(rtwdev, RTW_DBG_PHY,
0738         "iqk counter=%d reload=%d do_iqk_cnt=%d n_iqk_fail(mask)=0x%02x\n",
0739         counter, reload, ++do_iqk_cnt, iqk_fail_mask);
0740 }
0741 
0742 static void rtw8821c_phy_calibration(struct rtw_dev *rtwdev)
0743 {
0744     rtw8821c_do_iqk(rtwdev);
0745 }
0746 
0747 /* for coex */
0748 static void rtw8821c_coex_cfg_init(struct rtw_dev *rtwdev)
0749 {
0750     /* enable TBTT nterrupt */
0751     rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION);
0752 
0753     /* BT report packet sample rate */
0754     rtw_write8_mask(rtwdev, REG_BT_TDMA_TIME, BIT_MASK_SAMPLE_RATE, 0x5);
0755 
0756     /* enable BT counter statistics */
0757     rtw_write8(rtwdev, REG_BT_STAT_CTRL, BT_CNT_ENABLE);
0758 
0759     /* enable PTA (3-wire function form BT side) */
0760     rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN);
0761     rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_PO_BT_PTA_PINS);
0762 
0763     /* enable PTA (tx/rx signal form WiFi side) */
0764     rtw_write8_set(rtwdev, REG_QUEUE_CTRL, BIT_PTA_WL_TX_EN);
0765     /* wl tx signal to PTA not case EDCCA */
0766     rtw_write8_clr(rtwdev, REG_QUEUE_CTRL, BIT_PTA_EDCCA_EN);
0767     /* GNT_BT=1 while select both */
0768     rtw_write16_set(rtwdev, REG_BT_COEX_V2, BIT_GNT_BT_POLARITY);
0769 
0770     /* beacon queue always hi-pri  */
0771     rtw_write8_mask(rtwdev, REG_BT_COEX_TABLE_H + 3, BIT_BCN_QUEUE,
0772             BCN_PRI_EN);
0773 }
0774 
0775 static void rtw8821c_coex_cfg_ant_switch(struct rtw_dev *rtwdev, u8 ctrl_type,
0776                      u8 pos_type)
0777 {
0778     struct rtw_coex *coex = &rtwdev->coex;
0779     struct rtw_coex_dm *coex_dm = &coex->dm;
0780     struct rtw_coex_rfe *coex_rfe = &coex->rfe;
0781     u32 switch_status = FIELD_PREP(CTRL_TYPE_MASK, ctrl_type) | pos_type;
0782     bool polarity_inverse;
0783     u8 regval = 0;
0784 
0785     if (switch_status == coex_dm->cur_switch_status)
0786         return;
0787 
0788     if (coex_rfe->wlg_at_btg) {
0789         ctrl_type = COEX_SWITCH_CTRL_BY_BBSW;
0790 
0791         if (coex_rfe->ant_switch_polarity)
0792             pos_type = COEX_SWITCH_TO_WLA;
0793         else
0794             pos_type = COEX_SWITCH_TO_WLG_BT;
0795     }
0796 
0797     coex_dm->cur_switch_status = switch_status;
0798 
0799     if (coex_rfe->ant_switch_diversity &&
0800         ctrl_type == COEX_SWITCH_CTRL_BY_BBSW)
0801         ctrl_type = COEX_SWITCH_CTRL_BY_ANTDIV;
0802 
0803     polarity_inverse = (coex_rfe->ant_switch_polarity == 1);
0804 
0805     switch (ctrl_type) {
0806     default:
0807     case COEX_SWITCH_CTRL_BY_BBSW:
0808         rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN);
0809         rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL);
0810         /* BB SW, DPDT use RFE_ctrl8 and RFE_ctrl9 as ctrl pin */
0811         rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89,
0812                 DPDT_CTRL_PIN);
0813 
0814         if (pos_type == COEX_SWITCH_TO_WLG_BT) {
0815             if (coex_rfe->rfe_module_type != 0x4 &&
0816                 coex_rfe->rfe_module_type != 0x2)
0817                 regval = 0x3;
0818             else
0819                 regval = (!polarity_inverse ? 0x2 : 0x1);
0820         } else if (pos_type == COEX_SWITCH_TO_WLG) {
0821             regval = (!polarity_inverse ? 0x2 : 0x1);
0822         } else {
0823             regval = (!polarity_inverse ? 0x1 : 0x2);
0824         }
0825 
0826         rtw_write32_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_R_RFE_SEL_15,
0827                  regval);
0828         break;
0829     case COEX_SWITCH_CTRL_BY_PTA:
0830         rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN);
0831         rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL);
0832         /* PTA,  DPDT use RFE_ctrl8 and RFE_ctrl9 as ctrl pin */
0833         rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89,
0834                 PTA_CTRL_PIN);
0835 
0836         regval = (!polarity_inverse ? 0x2 : 0x1);
0837         rtw_write32_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_R_RFE_SEL_15,
0838                  regval);
0839         break;
0840     case COEX_SWITCH_CTRL_BY_ANTDIV:
0841         rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN);
0842         rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL);
0843         rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89,
0844                 ANTDIC_CTRL_PIN);
0845         break;
0846     case COEX_SWITCH_CTRL_BY_MAC:
0847         rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN);
0848 
0849         regval = (!polarity_inverse ? 0x0 : 0x1);
0850         rtw_write8_mask(rtwdev, REG_PAD_CTRL1, BIT_SW_DPDT_SEL_DATA,
0851                 regval);
0852         break;
0853     case COEX_SWITCH_CTRL_BY_FW:
0854         rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN);
0855         rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL);
0856         break;
0857     case COEX_SWITCH_CTRL_BY_BT:
0858         rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN);
0859         rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL);
0860         break;
0861     }
0862 
0863     if (ctrl_type == COEX_SWITCH_CTRL_BY_BT) {
0864         rtw_write8_clr(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE1);
0865         rtw_write8_clr(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE2);
0866     } else {
0867         rtw_write8_set(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE1);
0868         rtw_write8_set(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE2);
0869     }
0870 }
0871 
0872 static void rtw8821c_coex_cfg_gnt_fix(struct rtw_dev *rtwdev)
0873 {}
0874 
0875 static void rtw8821c_coex_cfg_gnt_debug(struct rtw_dev *rtwdev)
0876 {
0877     rtw_write32_clr(rtwdev, REG_PAD_CTRL1, BIT_BTGP_SPI_EN);
0878     rtw_write32_clr(rtwdev, REG_PAD_CTRL1, BIT_BTGP_JTAG_EN);
0879     rtw_write32_clr(rtwdev, REG_GPIO_MUXCFG, BIT_FSPI_EN);
0880     rtw_write32_clr(rtwdev, REG_PAD_CTRL1, BIT_LED1DIS);
0881     rtw_write32_clr(rtwdev, REG_SYS_SDIO_CTRL, BIT_SDIO_INT);
0882     rtw_write32_clr(rtwdev, REG_SYS_SDIO_CTRL, BIT_DBG_GNT_WL_BT);
0883 }
0884 
0885 static void rtw8821c_coex_cfg_rfe_type(struct rtw_dev *rtwdev)
0886 {
0887     struct rtw_coex *coex = &rtwdev->coex;
0888     struct rtw_coex_rfe *coex_rfe = &coex->rfe;
0889     struct rtw_efuse *efuse = &rtwdev->efuse;
0890 
0891     coex_rfe->rfe_module_type = efuse->rfe_option;
0892     coex_rfe->ant_switch_polarity = 0;
0893     coex_rfe->ant_switch_exist = true;
0894     coex_rfe->wlg_at_btg = false;
0895 
0896     switch (coex_rfe->rfe_module_type) {
0897     case 0:
0898     case 8:
0899     case 1:
0900     case 9:  /* 1-Ant, Main, WLG */
0901     default: /* 2-Ant, DPDT, WLG */
0902         break;
0903     case 2:
0904     case 10: /* 1-Ant, Main, BTG */
0905     case 7:
0906     case 15: /* 2-Ant, DPDT, BTG */
0907         coex_rfe->wlg_at_btg = true;
0908         break;
0909     case 3:
0910     case 11: /* 1-Ant, Aux, WLG */
0911         coex_rfe->ant_switch_polarity = 1;
0912         break;
0913     case 4:
0914     case 12: /* 1-Ant, Aux, BTG */
0915         coex_rfe->wlg_at_btg = true;
0916         coex_rfe->ant_switch_polarity = 1;
0917         break;
0918     case 5:
0919     case 13: /* 2-Ant, no switch, WLG */
0920     case 6:
0921     case 14: /* 2-Ant, no antenna switch, WLG */
0922         coex_rfe->ant_switch_exist = false;
0923         break;
0924     }
0925 }
0926 
0927 static void rtw8821c_coex_cfg_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr)
0928 {
0929     struct rtw_coex *coex = &rtwdev->coex;
0930     struct rtw_coex_dm *coex_dm = &coex->dm;
0931     struct rtw_efuse *efuse = &rtwdev->efuse;
0932     bool share_ant = efuse->share_ant;
0933 
0934     if (share_ant)
0935         return;
0936 
0937     if (wl_pwr == coex_dm->cur_wl_pwr_lvl)
0938         return;
0939 
0940     coex_dm->cur_wl_pwr_lvl = wl_pwr;
0941 }
0942 
0943 static void rtw8821c_coex_cfg_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain)
0944 {}
0945 
0946 static void
0947 rtw8821c_txagc_swing_offset(struct rtw_dev *rtwdev, u8 pwr_idx_offset,
0948                 s8 pwr_idx_offset_lower,
0949                 s8 *txagc_idx, u8 *swing_idx)
0950 {
0951     struct rtw_dm_info *dm_info = &rtwdev->dm_info;
0952     s8 delta_pwr_idx = dm_info->delta_power_index[RF_PATH_A];
0953     u8 swing_upper_bound = dm_info->default_ofdm_index + 10;
0954     u8 swing_lower_bound = 0;
0955     u8 max_pwr_idx_offset = 0xf;
0956     s8 agc_index = 0;
0957     u8 swing_index = dm_info->default_ofdm_index;
0958 
0959     pwr_idx_offset = min_t(u8, pwr_idx_offset, max_pwr_idx_offset);
0960     pwr_idx_offset_lower = max_t(s8, pwr_idx_offset_lower, -15);
0961 
0962     if (delta_pwr_idx >= 0) {
0963         if (delta_pwr_idx <= pwr_idx_offset) {
0964             agc_index = delta_pwr_idx;
0965             swing_index = dm_info->default_ofdm_index;
0966         } else if (delta_pwr_idx > pwr_idx_offset) {
0967             agc_index = pwr_idx_offset;
0968             swing_index = dm_info->default_ofdm_index +
0969                     delta_pwr_idx - pwr_idx_offset;
0970             swing_index = min_t(u8, swing_index, swing_upper_bound);
0971         }
0972     } else if (delta_pwr_idx < 0) {
0973         if (delta_pwr_idx >= pwr_idx_offset_lower) {
0974             agc_index = delta_pwr_idx;
0975             swing_index = dm_info->default_ofdm_index;
0976         } else if (delta_pwr_idx < pwr_idx_offset_lower) {
0977             if (dm_info->default_ofdm_index >
0978                 (pwr_idx_offset_lower - delta_pwr_idx))
0979                 swing_index = dm_info->default_ofdm_index +
0980                     delta_pwr_idx - pwr_idx_offset_lower;
0981             else
0982                 swing_index = swing_lower_bound;
0983 
0984             agc_index = pwr_idx_offset_lower;
0985         }
0986     }
0987 
0988     if (swing_index >= ARRAY_SIZE(rtw8821c_txscale_tbl)) {
0989         rtw_warn(rtwdev, "swing index overflow\n");
0990         swing_index = ARRAY_SIZE(rtw8821c_txscale_tbl) - 1;
0991     }
0992 
0993     *txagc_idx = agc_index;
0994     *swing_idx = swing_index;
0995 }
0996 
0997 static void rtw8821c_pwrtrack_set_pwr(struct rtw_dev *rtwdev, u8 pwr_idx_offset,
0998                       s8 pwr_idx_offset_lower)
0999 {
1000     s8 txagc_idx;
1001     u8 swing_idx;
1002 
1003     rtw8821c_txagc_swing_offset(rtwdev, pwr_idx_offset, pwr_idx_offset_lower,
1004                     &txagc_idx, &swing_idx);
1005     rtw_write32_mask(rtwdev, REG_TXAGCIDX, GENMASK(6, 1), txagc_idx);
1006     rtw_write32_mask(rtwdev, REG_TXSCALE_A, GENMASK(31, 21),
1007              rtw8821c_txscale_tbl[swing_idx]);
1008 }
1009 
1010 static void rtw8821c_pwrtrack_set(struct rtw_dev *rtwdev)
1011 {
1012     struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1013     u8 pwr_idx_offset, tx_pwr_idx;
1014     s8 pwr_idx_offset_lower;
1015     u8 channel = rtwdev->hal.current_channel;
1016     u8 band_width = rtwdev->hal.current_band_width;
1017     u8 regd = rtw_regd_get(rtwdev);
1018     u8 tx_rate = dm_info->tx_rate;
1019     u8 max_pwr_idx = rtwdev->chip->max_power_index;
1020 
1021     tx_pwr_idx = rtw_phy_get_tx_power_index(rtwdev, RF_PATH_A, tx_rate,
1022                         band_width, channel, regd);
1023 
1024     tx_pwr_idx = min_t(u8, tx_pwr_idx, max_pwr_idx);
1025 
1026     pwr_idx_offset = max_pwr_idx - tx_pwr_idx;
1027     pwr_idx_offset_lower = 0 - tx_pwr_idx;
1028 
1029     rtw8821c_pwrtrack_set_pwr(rtwdev, pwr_idx_offset, pwr_idx_offset_lower);
1030 }
1031 
1032 static void rtw8821c_phy_pwrtrack(struct rtw_dev *rtwdev)
1033 {
1034     struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1035     struct rtw_swing_table swing_table;
1036     u8 thermal_value, delta;
1037 
1038     rtw_phy_config_swing_table(rtwdev, &swing_table);
1039 
1040     if (rtwdev->efuse.thermal_meter[0] == 0xff)
1041         return;
1042 
1043     thermal_value = rtw_read_rf(rtwdev, RF_PATH_A, RF_T_METER, 0xfc00);
1044 
1045     rtw_phy_pwrtrack_avg(rtwdev, thermal_value, RF_PATH_A);
1046 
1047     if (dm_info->pwr_trk_init_trigger)
1048         dm_info->pwr_trk_init_trigger = false;
1049     else if (!rtw_phy_pwrtrack_thermal_changed(rtwdev, thermal_value,
1050                            RF_PATH_A))
1051         goto iqk;
1052 
1053     delta = rtw_phy_pwrtrack_get_delta(rtwdev, RF_PATH_A);
1054 
1055     delta = min_t(u8, delta, RTW_PWR_TRK_TBL_SZ - 1);
1056 
1057     dm_info->delta_power_index[RF_PATH_A] =
1058         rtw_phy_pwrtrack_get_pwridx(rtwdev, &swing_table, RF_PATH_A,
1059                         RF_PATH_A, delta);
1060     if (dm_info->delta_power_index[RF_PATH_A] ==
1061             dm_info->delta_power_index_last[RF_PATH_A])
1062         goto iqk;
1063     else
1064         dm_info->delta_power_index_last[RF_PATH_A] =
1065             dm_info->delta_power_index[RF_PATH_A];
1066     rtw8821c_pwrtrack_set(rtwdev);
1067 
1068 iqk:
1069     if (rtw_phy_pwrtrack_need_iqk(rtwdev))
1070         rtw8821c_do_iqk(rtwdev);
1071 }
1072 
1073 static void rtw8821c_pwr_track(struct rtw_dev *rtwdev)
1074 {
1075     struct rtw_efuse *efuse = &rtwdev->efuse;
1076     struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1077 
1078     if (efuse->power_track_type != 0)
1079         return;
1080 
1081     if (!dm_info->pwr_trk_triggered) {
1082         rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER,
1083                  GENMASK(17, 16), 0x03);
1084         dm_info->pwr_trk_triggered = true;
1085         return;
1086     }
1087 
1088     rtw8821c_phy_pwrtrack(rtwdev);
1089     dm_info->pwr_trk_triggered = false;
1090 }
1091 
1092 static void rtw8821c_bf_config_bfee_su(struct rtw_dev *rtwdev,
1093                        struct rtw_vif *vif,
1094                        struct rtw_bfee *bfee, bool enable)
1095 {
1096     if (enable)
1097         rtw_bf_enable_bfee_su(rtwdev, vif, bfee);
1098     else
1099         rtw_bf_remove_bfee_su(rtwdev, bfee);
1100 }
1101 
1102 static void rtw8821c_bf_config_bfee_mu(struct rtw_dev *rtwdev,
1103                        struct rtw_vif *vif,
1104                        struct rtw_bfee *bfee, bool enable)
1105 {
1106     if (enable)
1107         rtw_bf_enable_bfee_mu(rtwdev, vif, bfee);
1108     else
1109         rtw_bf_remove_bfee_mu(rtwdev, bfee);
1110 }
1111 
1112 static void rtw8821c_bf_config_bfee(struct rtw_dev *rtwdev, struct rtw_vif *vif,
1113                     struct rtw_bfee *bfee, bool enable)
1114 {
1115     if (bfee->role == RTW_BFEE_SU)
1116         rtw8821c_bf_config_bfee_su(rtwdev, vif, bfee, enable);
1117     else if (bfee->role == RTW_BFEE_MU)
1118         rtw8821c_bf_config_bfee_mu(rtwdev, vif, bfee, enable);
1119     else
1120         rtw_warn(rtwdev, "wrong bfee role\n");
1121 }
1122 
1123 static void rtw8821c_phy_cck_pd_set(struct rtw_dev *rtwdev, u8 new_lvl)
1124 {
1125     struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1126     u8 pd[CCK_PD_LV_MAX] = {3, 7, 13, 13, 13};
1127     u8 cck_n_rx;
1128 
1129     rtw_dbg(rtwdev, RTW_DBG_PHY, "lv: (%d) -> (%d)\n",
1130         dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A], new_lvl);
1131 
1132     if (dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] == new_lvl)
1133         return;
1134 
1135     cck_n_rx = (rtw_read8_mask(rtwdev, REG_CCK0_FAREPORT, BIT_CCK0_2RX) &&
1136             rtw_read8_mask(rtwdev, REG_CCK0_FAREPORT, BIT_CCK0_MRC)) ? 2 : 1;
1137     rtw_dbg(rtwdev, RTW_DBG_PHY,
1138         "is_linked=%d, lv=%d, n_rx=%d, cs_ratio=0x%x, pd_th=0x%x, cck_fa_avg=%d\n",
1139         rtw_is_assoc(rtwdev), new_lvl, cck_n_rx,
1140         dm_info->cck_pd_default + new_lvl * 2,
1141         pd[new_lvl], dm_info->cck_fa_avg);
1142 
1143     dm_info->cck_fa_avg = CCK_FA_AVG_RESET;
1144 
1145     dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] = new_lvl;
1146     rtw_write32_mask(rtwdev, REG_PWRTH, 0x3f0000, pd[new_lvl]);
1147     rtw_write32_mask(rtwdev, REG_PWRTH2, 0x1f0000,
1148              dm_info->cck_pd_default + new_lvl * 2);
1149 }
1150 
1151 static struct rtw_pwr_seq_cmd trans_carddis_to_cardemu_8821c[] = {
1152     {0x0086,
1153      RTW_PWR_CUT_ALL_MSK,
1154      RTW_PWR_INTF_SDIO_MSK,
1155      RTW_PWR_ADDR_SDIO,
1156      RTW_PWR_CMD_WRITE, BIT(0), 0},
1157     {0x0086,
1158      RTW_PWR_CUT_ALL_MSK,
1159      RTW_PWR_INTF_SDIO_MSK,
1160      RTW_PWR_ADDR_SDIO,
1161      RTW_PWR_CMD_POLLING, BIT(1), BIT(1)},
1162     {0x004A,
1163      RTW_PWR_CUT_ALL_MSK,
1164      RTW_PWR_INTF_USB_MSK,
1165      RTW_PWR_ADDR_MAC,
1166      RTW_PWR_CMD_WRITE, BIT(0), 0},
1167     {0x0005,
1168      RTW_PWR_CUT_ALL_MSK,
1169      RTW_PWR_INTF_ALL_MSK,
1170      RTW_PWR_ADDR_MAC,
1171      RTW_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0},
1172     {0x0300,
1173      RTW_PWR_CUT_ALL_MSK,
1174      RTW_PWR_INTF_PCI_MSK,
1175      RTW_PWR_ADDR_MAC,
1176      RTW_PWR_CMD_WRITE, 0xFF, 0},
1177     {0x0301,
1178      RTW_PWR_CUT_ALL_MSK,
1179      RTW_PWR_INTF_PCI_MSK,
1180      RTW_PWR_ADDR_MAC,
1181      RTW_PWR_CMD_WRITE, 0xFF, 0},
1182     {0xFFFF,
1183      RTW_PWR_CUT_ALL_MSK,
1184      RTW_PWR_INTF_ALL_MSK,
1185      0,
1186      RTW_PWR_CMD_END, 0, 0},
1187 };
1188 
1189 static struct rtw_pwr_seq_cmd trans_cardemu_to_act_8821c[] = {
1190     {0x0020,
1191      RTW_PWR_CUT_ALL_MSK,
1192      RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1193      RTW_PWR_ADDR_MAC,
1194      RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1195     {0x0001,
1196      RTW_PWR_CUT_ALL_MSK,
1197      RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1198      RTW_PWR_ADDR_MAC,
1199      RTW_PWR_CMD_DELAY, 1, RTW_PWR_DELAY_MS},
1200     {0x0000,
1201      RTW_PWR_CUT_ALL_MSK,
1202      RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1203      RTW_PWR_ADDR_MAC,
1204      RTW_PWR_CMD_WRITE, BIT(5), 0},
1205     {0x0005,
1206      RTW_PWR_CUT_ALL_MSK,
1207      RTW_PWR_INTF_ALL_MSK,
1208      RTW_PWR_ADDR_MAC,
1209      RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0},
1210     {0x0075,
1211      RTW_PWR_CUT_ALL_MSK,
1212      RTW_PWR_INTF_PCI_MSK,
1213      RTW_PWR_ADDR_MAC,
1214      RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1215     {0x0006,
1216      RTW_PWR_CUT_ALL_MSK,
1217      RTW_PWR_INTF_ALL_MSK,
1218      RTW_PWR_ADDR_MAC,
1219      RTW_PWR_CMD_POLLING, BIT(1), BIT(1)},
1220     {0x0075,
1221      RTW_PWR_CUT_ALL_MSK,
1222      RTW_PWR_INTF_PCI_MSK,
1223      RTW_PWR_ADDR_MAC,
1224      RTW_PWR_CMD_WRITE, BIT(0), 0},
1225     {0x0006,
1226      RTW_PWR_CUT_ALL_MSK,
1227      RTW_PWR_INTF_ALL_MSK,
1228      RTW_PWR_ADDR_MAC,
1229      RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1230     {0x0005,
1231      RTW_PWR_CUT_ALL_MSK,
1232      RTW_PWR_INTF_ALL_MSK,
1233      RTW_PWR_ADDR_MAC,
1234      RTW_PWR_CMD_WRITE, BIT(7), 0},
1235     {0x0005,
1236      RTW_PWR_CUT_ALL_MSK,
1237      RTW_PWR_INTF_ALL_MSK,
1238      RTW_PWR_ADDR_MAC,
1239      RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0},
1240     {0x10C3,
1241      RTW_PWR_CUT_ALL_MSK,
1242      RTW_PWR_INTF_USB_MSK,
1243      RTW_PWR_ADDR_MAC,
1244      RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1245     {0x0005,
1246      RTW_PWR_CUT_ALL_MSK,
1247      RTW_PWR_INTF_ALL_MSK,
1248      RTW_PWR_ADDR_MAC,
1249      RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1250     {0x0005,
1251      RTW_PWR_CUT_ALL_MSK,
1252      RTW_PWR_INTF_ALL_MSK,
1253      RTW_PWR_ADDR_MAC,
1254      RTW_PWR_CMD_POLLING, BIT(0), 0},
1255     {0x0020,
1256      RTW_PWR_CUT_ALL_MSK,
1257      RTW_PWR_INTF_ALL_MSK,
1258      RTW_PWR_ADDR_MAC,
1259      RTW_PWR_CMD_WRITE, BIT(3), BIT(3)},
1260     {0x0074,
1261      RTW_PWR_CUT_ALL_MSK,
1262      RTW_PWR_INTF_PCI_MSK,
1263      RTW_PWR_ADDR_MAC,
1264      RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
1265     {0x0022,
1266      RTW_PWR_CUT_ALL_MSK,
1267      RTW_PWR_INTF_PCI_MSK,
1268      RTW_PWR_ADDR_MAC,
1269      RTW_PWR_CMD_WRITE, BIT(1), 0},
1270     {0x0062,
1271      RTW_PWR_CUT_ALL_MSK,
1272      RTW_PWR_INTF_PCI_MSK,
1273      RTW_PWR_ADDR_MAC,
1274      RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)),
1275      (BIT(7) | BIT(6) | BIT(5))},
1276     {0x0061,
1277      RTW_PWR_CUT_ALL_MSK,
1278      RTW_PWR_INTF_PCI_MSK,
1279      RTW_PWR_ADDR_MAC,
1280      RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 0},
1281     {0x007C,
1282      RTW_PWR_CUT_ALL_MSK,
1283      RTW_PWR_INTF_ALL_MSK,
1284      RTW_PWR_ADDR_MAC,
1285      RTW_PWR_CMD_WRITE, BIT(1), 0},
1286     {0xFFFF,
1287      RTW_PWR_CUT_ALL_MSK,
1288      RTW_PWR_INTF_ALL_MSK,
1289      0,
1290      RTW_PWR_CMD_END, 0, 0},
1291 };
1292 
1293 static struct rtw_pwr_seq_cmd trans_act_to_cardemu_8821c[] = {
1294     {0x0093,
1295      RTW_PWR_CUT_ALL_MSK,
1296      RTW_PWR_INTF_ALL_MSK,
1297      RTW_PWR_ADDR_MAC,
1298      RTW_PWR_CMD_WRITE, BIT(3), 0},
1299     {0x001F,
1300      RTW_PWR_CUT_ALL_MSK,
1301      RTW_PWR_INTF_ALL_MSK,
1302      RTW_PWR_ADDR_MAC,
1303      RTW_PWR_CMD_WRITE, 0xFF, 0},
1304     {0x0049,
1305      RTW_PWR_CUT_ALL_MSK,
1306      RTW_PWR_INTF_ALL_MSK,
1307      RTW_PWR_ADDR_MAC,
1308      RTW_PWR_CMD_WRITE, BIT(1), 0},
1309     {0x0006,
1310      RTW_PWR_CUT_ALL_MSK,
1311      RTW_PWR_INTF_ALL_MSK,
1312      RTW_PWR_ADDR_MAC,
1313      RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1314     {0x0002,
1315      RTW_PWR_CUT_ALL_MSK,
1316      RTW_PWR_INTF_ALL_MSK,
1317      RTW_PWR_ADDR_MAC,
1318      RTW_PWR_CMD_WRITE, BIT(1), 0},
1319     {0x10C3,
1320      RTW_PWR_CUT_ALL_MSK,
1321      RTW_PWR_INTF_USB_MSK,
1322      RTW_PWR_ADDR_MAC,
1323      RTW_PWR_CMD_WRITE, BIT(0), 0},
1324     {0x0005,
1325      RTW_PWR_CUT_ALL_MSK,
1326      RTW_PWR_INTF_ALL_MSK,
1327      RTW_PWR_ADDR_MAC,
1328      RTW_PWR_CMD_WRITE, BIT(1), BIT(1)},
1329     {0x0005,
1330      RTW_PWR_CUT_ALL_MSK,
1331      RTW_PWR_INTF_ALL_MSK,
1332      RTW_PWR_ADDR_MAC,
1333      RTW_PWR_CMD_POLLING, BIT(1), 0},
1334     {0x0020,
1335      RTW_PWR_CUT_ALL_MSK,
1336      RTW_PWR_INTF_ALL_MSK,
1337      RTW_PWR_ADDR_MAC,
1338      RTW_PWR_CMD_WRITE, BIT(3), 0},
1339     {0x0000,
1340      RTW_PWR_CUT_ALL_MSK,
1341      RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1342      RTW_PWR_ADDR_MAC,
1343      RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
1344     {0xFFFF,
1345      RTW_PWR_CUT_ALL_MSK,
1346      RTW_PWR_INTF_ALL_MSK,
1347      0,
1348      RTW_PWR_CMD_END, 0, 0},
1349 };
1350 
1351 static struct rtw_pwr_seq_cmd trans_cardemu_to_carddis_8821c[] = {
1352     {0x0007,
1353      RTW_PWR_CUT_ALL_MSK,
1354      RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1355      RTW_PWR_ADDR_MAC,
1356      RTW_PWR_CMD_WRITE, 0xFF, 0x20},
1357     {0x0067,
1358      RTW_PWR_CUT_ALL_MSK,
1359      RTW_PWR_INTF_ALL_MSK,
1360      RTW_PWR_ADDR_MAC,
1361      RTW_PWR_CMD_WRITE, BIT(5), 0},
1362     {0x0005,
1363      RTW_PWR_CUT_ALL_MSK,
1364      RTW_PWR_INTF_PCI_MSK,
1365      RTW_PWR_ADDR_MAC,
1366      RTW_PWR_CMD_WRITE, BIT(2), BIT(2)},
1367     {0x004A,
1368      RTW_PWR_CUT_ALL_MSK,
1369      RTW_PWR_INTF_USB_MSK,
1370      RTW_PWR_ADDR_MAC,
1371      RTW_PWR_CMD_WRITE, BIT(0), 0},
1372     {0x0067,
1373      RTW_PWR_CUT_ALL_MSK,
1374      RTW_PWR_INTF_SDIO_MSK,
1375      RTW_PWR_ADDR_MAC,
1376      RTW_PWR_CMD_WRITE, BIT(5), 0},
1377     {0x0067,
1378      RTW_PWR_CUT_ALL_MSK,
1379      RTW_PWR_INTF_SDIO_MSK,
1380      RTW_PWR_ADDR_MAC,
1381      RTW_PWR_CMD_WRITE, BIT(4), 0},
1382     {0x004F,
1383      RTW_PWR_CUT_ALL_MSK,
1384      RTW_PWR_INTF_SDIO_MSK,
1385      RTW_PWR_ADDR_MAC,
1386      RTW_PWR_CMD_WRITE, BIT(0), 0},
1387     {0x0067,
1388      RTW_PWR_CUT_ALL_MSK,
1389      RTW_PWR_INTF_SDIO_MSK,
1390      RTW_PWR_ADDR_MAC,
1391      RTW_PWR_CMD_WRITE, BIT(1), 0},
1392     {0x0046,
1393      RTW_PWR_CUT_ALL_MSK,
1394      RTW_PWR_INTF_SDIO_MSK,
1395      RTW_PWR_ADDR_MAC,
1396      RTW_PWR_CMD_WRITE, BIT(6), BIT(6)},
1397     {0x0067,
1398      RTW_PWR_CUT_ALL_MSK,
1399      RTW_PWR_INTF_SDIO_MSK,
1400      RTW_PWR_ADDR_MAC,
1401      RTW_PWR_CMD_WRITE, BIT(2), 0},
1402     {0x0046,
1403      RTW_PWR_CUT_ALL_MSK,
1404      RTW_PWR_INTF_SDIO_MSK,
1405      RTW_PWR_ADDR_MAC,
1406      RTW_PWR_CMD_WRITE, BIT(7), BIT(7)},
1407     {0x0062,
1408      RTW_PWR_CUT_ALL_MSK,
1409      RTW_PWR_INTF_SDIO_MSK,
1410      RTW_PWR_ADDR_MAC,
1411      RTW_PWR_CMD_WRITE, BIT(4), BIT(4)},
1412     {0x0081,
1413      RTW_PWR_CUT_ALL_MSK,
1414      RTW_PWR_INTF_ALL_MSK,
1415      RTW_PWR_ADDR_MAC,
1416      RTW_PWR_CMD_WRITE, BIT(7) | BIT(6), 0},
1417     {0x0005,
1418      RTW_PWR_CUT_ALL_MSK,
1419      RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1420      RTW_PWR_ADDR_MAC,
1421      RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)},
1422     {0x0086,
1423      RTW_PWR_CUT_ALL_MSK,
1424      RTW_PWR_INTF_SDIO_MSK,
1425      RTW_PWR_ADDR_SDIO,
1426      RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1427     {0x0086,
1428      RTW_PWR_CUT_ALL_MSK,
1429      RTW_PWR_INTF_SDIO_MSK,
1430      RTW_PWR_ADDR_SDIO,
1431      RTW_PWR_CMD_POLLING, BIT(1), 0},
1432     {0x0090,
1433      RTW_PWR_CUT_ALL_MSK,
1434      RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_PCI_MSK,
1435      RTW_PWR_ADDR_MAC,
1436      RTW_PWR_CMD_WRITE, BIT(1), 0},
1437     {0x0044,
1438      RTW_PWR_CUT_ALL_MSK,
1439      RTW_PWR_INTF_SDIO_MSK,
1440      RTW_PWR_ADDR_SDIO,
1441      RTW_PWR_CMD_WRITE, 0xFF, 0},
1442     {0x0040,
1443      RTW_PWR_CUT_ALL_MSK,
1444      RTW_PWR_INTF_SDIO_MSK,
1445      RTW_PWR_ADDR_SDIO,
1446      RTW_PWR_CMD_WRITE, 0xFF, 0x90},
1447     {0x0041,
1448      RTW_PWR_CUT_ALL_MSK,
1449      RTW_PWR_INTF_SDIO_MSK,
1450      RTW_PWR_ADDR_SDIO,
1451      RTW_PWR_CMD_WRITE, 0xFF, 0x00},
1452     {0x0042,
1453      RTW_PWR_CUT_ALL_MSK,
1454      RTW_PWR_INTF_SDIO_MSK,
1455      RTW_PWR_ADDR_SDIO,
1456      RTW_PWR_CMD_WRITE, 0xFF, 0x04},
1457     {0xFFFF,
1458      RTW_PWR_CUT_ALL_MSK,
1459      RTW_PWR_INTF_ALL_MSK,
1460      0,
1461      RTW_PWR_CMD_END, 0, 0},
1462 };
1463 
1464 static const struct rtw_pwr_seq_cmd *card_enable_flow_8821c[] = {
1465     trans_carddis_to_cardemu_8821c,
1466     trans_cardemu_to_act_8821c,
1467     NULL
1468 };
1469 
1470 static const struct rtw_pwr_seq_cmd *card_disable_flow_8821c[] = {
1471     trans_act_to_cardemu_8821c,
1472     trans_cardemu_to_carddis_8821c,
1473     NULL
1474 };
1475 
1476 static const struct rtw_intf_phy_para usb2_param_8821c[] = {
1477     {0xFFFF, 0x00,
1478      RTW_IP_SEL_PHY,
1479      RTW_INTF_PHY_CUT_ALL,
1480      RTW_INTF_PHY_PLATFORM_ALL},
1481 };
1482 
1483 static const struct rtw_intf_phy_para usb3_param_8821c[] = {
1484     {0xFFFF, 0x0000,
1485      RTW_IP_SEL_PHY,
1486      RTW_INTF_PHY_CUT_ALL,
1487      RTW_INTF_PHY_PLATFORM_ALL},
1488 };
1489 
1490 static const struct rtw_intf_phy_para pcie_gen1_param_8821c[] = {
1491     {0x0009, 0x6380,
1492      RTW_IP_SEL_PHY,
1493      RTW_INTF_PHY_CUT_ALL,
1494      RTW_INTF_PHY_PLATFORM_ALL},
1495     {0xFFFF, 0x0000,
1496      RTW_IP_SEL_PHY,
1497      RTW_INTF_PHY_CUT_ALL,
1498      RTW_INTF_PHY_PLATFORM_ALL},
1499 };
1500 
1501 static const struct rtw_intf_phy_para pcie_gen2_param_8821c[] = {
1502     {0xFFFF, 0x0000,
1503      RTW_IP_SEL_PHY,
1504      RTW_INTF_PHY_CUT_ALL,
1505      RTW_INTF_PHY_PLATFORM_ALL},
1506 };
1507 
1508 static const struct rtw_intf_phy_para_table phy_para_table_8821c = {
1509     .usb2_para  = usb2_param_8821c,
1510     .usb3_para  = usb3_param_8821c,
1511     .gen1_para  = pcie_gen1_param_8821c,
1512     .gen2_para  = pcie_gen2_param_8821c,
1513     .n_usb2_para    = ARRAY_SIZE(usb2_param_8821c),
1514     .n_usb3_para    = ARRAY_SIZE(usb2_param_8821c),
1515     .n_gen1_para    = ARRAY_SIZE(pcie_gen1_param_8821c),
1516     .n_gen2_para    = ARRAY_SIZE(pcie_gen2_param_8821c),
1517 };
1518 
1519 static const struct rtw_rfe_def rtw8821c_rfe_defs[] = {
1520     [0] = RTW_DEF_RFE(8821c, 0, 0),
1521     [2] = RTW_DEF_RFE_EXT(8821c, 0, 0, 2),
1522     [4] = RTW_DEF_RFE_EXT(8821c, 0, 0, 2),
1523     [6] = RTW_DEF_RFE(8821c, 0, 0),
1524 };
1525 
1526 static struct rtw_hw_reg rtw8821c_dig[] = {
1527     [0] = { .addr = 0xc50, .mask = 0x7f },
1528 };
1529 
1530 static const struct rtw_ltecoex_addr rtw8821c_ltecoex_addr = {
1531     .ctrl = LTECOEX_ACCESS_CTRL,
1532     .wdata = LTECOEX_WRITE_DATA,
1533     .rdata = LTECOEX_READ_DATA,
1534 };
1535 
1536 static struct rtw_page_table page_table_8821c[] = {
1537     /* not sure what [0] stands for */
1538     {16, 16, 16, 14, 1},
1539     {16, 16, 16, 14, 1},
1540     {16, 16, 0, 0, 1},
1541     {16, 16, 16, 0, 1},
1542     {16, 16, 16, 14, 1},
1543 };
1544 
1545 static struct rtw_rqpn rqpn_table_8821c[] = {
1546     /* not sure what [0] stands for */
1547     {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
1548      RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
1549      RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
1550     {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
1551      RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
1552      RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
1553     {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
1554      RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_HIGH,
1555      RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH},
1556     {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
1557      RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
1558      RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH},
1559     {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
1560      RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
1561      RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
1562 };
1563 
1564 static struct rtw_prioq_addrs prioq_addrs_8821c = {
1565     .prio[RTW_DMA_MAPPING_EXTRA] = {
1566         .rsvd = REG_FIFOPAGE_INFO_4, .avail = REG_FIFOPAGE_INFO_4 + 2,
1567     },
1568     .prio[RTW_DMA_MAPPING_LOW] = {
1569         .rsvd = REG_FIFOPAGE_INFO_2, .avail = REG_FIFOPAGE_INFO_2 + 2,
1570     },
1571     .prio[RTW_DMA_MAPPING_NORMAL] = {
1572         .rsvd = REG_FIFOPAGE_INFO_3, .avail = REG_FIFOPAGE_INFO_3 + 2,
1573     },
1574     .prio[RTW_DMA_MAPPING_HIGH] = {
1575         .rsvd = REG_FIFOPAGE_INFO_1, .avail = REG_FIFOPAGE_INFO_1 + 2,
1576     },
1577     .wsize = true,
1578 };
1579 
1580 static struct rtw_chip_ops rtw8821c_ops = {
1581     .phy_set_param      = rtw8821c_phy_set_param,
1582     .read_efuse     = rtw8821c_read_efuse,
1583     .query_rx_desc      = rtw8821c_query_rx_desc,
1584     .set_channel        = rtw8821c_set_channel,
1585     .mac_init       = rtw8821c_mac_init,
1586     .read_rf        = rtw_phy_read_rf,
1587     .write_rf       = rtw_phy_write_rf_reg_sipi,
1588     .set_antenna        = NULL,
1589     .set_tx_power_index = rtw8821c_set_tx_power_index,
1590     .cfg_ldo25      = rtw8821c_cfg_ldo25,
1591     .false_alarm_statistics = rtw8821c_false_alarm_statistics,
1592     .phy_calibration    = rtw8821c_phy_calibration,
1593     .cck_pd_set     = rtw8821c_phy_cck_pd_set,
1594     .pwr_track      = rtw8821c_pwr_track,
1595     .config_bfee        = rtw8821c_bf_config_bfee,
1596     .set_gid_table      = rtw_bf_set_gid_table,
1597     .cfg_csi_rate       = rtw_bf_cfg_csi_rate,
1598 
1599     .coex_set_init      = rtw8821c_coex_cfg_init,
1600     .coex_set_ant_switch    = rtw8821c_coex_cfg_ant_switch,
1601     .coex_set_gnt_fix   = rtw8821c_coex_cfg_gnt_fix,
1602     .coex_set_gnt_debug = rtw8821c_coex_cfg_gnt_debug,
1603     .coex_set_rfe_type  = rtw8821c_coex_cfg_rfe_type,
1604     .coex_set_wl_tx_power   = rtw8821c_coex_cfg_wl_tx_power,
1605     .coex_set_wl_rx_gain    = rtw8821c_coex_cfg_wl_rx_gain,
1606 };
1607 
1608 /* rssi in percentage % (dbm = % - 100) */
1609 static const u8 wl_rssi_step_8821c[] = {101, 45, 101, 40};
1610 static const u8 bt_rssi_step_8821c[] = {101, 101, 101, 101};
1611 
1612 /* Shared-Antenna Coex Table */
1613 static const struct coex_table_para table_sant_8821c[] = {
1614     {0x55555555, 0x55555555}, /* case-0 */
1615     {0x55555555, 0x55555555},
1616     {0x66555555, 0x66555555},
1617     {0xaaaaaaaa, 0xaaaaaaaa},
1618     {0x5a5a5a5a, 0x5a5a5a5a},
1619     {0xfafafafa, 0xfafafafa}, /* case-5 */
1620     {0x6a5a5555, 0xaaaaaaaa},
1621     {0x6a5a56aa, 0x6a5a56aa},
1622     {0x6a5a5a5a, 0x6a5a5a5a},
1623     {0x66555555, 0x5a5a5a5a},
1624     {0x66555555, 0x6a5a5a5a}, /* case-10 */
1625     {0x66555555, 0xaaaaaaaa},
1626     {0x66555555, 0x6a5a5aaa},
1627     {0x66555555, 0x6aaa6aaa},
1628     {0x66555555, 0x6a5a5aaa},
1629     {0x66555555, 0xaaaaaaaa}, /* case-15 */
1630     {0xffff55ff, 0xfafafafa},
1631     {0xffff55ff, 0x6afa5afa},
1632     {0xaaffffaa, 0xfafafafa},
1633     {0xaa5555aa, 0x5a5a5a5a},
1634     {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */
1635     {0xaa5555aa, 0xaaaaaaaa},
1636     {0xffffffff, 0x55555555},
1637     {0xffffffff, 0x5a5a5a5a},
1638     {0xffffffff, 0x5a5a5a5a},
1639     {0xffffffff, 0x5a5a5aaa}, /* case-25 */
1640     {0x55555555, 0x5a5a5a5a},
1641     {0x55555555, 0xaaaaaaaa},
1642     {0x66555555, 0x6a5a6a5a},
1643     {0x66556655, 0x66556655},
1644     {0x66556aaa, 0x6a5a6aaa}, /* case-30 */
1645     {0xffffffff, 0x5aaa5aaa},
1646     {0x56555555, 0x5a5a5aaa}
1647 };
1648 
1649 /* Non-Shared-Antenna Coex Table */
1650 static const struct coex_table_para table_nsant_8821c[] = {
1651     {0xffffffff, 0xffffffff}, /* case-100 */
1652     {0xffff55ff, 0xfafafafa},
1653     {0x66555555, 0x66555555},
1654     {0xaaaaaaaa, 0xaaaaaaaa},
1655     {0x5a5a5a5a, 0x5a5a5a5a},
1656     {0xffffffff, 0xffffffff}, /* case-105 */
1657     {0x5afa5afa, 0x5afa5afa},
1658     {0x55555555, 0xfafafafa},
1659     {0x66555555, 0xfafafafa},
1660     {0x66555555, 0x5a5a5a5a},
1661     {0x66555555, 0x6a5a5a5a}, /* case-110 */
1662     {0x66555555, 0xaaaaaaaa},
1663     {0xffff55ff, 0xfafafafa},
1664     {0xffff55ff, 0x5afa5afa},
1665     {0xffff55ff, 0xaaaaaaaa},
1666     {0xffff55ff, 0xffff55ff}, /* case-115 */
1667     {0xaaffffaa, 0x5afa5afa},
1668     {0xaaffffaa, 0xaaaaaaaa},
1669     {0xffffffff, 0xfafafafa},
1670     {0xffff55ff, 0xfafafafa},
1671     {0xffffffff, 0xaaaaaaaa}, /* case-120 */
1672     {0xffff55ff, 0x5afa5afa},
1673     {0xffff55ff, 0x5afa5afa},
1674     {0x55ff55ff, 0x55ff55ff}
1675 };
1676 
1677 /* Shared-Antenna TDMA */
1678 static const struct coex_tdma_para tdma_sant_8821c[] = {
1679     { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */
1680     { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-1 */
1681     { {0x61, 0x3a, 0x03, 0x11, 0x11} },
1682     { {0x61, 0x35, 0x03, 0x11, 0x11} },
1683     { {0x61, 0x20, 0x03, 0x11, 0x11} },
1684     { {0x61, 0x3a, 0x03, 0x11, 0x11} }, /* case-5 */
1685     { {0x61, 0x45, 0x03, 0x11, 0x10} },
1686     { {0x61, 0x35, 0x03, 0x11, 0x10} },
1687     { {0x61, 0x30, 0x03, 0x11, 0x10} },
1688     { {0x61, 0x20, 0x03, 0x11, 0x10} },
1689     { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */
1690     { {0x61, 0x08, 0x03, 0x11, 0x15} },
1691     { {0x61, 0x08, 0x03, 0x10, 0x14} },
1692     { {0x51, 0x08, 0x03, 0x10, 0x54} },
1693     { {0x51, 0x08, 0x03, 0x10, 0x55} },
1694     { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */
1695     { {0x51, 0x45, 0x03, 0x10, 0x50} },
1696     { {0x51, 0x3a, 0x03, 0x11, 0x50} },
1697     { {0x51, 0x30, 0x03, 0x10, 0x50} },
1698     { {0x51, 0x21, 0x03, 0x10, 0x50} },
1699     { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */
1700     { {0x51, 0x4a, 0x03, 0x10, 0x50} },
1701     { {0x51, 0x08, 0x03, 0x30, 0x54} },
1702     { {0x55, 0x08, 0x03, 0x10, 0x54} },
1703     { {0x65, 0x10, 0x03, 0x11, 0x10} },
1704     { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */
1705     { {0x51, 0x21, 0x03, 0x10, 0x50} },
1706     { {0x61, 0x08, 0x03, 0x11, 0x11} }
1707 };
1708 
1709 /* Non-Shared-Antenna TDMA */
1710 static const struct coex_tdma_para tdma_nsant_8821c[] = {
1711     { {0x00, 0x00, 0x00, 0x40, 0x00} }, /* case-100 */
1712     { {0x61, 0x45, 0x03, 0x11, 0x11} },
1713     { {0x61, 0x25, 0x03, 0x11, 0x11} },
1714     { {0x61, 0x35, 0x03, 0x11, 0x11} },
1715     { {0x61, 0x20, 0x03, 0x11, 0x11} },
1716     { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */
1717     { {0x61, 0x45, 0x03, 0x11, 0x10} },
1718     { {0x61, 0x30, 0x03, 0x11, 0x10} },
1719     { {0x61, 0x30, 0x03, 0x11, 0x10} },
1720     { {0x61, 0x20, 0x03, 0x11, 0x10} },
1721     { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */
1722     { {0x61, 0x10, 0x03, 0x11, 0x11} },
1723     { {0x61, 0x08, 0x03, 0x10, 0x14} },
1724     { {0x51, 0x08, 0x03, 0x10, 0x54} },
1725     { {0x51, 0x08, 0x03, 0x10, 0x55} },
1726     { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */
1727     { {0x51, 0x45, 0x03, 0x10, 0x50} },
1728     { {0x51, 0x3a, 0x03, 0x10, 0x50} },
1729     { {0x51, 0x30, 0x03, 0x10, 0x50} },
1730     { {0x51, 0x21, 0x03, 0x10, 0x50} },
1731     { {0x51, 0x21, 0x03, 0x10, 0x50} }, /* case-120 */
1732     { {0x51, 0x10, 0x03, 0x10, 0x50} }
1733 };
1734 
1735 static const struct coex_5g_afh_map afh_5g_8821c[] = { {0, 0, 0} };
1736 
1737 /* wl_tx_dec_power, bt_tx_dec_power, wl_rx_gain, bt_rx_lna_constrain */
1738 static const struct coex_rf_para rf_para_tx_8821c[] = {
1739     {0, 0, false, 7},  /* for normal */
1740     {0, 20, false, 7}, /* for WL-CPT */
1741     {8, 17, true, 4},
1742     {7, 18, true, 4},
1743     {6, 19, true, 4},
1744     {5, 20, true, 4}
1745 };
1746 
1747 static const struct coex_rf_para rf_para_rx_8821c[] = {
1748     {0, 0, false, 7},  /* for normal */
1749     {0, 20, false, 7}, /* for WL-CPT */
1750     {3, 24, true, 5},
1751     {2, 26, true, 5},
1752     {1, 27, true, 5},
1753     {0, 28, true, 5}
1754 };
1755 
1756 static_assert(ARRAY_SIZE(rf_para_tx_8821c) == ARRAY_SIZE(rf_para_rx_8821c));
1757 
1758 static const u8 rtw8821c_pwrtrk_5gb_n[][RTW_PWR_TRK_TBL_SZ] = {
1759     {0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 9, 10, 10,
1760      11, 11, 12, 12, 12, 12, 12},
1761     {0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11,
1762      11, 12, 12, 12, 12, 12, 12, 12},
1763     {0, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11,
1764      11, 12, 12, 12, 12, 12, 12},
1765 };
1766 
1767 static const u8 rtw8821c_pwrtrk_5gb_p[][RTW_PWR_TRK_TBL_SZ] = {
1768     {0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11,
1769      12, 12, 12, 12, 12, 12, 12},
1770     {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11,
1771      12, 12, 12, 12, 12, 12, 12, 12},
1772     {0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11,
1773      11, 12, 12, 12, 12, 12, 12, 12},
1774 };
1775 
1776 static const u8 rtw8821c_pwrtrk_5ga_n[][RTW_PWR_TRK_TBL_SZ] = {
1777     {0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 9, 10, 10,
1778      11, 11, 12, 12, 12, 12, 12},
1779     {0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11,
1780      11, 12, 12, 12, 12, 12, 12, 12},
1781     {0, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11,
1782      11, 12, 12, 12, 12, 12, 12},
1783 };
1784 
1785 static const u8 rtw8821c_pwrtrk_5ga_p[][RTW_PWR_TRK_TBL_SZ] = {
1786     {0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11,
1787      12, 12, 12, 12, 12, 12, 12},
1788     {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11,
1789      12, 12, 12, 12, 12, 12, 12, 12},
1790     {0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11,
1791      11, 12, 12, 12, 12, 12, 12, 12},
1792 };
1793 
1794 static const u8 rtw8821c_pwrtrk_2gb_n[] = {
1795     0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4,
1796     4, 4, 5, 5, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9
1797 };
1798 
1799 static const u8 rtw8821c_pwrtrk_2gb_p[] = {
1800     0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5,
1801     5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9
1802 };
1803 
1804 static const u8 rtw8821c_pwrtrk_2ga_n[] = {
1805     0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4,
1806     4, 4, 5, 5, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9
1807 };
1808 
1809 static const u8 rtw8821c_pwrtrk_2ga_p[] = {
1810     0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5,
1811     5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9
1812 };
1813 
1814 static const u8 rtw8821c_pwrtrk_2g_cck_b_n[] = {
1815     0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4,
1816     4, 5, 5, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9
1817 };
1818 
1819 static const u8 rtw8821c_pwrtrk_2g_cck_b_p[] = {
1820     0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5,
1821     5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9
1822 };
1823 
1824 static const u8 rtw8821c_pwrtrk_2g_cck_a_n[] = {
1825     0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4,
1826     4, 5, 5, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9
1827 };
1828 
1829 static const u8 rtw8821c_pwrtrk_2g_cck_a_p[] = {
1830     0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5,
1831     5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9
1832 };
1833 
1834 static const struct rtw_pwr_track_tbl rtw8821c_rtw_pwr_track_tbl = {
1835     .pwrtrk_5gb_n[0] = rtw8821c_pwrtrk_5gb_n[0],
1836     .pwrtrk_5gb_n[1] = rtw8821c_pwrtrk_5gb_n[1],
1837     .pwrtrk_5gb_n[2] = rtw8821c_pwrtrk_5gb_n[2],
1838     .pwrtrk_5gb_p[0] = rtw8821c_pwrtrk_5gb_p[0],
1839     .pwrtrk_5gb_p[1] = rtw8821c_pwrtrk_5gb_p[1],
1840     .pwrtrk_5gb_p[2] = rtw8821c_pwrtrk_5gb_p[2],
1841     .pwrtrk_5ga_n[0] = rtw8821c_pwrtrk_5ga_n[0],
1842     .pwrtrk_5ga_n[1] = rtw8821c_pwrtrk_5ga_n[1],
1843     .pwrtrk_5ga_n[2] = rtw8821c_pwrtrk_5ga_n[2],
1844     .pwrtrk_5ga_p[0] = rtw8821c_pwrtrk_5ga_p[0],
1845     .pwrtrk_5ga_p[1] = rtw8821c_pwrtrk_5ga_p[1],
1846     .pwrtrk_5ga_p[2] = rtw8821c_pwrtrk_5ga_p[2],
1847     .pwrtrk_2gb_n = rtw8821c_pwrtrk_2gb_n,
1848     .pwrtrk_2gb_p = rtw8821c_pwrtrk_2gb_p,
1849     .pwrtrk_2ga_n = rtw8821c_pwrtrk_2ga_n,
1850     .pwrtrk_2ga_p = rtw8821c_pwrtrk_2ga_p,
1851     .pwrtrk_2g_cckb_n = rtw8821c_pwrtrk_2g_cck_b_n,
1852     .pwrtrk_2g_cckb_p = rtw8821c_pwrtrk_2g_cck_b_p,
1853     .pwrtrk_2g_ccka_n = rtw8821c_pwrtrk_2g_cck_a_n,
1854     .pwrtrk_2g_ccka_p = rtw8821c_pwrtrk_2g_cck_a_p,
1855 };
1856 
1857 static const struct rtw_reg_domain coex_info_hw_regs_8821c[] = {
1858     {0xCB0, MASKDWORD, RTW_REG_DOMAIN_MAC32},
1859     {0xCB4, MASKDWORD, RTW_REG_DOMAIN_MAC32},
1860     {0xCBA, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
1861     {0, 0, RTW_REG_DOMAIN_NL},
1862     {0x430, MASKDWORD, RTW_REG_DOMAIN_MAC32},
1863     {0x434, MASKDWORD, RTW_REG_DOMAIN_MAC32},
1864     {0x42a, MASKLWORD, RTW_REG_DOMAIN_MAC16},
1865     {0x426, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
1866     {0x45e, BIT(3), RTW_REG_DOMAIN_MAC8},
1867     {0x454, MASKLWORD, RTW_REG_DOMAIN_MAC16},
1868     {0, 0, RTW_REG_DOMAIN_NL},
1869     {0x4c, BIT(24) | BIT(23), RTW_REG_DOMAIN_MAC32},
1870     {0x64, BIT(0), RTW_REG_DOMAIN_MAC8},
1871     {0x4c6, BIT(4), RTW_REG_DOMAIN_MAC8},
1872     {0x40, BIT(5), RTW_REG_DOMAIN_MAC8},
1873     {0x1, RFREG_MASK, RTW_REG_DOMAIN_RF_A},
1874     {0, 0, RTW_REG_DOMAIN_NL},
1875     {0x550, MASKDWORD, RTW_REG_DOMAIN_MAC32},
1876     {0x522, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
1877     {0x953, BIT(1), RTW_REG_DOMAIN_MAC8},
1878     {0xc50,  MASKBYTE0, RTW_REG_DOMAIN_MAC8},
1879     {0x60A, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
1880 };
1881 
1882 const struct rtw_chip_info rtw8821c_hw_spec = {
1883     .ops = &rtw8821c_ops,
1884     .id = RTW_CHIP_TYPE_8821C,
1885     .fw_name = "rtw88/rtw8821c_fw.bin",
1886     .wlan_cpu = RTW_WCPU_11AC,
1887     .tx_pkt_desc_sz = 48,
1888     .tx_buf_desc_sz = 16,
1889     .rx_pkt_desc_sz = 24,
1890     .rx_buf_desc_sz = 8,
1891     .phy_efuse_size = 512,
1892     .log_efuse_size = 512,
1893     .ptct_efuse_size = 96,
1894     .txff_size = 65536,
1895     .rxff_size = 16384,
1896     .txgi_factor = 1,
1897     .is_pwr_by_rate_dec = true,
1898     .max_power_index = 0x3f,
1899     .csi_buf_pg_num = 0,
1900     .band = RTW_BAND_2G | RTW_BAND_5G,
1901     .page_size = 128,
1902     .dig_min = 0x1c,
1903     .ht_supported = true,
1904     .vht_supported = true,
1905     .lps_deep_mode_supported = BIT(LPS_DEEP_MODE_LCLK),
1906     .sys_func_en = 0xD8,
1907     .pwr_on_seq = card_enable_flow_8821c,
1908     .pwr_off_seq = card_disable_flow_8821c,
1909     .page_table = page_table_8821c,
1910     .rqpn_table = rqpn_table_8821c,
1911     .prioq_addrs = &prioq_addrs_8821c,
1912     .intf_table = &phy_para_table_8821c,
1913     .dig = rtw8821c_dig,
1914     .rf_base_addr = {0x2800, 0x2c00},
1915     .rf_sipi_addr = {0xc90, 0xe90},
1916     .ltecoex_addr = &rtw8821c_ltecoex_addr,
1917     .mac_tbl = &rtw8821c_mac_tbl,
1918     .agc_tbl = &rtw8821c_agc_tbl,
1919     .bb_tbl = &rtw8821c_bb_tbl,
1920     .rf_tbl = {&rtw8821c_rf_a_tbl},
1921     .rfe_defs = rtw8821c_rfe_defs,
1922     .rfe_defs_size = ARRAY_SIZE(rtw8821c_rfe_defs),
1923     .rx_ldpc = false,
1924     .pwr_track_tbl = &rtw8821c_rtw_pwr_track_tbl,
1925     .iqk_threshold = 8,
1926     .bfer_su_max_num = 2,
1927     .bfer_mu_max_num = 1,
1928     .ampdu_density = IEEE80211_HT_MPDU_DENSITY_2,
1929 
1930     .coex_para_ver = 0x19092746,
1931     .bt_desired_ver = 0x46,
1932     .scbd_support = true,
1933     .new_scbd10_def = false,
1934     .ble_hid_profile_support = false,
1935     .wl_mimo_ps_support = false,
1936     .pstdma_type = COEX_PSTDMA_FORCE_LPSOFF,
1937     .bt_rssi_type = COEX_BTRSSI_RATIO,
1938     .ant_isolation = 15,
1939     .rssi_tolerance = 2,
1940     .wl_rssi_step = wl_rssi_step_8821c,
1941     .bt_rssi_step = bt_rssi_step_8821c,
1942     .table_sant_num = ARRAY_SIZE(table_sant_8821c),
1943     .table_sant = table_sant_8821c,
1944     .table_nsant_num = ARRAY_SIZE(table_nsant_8821c),
1945     .table_nsant = table_nsant_8821c,
1946     .tdma_sant_num = ARRAY_SIZE(tdma_sant_8821c),
1947     .tdma_sant = tdma_sant_8821c,
1948     .tdma_nsant_num = ARRAY_SIZE(tdma_nsant_8821c),
1949     .tdma_nsant = tdma_nsant_8821c,
1950     .wl_rf_para_num = ARRAY_SIZE(rf_para_tx_8821c),
1951     .wl_rf_para_tx = rf_para_tx_8821c,
1952     .wl_rf_para_rx = rf_para_rx_8821c,
1953     .bt_afh_span_bw20 = 0x24,
1954     .bt_afh_span_bw40 = 0x36,
1955     .afh_5g_num = ARRAY_SIZE(afh_5g_8821c),
1956     .afh_5g = afh_5g_8821c,
1957 
1958     .coex_info_hw_regs_num = ARRAY_SIZE(coex_info_hw_regs_8821c),
1959     .coex_info_hw_regs = coex_info_hw_regs_8821c,
1960 };
1961 EXPORT_SYMBOL(rtw8821c_hw_spec);
1962 
1963 MODULE_FIRMWARE("rtw88/rtw8821c_fw.bin");
1964 
1965 MODULE_AUTHOR("Realtek Corporation");
1966 MODULE_DESCRIPTION("Realtek 802.11ac wireless 8821c driver");
1967 MODULE_LICENSE("Dual BSD/GPL");
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