realtek/rtw88/rtw8723d.h

0001 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
0002 /* Copyright(c) 2018-2019  Realtek Corporation
0003  */
0004
0005 #ifndef __RTW8723D_H__
0006 #define __RTW8723D_H__
0007
0008 enum rtw8723d_path {
0009     PATH_S1,
0010     PATH_S0,
0011     PATH_NR,
0012 };
0013
0014 enum rtw8723d_iqk_round {
0015     IQK_ROUND_0,
0016     IQK_ROUND_1,
0017     IQK_ROUND_2,
0018     IQK_ROUND_HYBRID,
0019     IQK_ROUND_SIZE,
0020     IQK_ROUND_INVALID = 0xff,
0021 };
0022
0023 enum rtw8723d_iqk_result {
0024     IQK_S1_TX_X,
0025     IQK_S1_TX_Y,
0026     IQK_S1_RX_X,
0027     IQK_S1_RX_Y,
0028     IQK_S0_TX_X,
0029     IQK_S0_TX_Y,
0030     IQK_S0_RX_X,
0031     IQK_S0_RX_Y,
0032     IQK_NR,
0033     IQK_SX_NR = IQK_NR / PATH_NR,
0034 };
0035
0036 struct rtw8723de_efuse {
0037     u8 mac_addr[ETH_ALEN];      /* 0xd0 */
0038     u8 vender_id[2];
0039     u8 device_id[2];
0040     u8 sub_vender_id[2];
0041     u8 sub_device_id[2];
0042 };
0043
0044 struct rtw8723d_efuse {
0045     __le16 rtl_id;
0046     u8 rsvd[2];
0047     u8 afe;
0048     u8 rsvd1[11];
0049
0050     /* power index for four RF paths */
0051     struct rtw_txpwr_idx txpwr_idx_table[4];
0052
0053     u8 channel_plan;        /* 0xb8 */
0054     u8 xtal_k;
0055     u8 thermal_meter;
0056     u8 iqk_lck;
0057     u8 pa_type;         /* 0xbc */
0058     u8 lna_type_2g[2];      /* 0xbd */
0059     u8 lna_type_5g[2];
0060     u8 rf_board_option;
0061     u8 rf_feature_option;
0062     u8 rf_bt_setting;
0063     u8 eeprom_version;
0064     u8 eeprom_customer_id;
0065     u8 tx_bb_swing_setting_2g;
0066     u8 res_c7;
0067     u8 tx_pwr_calibrate_rate;
0068     u8 rf_antenna_option;       /* 0xc9 */
0069     u8 rfe_option;
0070     u8 country_code[2];
0071     u8 res[3];
0072     struct rtw8723de_efuse e;
0073 };
0074
0075 extern const struct rtw_chip_info rtw8723d_hw_spec;
0076
0077 /* phy status page0 */
0078 #define GET_PHY_STAT_P0_PWDB(phy_stat)                                         \
0079     le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
0080
0081 /* phy status page1 */
0082 #define GET_PHY_STAT_P1_PWDB_A(phy_stat)                                       \
0083     le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
0084 #define GET_PHY_STAT_P1_PWDB_B(phy_stat)                                       \
0085     le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(23, 16))
0086 #define GET_PHY_STAT_P1_RF_MODE(phy_stat)                                      \
0087     le32_get_bits(*((__le32 *)(phy_stat) + 0x03), GENMASK(29, 28))
0088 #define GET_PHY_STAT_P1_L_RXSC(phy_stat)                                       \
0089     le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(11, 8))
0090 #define GET_PHY_STAT_P1_HT_RXSC(phy_stat)                                      \
0091     le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(15, 12))
0092 #define GET_PHY_STAT_P1_RXEVM_A(phy_stat)                                      \
0093     le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(7, 0))
0094 #define GET_PHY_STAT_P1_CFO_TAIL_A(phy_stat)                                   \
0095     le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(7, 0))
0096 #define GET_PHY_STAT_P1_RXSNR_A(phy_stat)                                      \
0097     le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(7, 0))
0098
0099 static inline s32 iqkxy_to_s32(s32 val)
0100 {
0101     /* val is Q10.8 */
0102     return sign_extend32(val, 9);
0103 }
0104
0105 static inline s32 iqk_mult(s32 x, s32 y, s32 *ext)
0106 {
0107     /* x, y and return value are Q10.8 */
0108     s32 t;
0109
0110     t = x * y;
0111     if (ext)
0112         *ext = (t >> 7) & 0x1;  /* Q.16 --> Q.9; get LSB of Q.9 */
0113
0114     return (t >> 8);    /* Q.16 --> Q.8 */
0115 }
0116
0117 #define OFDM_SWING_A(swing)     FIELD_GET(GENMASK(9, 0), swing)
0118 #define OFDM_SWING_B(swing)     FIELD_GET(GENMASK(15, 10), swing)
0119 #define OFDM_SWING_C(swing)     FIELD_GET(GENMASK(21, 16), swing)
0120 #define OFDM_SWING_D(swing)     FIELD_GET(GENMASK(31, 22), swing)
0121 #define RTW_DEF_OFDM_SWING_INDEX    28
0122 #define RTW_DEF_CCK_SWING_INDEX     28
0123
0124 #define MAX_TOLERANCE   5
0125 #define IQK_TX_X_ERR    0x142
0126 #define IQK_TX_Y_ERR    0x42
0127 #define IQK_RX_X_UPPER  0x11a
0128 #define IQK_RX_X_LOWER  0xe6
0129 #define IQK_RX_Y_LMT    0x1a
0130 #define IQK_TX_OK   BIT(0)
0131 #define IQK_RX_OK   BIT(1)
0132 #define PATH_IQK_RETRY  2
0133
0134 #define SPUR_THRES      0x16
0135 #define CCK_DFIR_NR     3
0136 #define DIS_3WIRE       0xccf000c0
0137 #define EN_3WIRE        0xccc000c0
0138 #define START_PSD       0x400000
0139 #define FREQ_CH13       0xfccd
0140 #define FREQ_CH14       0xff9a
0141 #define RFCFGCH_CHANNEL_MASK    GENMASK(7, 0)
0142 #define RFCFGCH_BW_MASK     (BIT(11) | BIT(10))
0143 #define RFCFGCH_BW_20M      (BIT(11) | BIT(10))
0144 #define RFCFGCH_BW_40M      BIT(10)
0145 #define BIT_MASK_RFMOD      BIT(0)
0146 #define BIT_LCK         BIT(15)
0147
0148 #define REG_GPIO_INTM       0x0048
0149 #define REG_BTG_SEL     0x0067
0150 #define BIT_MASK_BTG_WL     BIT(7)
0151 #define REG_LTECOEX_PATH_CONTROL    0x0070
0152 #define REG_LTECOEX_CTRL    0x07c0
0153 #define REG_LTECOEX_WRITE_DATA  0x07c4
0154 #define REG_LTECOEX_READ_DATA   0x07c8
0155 #define REG_PSDFN       0x0808
0156 #define REG_BB_PWR_SAV1_11N 0x0874
0157 #define REG_ANA_PARAM1      0x0880
0158 #define REG_ANALOG_P4       0x088c
0159 #define REG_PSDRPT      0x08b4
0160 #define REG_FPGA1_RFMOD     0x0900
0161 #define REG_BB_SEL_BTG      0x0948
0162 #define REG_BBRX_DFIR       0x0954
0163 #define BIT_MASK_RXBB_DFIR  GENMASK(27, 24)
0164 #define BIT_RXBB_DFIR_EN    BIT(19)
0165 #define REG_CCK0_SYS        0x0a00
0166 #define BIT_CCK_SIDE_BAND   BIT(4)
0167 #define REG_CCK_ANT_SEL_11N 0x0a04
0168 #define REG_PWRTH       0x0a08
0169 #define REG_CCK_FA_RST_11N  0x0a2c
0170 #define BIT_MASK_CCK_CNT_KEEP   BIT(12)
0171 #define BIT_MASK_CCK_CNT_EN BIT(13)
0172 #define BIT_MASK_CCK_CNT_KPEN   (BIT_MASK_CCK_CNT_KEEP | BIT_MASK_CCK_CNT_EN)
0173 #define BIT_MASK_CCK_FA_KEEP    BIT(14)
0174 #define BIT_MASK_CCK_FA_EN  BIT(15)
0175 #define BIT_MASK_CCK_FA_KPEN    (BIT_MASK_CCK_FA_KEEP | BIT_MASK_CCK_FA_EN)
0176 #define REG_CCK_FA_LSB_11N  0x0a5c
0177 #define REG_CCK_FA_MSB_11N  0x0a58
0178 #define REG_CCK_CCA_CNT_11N 0x0a60
0179 #define BIT_MASK_CCK_FA_MSB GENMASK(7, 0)
0180 #define BIT_MASK_CCK_FA_LSB GENMASK(15, 8)
0181 #define REG_PWRTH2      0x0aa8
0182 #define REG_CSRATIO     0x0aaa
0183 #define REG_OFDM_FA_HOLDC_11N   0x0c00
0184 #define BIT_MASK_OFDM_FA_KEEP   BIT(31)
0185 #define REG_BB_RX_PATH_11N  0x0c04
0186 #define REG_TRMUX_11N       0x0c08
0187 #define REG_OFDM_FA_RSTC_11N    0x0c0c
0188 #define BIT_MASK_OFDM_FA_RST    BIT(31)
0189 #define REG_A_RXIQI     0x0c14
0190 #define BIT_MASK_RXIQ_S1_X  0x000003FF
0191 #define BIT_MASK_RXIQ_S1_Y1 0x0000FC00
0192 #define BIT_SET_RXIQ_S1_Y1(y)   ((y) & 0x3F)
0193 #define REG_OFDM0_RXDSP     0x0c40
0194 #define BIT_MASK_RXDSP      GENMASK(28, 24)
0195 #define BIT_EN_RXDSP        BIT(9)
0196 #define REG_OFDM_0_ECCA_THRESHOLD   0x0c4c
0197 #define BIT_MASK_OFDM0_EXT_A    BIT(31)
0198 #define BIT_MASK_OFDM0_EXT_C    BIT(29)
0199 #define BIT_MASK_OFDM0_EXTS (BIT(31) | BIT(29) | BIT(28))
0200 #define BIT_SET_OFDM0_EXTS(a, c, d) (((a) << 31) | ((c) << 29) | ((d) << 28))
0201 #define REG_OFDM0_XAAGC1    0x0c50
0202 #define REG_OFDM0_XBAGC1    0x0c58
0203 #define REG_AGCRSSI     0x0c78
0204 #define REG_OFDM_0_XA_TX_IQ_IMBALANCE   0x0c80
0205 #define BIT_MASK_TXIQ_ELM_A 0x03ff
0206 #define BIT_SET_TXIQ_ELM_ACD(a, c, d) (((d) << 22) | (((c) & 0x3F) << 16) |    \
0207                        ((a) & 0x03ff))
0208 #define BIT_MASK_TXIQ_ELM_C GENMASK(21, 16)
0209 #define BIT_SET_TXIQ_ELM_C2(c)  ((c) & 0x3F)
0210 #define BIT_MASK_TXIQ_ELM_D GENMASK(31, 22)
0211 #define REG_TXIQK_MATRIXA_LSB2_11N  0x0c94
0212 #define BIT_SET_TXIQ_ELM_C1(c)  (((c) & 0x000003C0) >> 6)
0213 #define REG_RXIQK_MATRIX_LSB_11N    0x0ca0
0214 #define BIT_MASK_RXIQ_S1_Y2 0xF0000000
0215 #define BIT_SET_RXIQ_S1_Y2(y)   (((y) >> 6) & 0xF)
0216 #define REG_TXIQ_AB_S0      0x0cd0
0217 #define BIT_MASK_TXIQ_A_S0  0x000007FE
0218 #define BIT_MASK_TXIQ_A_EXT_S0  BIT(0)
0219 #define BIT_MASK_TXIQ_B_S0  0x0007E000
0220 #define REG_TXIQ_CD_S0      0x0cd4
0221 #define BIT_MASK_TXIQ_C_S0  0x000007FE
0222 #define BIT_MASK_TXIQ_C_EXT_S0  BIT(0)
0223 #define BIT_MASK_TXIQ_D_S0  GENMASK(22, 13)
0224 #define BIT_MASK_TXIQ_D_EXT_S0  BIT(12)
0225 #define REG_RXIQ_AB_S0      0x0cd8
0226 #define BIT_MASK_RXIQ_X_S0  0x000003FF
0227 #define BIT_MASK_RXIQ_Y_S0  0x003FF000
0228 #define REG_OFDM_FA_TYPE1_11N   0x0cf0
0229 #define BIT_MASK_OFDM_FF_CNT    GENMASK(15, 0)
0230 #define BIT_MASK_OFDM_SF_CNT    GENMASK(31, 16)
0231 #define REG_OFDM_FA_RSTD_11N    0x0d00
0232 #define BIT_MASK_OFDM_FA_RST1   BIT(27)
0233 #define BIT_MASK_OFDM_FA_KEEP1  BIT(31)
0234 #define REG_CTX         0x0d03
0235 #define BIT_MASK_CTX_TYPE   GENMASK(6, 4)
0236 #define REG_OFDM1_CFOTRK    0x0d2c
0237 #define BIT_EN_CFOTRK       BIT(28)
0238 #define REG_OFDM1_CSI1      0x0d40
0239 #define REG_OFDM1_CSI2      0x0d44
0240 #define REG_OFDM1_CSI3      0x0d48
0241 #define REG_OFDM1_CSI4      0x0d4c
0242 #define REG_OFDM_FA_TYPE2_11N   0x0da0
0243 #define BIT_MASK_OFDM_CCA_CNT   GENMASK(15, 0)
0244 #define BIT_MASK_OFDM_PF_CNT    GENMASK(31, 16)
0245 #define REG_OFDM_FA_TYPE3_11N   0x0da4
0246 #define BIT_MASK_OFDM_RI_CNT    GENMASK(15, 0)
0247 #define BIT_MASK_OFDM_CRC_CNT   GENMASK(31, 16)
0248 #define REG_OFDM_FA_TYPE4_11N   0x0da8
0249 #define BIT_MASK_OFDM_MNS_CNT   GENMASK(15, 0)
0250 #define REG_FPGA0_IQK_11N   0x0e28
0251 #define BIT_MASK_IQK_MOD    0xffffff00
0252 #define EN_IQK          0x808000
0253 #define RST_IQK         0x000000
0254 #define REG_TXIQK_TONE_A_11N    0x0e30
0255 #define REG_RXIQK_TONE_A_11N    0x0e34
0256 #define REG_TXIQK_PI_A_11N  0x0e38
0257 #define REG_RXIQK_PI_A_11N  0x0e3c
0258 #define REG_TXIQK_11N       0x0e40
0259 #define BIT_SET_TXIQK_11N(x, y) (0x80007C00 | ((x) << 16) | (y))
0260 #define REG_RXIQK_11N       0x0e44
0261 #define REG_IQK_AGC_PTS_11N 0x0e48
0262 #define REG_IQK_AGC_RSP_11N 0x0e4c
0263 #define REG_TX_IQK_TONE_B   0x0e50
0264 #define REG_RX_IQK_TONE_B   0x0e54
0265 #define REG_IQK_RES_TX      0x0e94
0266 #define BIT_MASK_RES_TX     GENMASK(25, 16)
0267 #define REG_IQK_RES_TY      0x0e9c
0268 #define BIT_MASK_RES_TY     GENMASK(25, 16)
0269 #define REG_IQK_RES_RX      0x0ea4
0270 #define BIT_MASK_RES_RX     GENMASK(25, 16)
0271 #define REG_IQK_RES_RY      0x0eac
0272 #define BIT_IQK_TX_FAIL     BIT(28)
0273 #define BIT_IQK_RX_FAIL     BIT(27)
0274 #define BIT_IQK_DONE        BIT(26)
0275 #define BIT_MASK_RES_RY     GENMASK(25, 16)
0276 #define REG_PAGE_F_RST_11N      0x0f14
0277 #define BIT_MASK_F_RST_ALL      BIT(16)
0278 #define REG_IGI_C_11N           0x0f84
0279 #define REG_IGI_D_11N           0x0f88
0280 #define REG_HT_CRC32_CNT_11N        0x0f90
0281 #define BIT_MASK_HT_CRC_OK      GENMASK(15, 0)
0282 #define BIT_MASK_HT_CRC_ERR     GENMASK(31, 16)
0283 #define REG_OFDM_CRC32_CNT_11N      0x0f94
0284 #define BIT_MASK_OFDM_LCRC_OK       GENMASK(15, 0)
0285 #define BIT_MASK_OFDM_LCRC_ERR      GENMASK(31, 16)
0286 #define REG_HT_CRC32_CNT_11N_AGG    0x0fb8
0287
0288 #endif