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0005 #ifndef __RTW_PHY_H_
0006 #define __RTW_PHY_H_
0007
0008 #include "debug.h"
0009
0010 extern u8 rtw_cck_rates[];
0011 extern u8 rtw_ofdm_rates[];
0012 extern u8 rtw_ht_1s_rates[];
0013 extern u8 rtw_ht_2s_rates[];
0014 extern u8 rtw_vht_1s_rates[];
0015 extern u8 rtw_vht_2s_rates[];
0016 extern u8 *rtw_rate_section[];
0017 extern u8 rtw_rate_size[];
0018
0019 void rtw_phy_init(struct rtw_dev *rtwdev);
0020 void rtw_phy_dynamic_mechanism(struct rtw_dev *rtwdev);
0021 u8 rtw_phy_rf_power_2_rssi(s8 *rf_power, u8 path_num);
0022 u32 rtw_phy_read_rf(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
0023 u32 addr, u32 mask);
0024 u32 rtw_phy_read_rf_sipi(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
0025 u32 addr, u32 mask);
0026 bool rtw_phy_write_rf_reg_sipi(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
0027 u32 addr, u32 mask, u32 data);
0028 bool rtw_phy_write_rf_reg(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
0029 u32 addr, u32 mask, u32 data);
0030 bool rtw_phy_write_rf_reg_mix(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
0031 u32 addr, u32 mask, u32 data);
0032 void rtw_phy_setup_phy_cond(struct rtw_dev *rtwdev, u32 pkg);
0033 void rtw_parse_tbl_phy_cond(struct rtw_dev *rtwdev, const struct rtw_table *tbl);
0034 void rtw_parse_tbl_bb_pg(struct rtw_dev *rtwdev, const struct rtw_table *tbl);
0035 void rtw_parse_tbl_txpwr_lmt(struct rtw_dev *rtwdev, const struct rtw_table *tbl);
0036 void rtw_phy_cfg_mac(struct rtw_dev *rtwdev, const struct rtw_table *tbl,
0037 u32 addr, u32 data);
0038 void rtw_phy_cfg_agc(struct rtw_dev *rtwdev, const struct rtw_table *tbl,
0039 u32 addr, u32 data);
0040 void rtw_phy_cfg_bb(struct rtw_dev *rtwdev, const struct rtw_table *tbl,
0041 u32 addr, u32 data);
0042 void rtw_phy_cfg_rf(struct rtw_dev *rtwdev, const struct rtw_table *tbl,
0043 u32 addr, u32 data);
0044 void rtw_phy_init_tx_power(struct rtw_dev *rtwdev);
0045 void rtw_phy_load_tables(struct rtw_dev *rtwdev);
0046 u8 rtw_phy_get_tx_power_index(struct rtw_dev *rtwdev, u8 rf_path, u8 rate,
0047 enum rtw_bandwidth bw, u8 channel, u8 regd);
0048 void rtw_phy_set_tx_power_level(struct rtw_dev *rtwdev, u8 channel);
0049 void rtw_phy_tx_power_by_rate_config(struct rtw_hal *hal);
0050 void rtw_phy_tx_power_limit_config(struct rtw_hal *hal);
0051 void rtw_phy_pwrtrack_avg(struct rtw_dev *rtwdev, u8 thermal, u8 path);
0052 bool rtw_phy_pwrtrack_thermal_changed(struct rtw_dev *rtwdev, u8 thermal,
0053 u8 path);
0054 u8 rtw_phy_pwrtrack_get_delta(struct rtw_dev *rtwdev, u8 path);
0055 s8 rtw_phy_pwrtrack_get_pwridx(struct rtw_dev *rtwdev,
0056 struct rtw_swing_table *swing_table,
0057 u8 tbl_path, u8 therm_path, u8 delta);
0058 bool rtw_phy_pwrtrack_need_lck(struct rtw_dev *rtwdev);
0059 bool rtw_phy_pwrtrack_need_iqk(struct rtw_dev *rtwdev);
0060 void rtw_phy_config_swing_table(struct rtw_dev *rtwdev,
0061 struct rtw_swing_table *swing_table);
0062 void rtw_phy_set_edcca_th(struct rtw_dev *rtwdev, u8 l2h, u8 h2l);
0063 void rtw_phy_adaptivity_set_mode(struct rtw_dev *rtwdev);
0064 void rtw_phy_parsing_cfo(struct rtw_dev *rtwdev,
0065 struct rtw_rx_pkt_stat *pkt_stat);
0066 void rtw_phy_tx_path_diversity(struct rtw_dev *rtwdev);
0067
0068 struct rtw_txpwr_lmt_cfg_pair {
0069 u8 regd;
0070 u8 band;
0071 u8 bw;
0072 u8 rs;
0073 u8 ch;
0074 s8 txpwr_lmt;
0075 };
0076
0077 struct rtw_phy_pg_cfg_pair {
0078 u32 band;
0079 u32 rf_path;
0080 u32 tx_num;
0081 u32 addr;
0082 u32 bitmask;
0083 u32 data;
0084 };
0085
0086 #define RTW_DECL_TABLE_PHY_COND_CORE(name, cfg, path) \
0087 const struct rtw_table name ## _tbl = { \
0088 .data = name, \
0089 .size = ARRAY_SIZE(name), \
0090 .parse = rtw_parse_tbl_phy_cond, \
0091 .do_cfg = cfg, \
0092 .rf_path = path, \
0093 }
0094
0095 #define RTW_DECL_TABLE_PHY_COND(name, cfg) \
0096 RTW_DECL_TABLE_PHY_COND_CORE(name, cfg, 0)
0097
0098 #define RTW_DECL_TABLE_RF_RADIO(name, path) \
0099 RTW_DECL_TABLE_PHY_COND_CORE(name, rtw_phy_cfg_rf, RF_PATH_ ## path)
0100
0101 #define RTW_DECL_TABLE_BB_PG(name) \
0102 const struct rtw_table name ## _tbl = { \
0103 .data = name, \
0104 .size = ARRAY_SIZE(name), \
0105 .parse = rtw_parse_tbl_bb_pg, \
0106 }
0107
0108 #define RTW_DECL_TABLE_TXPWR_LMT(name) \
0109 const struct rtw_table name ## _tbl = { \
0110 .data = name, \
0111 .size = ARRAY_SIZE(name), \
0112 .parse = rtw_parse_tbl_txpwr_lmt, \
0113 }
0114
0115 static inline const struct rtw_rfe_def *rtw_get_rfe_def(struct rtw_dev *rtwdev)
0116 {
0117 struct rtw_chip_info *chip = rtwdev->chip;
0118 struct rtw_efuse *efuse = &rtwdev->efuse;
0119 const struct rtw_rfe_def *rfe_def = NULL;
0120
0121 if (chip->rfe_defs_size == 0)
0122 return NULL;
0123
0124 if (efuse->rfe_option < chip->rfe_defs_size)
0125 rfe_def = &chip->rfe_defs[efuse->rfe_option];
0126
0127 rtw_dbg(rtwdev, RTW_DBG_PHY, "use rfe_def[%d]\n", efuse->rfe_option);
0128 return rfe_def;
0129 }
0130
0131 static inline int rtw_check_supported_rfe(struct rtw_dev *rtwdev)
0132 {
0133 const struct rtw_rfe_def *rfe_def = rtw_get_rfe_def(rtwdev);
0134
0135 if (!rfe_def || !rfe_def->phy_pg_tbl || !rfe_def->txpwr_lmt_tbl) {
0136 rtw_err(rtwdev, "rfe %d isn't supported\n",
0137 rtwdev->efuse.rfe_option);
0138 return -ENODEV;
0139 }
0140
0141 return 0;
0142 }
0143
0144 void rtw_phy_dig_write(struct rtw_dev *rtwdev, u8 igi);
0145
0146 struct rtw_power_params {
0147 u8 pwr_base;
0148 s8 pwr_offset;
0149 s8 pwr_limit;
0150 s8 pwr_remnant;
0151 s8 pwr_sar;
0152 };
0153
0154 void
0155 rtw_get_tx_power_params(struct rtw_dev *rtwdev, u8 path,
0156 u8 rate, u8 bw, u8 ch, u8 regd,
0157 struct rtw_power_params *pwr_param);
0158
0159 enum rtw_phy_cck_pd_lv {
0160 CCK_PD_LV0,
0161 CCK_PD_LV1,
0162 CCK_PD_LV2,
0163 CCK_PD_LV3,
0164 CCK_PD_LV4,
0165 CCK_PD_LV_MAX,
0166 };
0167
0168 #define MASKBYTE0 0xff
0169 #define MASKBYTE1 0xff00
0170 #define MASKBYTE2 0xff0000
0171 #define MASKBYTE3 0xff000000
0172 #define MASKHWORD 0xffff0000
0173 #define MASKLWORD 0x0000ffff
0174 #define MASKDWORD 0xffffffff
0175 #define RFREG_MASK 0xfffff
0176
0177 #define MASK7BITS 0x7f
0178 #define MASK12BITS 0xfff
0179 #define MASKH4BITS 0xf0000000
0180 #define MASK20BITS 0xfffff
0181 #define MASK24BITS 0xffffff
0182
0183 #define MASKH3BYTES 0xffffff00
0184 #define MASKL3BYTES 0x00ffffff
0185 #define MASKBYTE2HIGHNIBBLE 0x00f00000
0186 #define MASKBYTE3LOWNIBBLE 0x0f000000
0187 #define MASKL3BYTES 0x00ffffff
0188
0189 #define CCK_FA_AVG_RESET 0xffffffff
0190
0191 #define LSSI_READ_ADDR_MASK 0x7f800000
0192 #define LSSI_READ_EDGE_MASK 0x80000000
0193 #define LSSI_READ_DATA_MASK 0xfffff
0194
0195 #define RRSR_RATE_ORDER_MAX 0xfffff
0196 #define RRSR_RATE_ORDER_CCK_LEN 4
0197
0198 #endif
