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0001 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
0002 /* Copyright(c) 2018-2019  Realtek Corporation
0003  */
0004 
0005 #ifndef __RTK_MAIN_H_
0006 #define __RTK_MAIN_H_
0007 
0008 #include <net/mac80211.h>
0009 #include <linux/vmalloc.h>
0010 #include <linux/firmware.h>
0011 #include <linux/average.h>
0012 #include <linux/bitops.h>
0013 #include <linux/bitfield.h>
0014 #include <linux/iopoll.h>
0015 #include <linux/interrupt.h>
0016 #include <linux/workqueue.h>
0017 
0018 #include "util.h"
0019 
0020 #define RTW_MAX_MAC_ID_NUM      32
0021 #define RTW_MAX_SEC_CAM_NUM     32
0022 #define MAX_PG_CAM_BACKUP_NUM       8
0023 
0024 #define RTW_SCAN_MAX_SSIDS      4
0025 #define RTW_SCAN_MAX_IE_LEN     128
0026 
0027 #define RTW_MAX_PATTERN_NUM     12
0028 #define RTW_MAX_PATTERN_MASK_SIZE   16
0029 #define RTW_MAX_PATTERN_SIZE        128
0030 
0031 #define RTW_WATCH_DOG_DELAY_TIME    round_jiffies_relative(HZ * 2)
0032 
0033 #define RFREG_MASK          0xfffff
0034 #define INV_RF_DATA         0xffffffff
0035 #define TX_PAGE_SIZE_SHIFT      7
0036 
0037 #define RTW_CHANNEL_WIDTH_MAX       3
0038 #define RTW_RF_PATH_MAX         4
0039 #define HW_FEATURE_LEN          13
0040 
0041 #define RTW_TP_SHIFT            18 /* bytes/2s --> Mbps */
0042 
0043 extern bool rtw_bf_support;
0044 extern bool rtw_disable_lps_deep_mode;
0045 extern unsigned int rtw_debug_mask;
0046 extern bool rtw_edcca_enabled;
0047 extern const struct ieee80211_ops rtw_ops;
0048 
0049 #define RTW_MAX_CHANNEL_NUM_2G 14
0050 #define RTW_MAX_CHANNEL_NUM_5G 49
0051 
0052 struct rtw_dev;
0053 
0054 enum rtw_hci_type {
0055     RTW_HCI_TYPE_PCIE,
0056     RTW_HCI_TYPE_USB,
0057     RTW_HCI_TYPE_SDIO,
0058 
0059     RTW_HCI_TYPE_UNDEFINE,
0060 };
0061 
0062 struct rtw_hci {
0063     struct rtw_hci_ops *ops;
0064     enum rtw_hci_type type;
0065 
0066     u32 rpwm_addr;
0067     u32 cpwm_addr;
0068 
0069     u8 bulkout_num;
0070 };
0071 
0072 #define IS_CH_5G_BAND_1(channel) ((channel) >= 36 && (channel <= 48))
0073 #define IS_CH_5G_BAND_2(channel) ((channel) >= 52 && (channel <= 64))
0074 #define IS_CH_5G_BAND_3(channel) ((channel) >= 100 && (channel <= 144))
0075 #define IS_CH_5G_BAND_4(channel) ((channel) >= 149 && (channel <= 177))
0076 
0077 #define IS_CH_5G_BAND_MID(channel) \
0078     (IS_CH_5G_BAND_2(channel) || IS_CH_5G_BAND_3(channel))
0079 
0080 #define IS_CH_2G_BAND(channel) ((channel) <= 14)
0081 #define IS_CH_5G_BAND(channel) \
0082     (IS_CH_5G_BAND_1(channel) || IS_CH_5G_BAND_2(channel) || \
0083      IS_CH_5G_BAND_3(channel) || IS_CH_5G_BAND_4(channel))
0084 
0085 enum rtw_supported_band {
0086     RTW_BAND_2G = BIT(NL80211_BAND_2GHZ),
0087     RTW_BAND_5G = BIT(NL80211_BAND_5GHZ),
0088     RTW_BAND_60G = BIT(NL80211_BAND_60GHZ),
0089 };
0090 
0091 /* now, support upto 80M bw */
0092 #define RTW_MAX_CHANNEL_WIDTH RTW_CHANNEL_WIDTH_80
0093 
0094 enum rtw_bandwidth {
0095     RTW_CHANNEL_WIDTH_20    = 0,
0096     RTW_CHANNEL_WIDTH_40    = 1,
0097     RTW_CHANNEL_WIDTH_80    = 2,
0098     RTW_CHANNEL_WIDTH_160   = 3,
0099     RTW_CHANNEL_WIDTH_80_80 = 4,
0100     RTW_CHANNEL_WIDTH_5 = 5,
0101     RTW_CHANNEL_WIDTH_10    = 6,
0102 };
0103 
0104 enum rtw_sc_offset {
0105     RTW_SC_DONT_CARE    = 0,
0106     RTW_SC_20_UPPER     = 1,
0107     RTW_SC_20_LOWER     = 2,
0108     RTW_SC_20_UPMOST    = 3,
0109     RTW_SC_20_LOWEST    = 4,
0110     RTW_SC_40_UPPER     = 9,
0111     RTW_SC_40_LOWER     = 10,
0112 };
0113 
0114 enum rtw_net_type {
0115     RTW_NET_NO_LINK     = 0,
0116     RTW_NET_AD_HOC      = 1,
0117     RTW_NET_MGD_LINKED  = 2,
0118     RTW_NET_AP_MODE     = 3,
0119 };
0120 
0121 enum rtw_rf_type {
0122     RF_1T1R         = 0,
0123     RF_1T2R         = 1,
0124     RF_2T2R         = 2,
0125     RF_2T3R         = 3,
0126     RF_2T4R         = 4,
0127     RF_3T3R         = 5,
0128     RF_3T4R         = 6,
0129     RF_4T4R         = 7,
0130     RF_TYPE_MAX,
0131 };
0132 
0133 enum rtw_rf_path {
0134     RF_PATH_A = 0,
0135     RF_PATH_B = 1,
0136     RF_PATH_C = 2,
0137     RF_PATH_D = 3,
0138 };
0139 
0140 enum rtw_bb_path {
0141     BB_PATH_A = BIT(0),
0142     BB_PATH_B = BIT(1),
0143     BB_PATH_C = BIT(2),
0144     BB_PATH_D = BIT(3),
0145 
0146     BB_PATH_AB = (BB_PATH_A | BB_PATH_B),
0147     BB_PATH_AC = (BB_PATH_A | BB_PATH_C),
0148     BB_PATH_AD = (BB_PATH_A | BB_PATH_D),
0149     BB_PATH_BC = (BB_PATH_B | BB_PATH_C),
0150     BB_PATH_BD = (BB_PATH_B | BB_PATH_D),
0151     BB_PATH_CD = (BB_PATH_C | BB_PATH_D),
0152 
0153     BB_PATH_ABC = (BB_PATH_A | BB_PATH_B | BB_PATH_C),
0154     BB_PATH_ABD = (BB_PATH_A | BB_PATH_B | BB_PATH_D),
0155     BB_PATH_ACD = (BB_PATH_A | BB_PATH_C | BB_PATH_D),
0156     BB_PATH_BCD = (BB_PATH_B | BB_PATH_C | BB_PATH_D),
0157 
0158     BB_PATH_ABCD = (BB_PATH_A | BB_PATH_B | BB_PATH_C | BB_PATH_D),
0159 };
0160 
0161 enum rtw_rate_section {
0162     RTW_RATE_SECTION_CCK = 0,
0163     RTW_RATE_SECTION_OFDM,
0164     RTW_RATE_SECTION_HT_1S,
0165     RTW_RATE_SECTION_HT_2S,
0166     RTW_RATE_SECTION_VHT_1S,
0167     RTW_RATE_SECTION_VHT_2S,
0168 
0169     /* keep last */
0170     RTW_RATE_SECTION_MAX,
0171 };
0172 
0173 enum rtw_wireless_set {
0174     WIRELESS_CCK    = 0x00000001,
0175     WIRELESS_OFDM   = 0x00000002,
0176     WIRELESS_HT = 0x00000004,
0177     WIRELESS_VHT    = 0x00000008,
0178 };
0179 
0180 #define HT_STBC_EN  BIT(0)
0181 #define VHT_STBC_EN BIT(1)
0182 #define HT_LDPC_EN  BIT(0)
0183 #define VHT_LDPC_EN BIT(1)
0184 
0185 enum rtw_chip_type {
0186     RTW_CHIP_TYPE_8822B,
0187     RTW_CHIP_TYPE_8822C,
0188     RTW_CHIP_TYPE_8723D,
0189     RTW_CHIP_TYPE_8821C,
0190 };
0191 
0192 enum rtw_tx_queue_type {
0193     /* the order of AC queues matters */
0194     RTW_TX_QUEUE_BK = 0x0,
0195     RTW_TX_QUEUE_BE = 0x1,
0196     RTW_TX_QUEUE_VI = 0x2,
0197     RTW_TX_QUEUE_VO = 0x3,
0198 
0199     RTW_TX_QUEUE_BCN = 0x4,
0200     RTW_TX_QUEUE_MGMT = 0x5,
0201     RTW_TX_QUEUE_HI0 = 0x6,
0202     RTW_TX_QUEUE_H2C = 0x7,
0203     /* keep it last */
0204     RTK_MAX_TX_QUEUE_NUM
0205 };
0206 
0207 enum rtw_rx_queue_type {
0208     RTW_RX_QUEUE_MPDU = 0x0,
0209     RTW_RX_QUEUE_C2H = 0x1,
0210     /* keep it last */
0211     RTK_MAX_RX_QUEUE_NUM
0212 };
0213 
0214 enum rtw_fw_type {
0215     RTW_NORMAL_FW = 0x0,
0216     RTW_WOWLAN_FW = 0x1,
0217 };
0218 
0219 enum rtw_rate_index {
0220     RTW_RATEID_BGN_40M_2SS  = 0,
0221     RTW_RATEID_BGN_40M_1SS  = 1,
0222     RTW_RATEID_BGN_20M_2SS  = 2,
0223     RTW_RATEID_BGN_20M_1SS  = 3,
0224     RTW_RATEID_GN_N2SS  = 4,
0225     RTW_RATEID_GN_N1SS  = 5,
0226     RTW_RATEID_BG       = 6,
0227     RTW_RATEID_G        = 7,
0228     RTW_RATEID_B_20M    = 8,
0229     RTW_RATEID_ARFR0_AC_2SS = 9,
0230     RTW_RATEID_ARFR1_AC_1SS = 10,
0231     RTW_RATEID_ARFR2_AC_2G_1SS = 11,
0232     RTW_RATEID_ARFR3_AC_2G_2SS = 12,
0233     RTW_RATEID_ARFR4_AC_3SS = 13,
0234     RTW_RATEID_ARFR5_N_3SS  = 14,
0235     RTW_RATEID_ARFR7_N_4SS  = 15,
0236     RTW_RATEID_ARFR6_AC_4SS = 16
0237 };
0238 
0239 enum rtw_trx_desc_rate {
0240     DESC_RATE1M = 0x00,
0241     DESC_RATE2M = 0x01,
0242     DESC_RATE5_5M   = 0x02,
0243     DESC_RATE11M    = 0x03,
0244 
0245     DESC_RATE6M = 0x04,
0246     DESC_RATE9M = 0x05,
0247     DESC_RATE12M    = 0x06,
0248     DESC_RATE18M    = 0x07,
0249     DESC_RATE24M    = 0x08,
0250     DESC_RATE36M    = 0x09,
0251     DESC_RATE48M    = 0x0a,
0252     DESC_RATE54M    = 0x0b,
0253 
0254     DESC_RATEMCS0   = 0x0c,
0255     DESC_RATEMCS1   = 0x0d,
0256     DESC_RATEMCS2   = 0x0e,
0257     DESC_RATEMCS3   = 0x0f,
0258     DESC_RATEMCS4   = 0x10,
0259     DESC_RATEMCS5   = 0x11,
0260     DESC_RATEMCS6   = 0x12,
0261     DESC_RATEMCS7   = 0x13,
0262     DESC_RATEMCS8   = 0x14,
0263     DESC_RATEMCS9   = 0x15,
0264     DESC_RATEMCS10  = 0x16,
0265     DESC_RATEMCS11  = 0x17,
0266     DESC_RATEMCS12  = 0x18,
0267     DESC_RATEMCS13  = 0x19,
0268     DESC_RATEMCS14  = 0x1a,
0269     DESC_RATEMCS15  = 0x1b,
0270     DESC_RATEMCS16  = 0x1c,
0271     DESC_RATEMCS17  = 0x1d,
0272     DESC_RATEMCS18  = 0x1e,
0273     DESC_RATEMCS19  = 0x1f,
0274     DESC_RATEMCS20  = 0x20,
0275     DESC_RATEMCS21  = 0x21,
0276     DESC_RATEMCS22  = 0x22,
0277     DESC_RATEMCS23  = 0x23,
0278     DESC_RATEMCS24  = 0x24,
0279     DESC_RATEMCS25  = 0x25,
0280     DESC_RATEMCS26  = 0x26,
0281     DESC_RATEMCS27  = 0x27,
0282     DESC_RATEMCS28  = 0x28,
0283     DESC_RATEMCS29  = 0x29,
0284     DESC_RATEMCS30  = 0x2a,
0285     DESC_RATEMCS31  = 0x2b,
0286 
0287     DESC_RATEVHT1SS_MCS0    = 0x2c,
0288     DESC_RATEVHT1SS_MCS1    = 0x2d,
0289     DESC_RATEVHT1SS_MCS2    = 0x2e,
0290     DESC_RATEVHT1SS_MCS3    = 0x2f,
0291     DESC_RATEVHT1SS_MCS4    = 0x30,
0292     DESC_RATEVHT1SS_MCS5    = 0x31,
0293     DESC_RATEVHT1SS_MCS6    = 0x32,
0294     DESC_RATEVHT1SS_MCS7    = 0x33,
0295     DESC_RATEVHT1SS_MCS8    = 0x34,
0296     DESC_RATEVHT1SS_MCS9    = 0x35,
0297 
0298     DESC_RATEVHT2SS_MCS0    = 0x36,
0299     DESC_RATEVHT2SS_MCS1    = 0x37,
0300     DESC_RATEVHT2SS_MCS2    = 0x38,
0301     DESC_RATEVHT2SS_MCS3    = 0x39,
0302     DESC_RATEVHT2SS_MCS4    = 0x3a,
0303     DESC_RATEVHT2SS_MCS5    = 0x3b,
0304     DESC_RATEVHT2SS_MCS6    = 0x3c,
0305     DESC_RATEVHT2SS_MCS7    = 0x3d,
0306     DESC_RATEVHT2SS_MCS8    = 0x3e,
0307     DESC_RATEVHT2SS_MCS9    = 0x3f,
0308 
0309     DESC_RATEVHT3SS_MCS0    = 0x40,
0310     DESC_RATEVHT3SS_MCS1    = 0x41,
0311     DESC_RATEVHT3SS_MCS2    = 0x42,
0312     DESC_RATEVHT3SS_MCS3    = 0x43,
0313     DESC_RATEVHT3SS_MCS4    = 0x44,
0314     DESC_RATEVHT3SS_MCS5    = 0x45,
0315     DESC_RATEVHT3SS_MCS6    = 0x46,
0316     DESC_RATEVHT3SS_MCS7    = 0x47,
0317     DESC_RATEVHT3SS_MCS8    = 0x48,
0318     DESC_RATEVHT3SS_MCS9    = 0x49,
0319 
0320     DESC_RATEVHT4SS_MCS0    = 0x4a,
0321     DESC_RATEVHT4SS_MCS1    = 0x4b,
0322     DESC_RATEVHT4SS_MCS2    = 0x4c,
0323     DESC_RATEVHT4SS_MCS3    = 0x4d,
0324     DESC_RATEVHT4SS_MCS4    = 0x4e,
0325     DESC_RATEVHT4SS_MCS5    = 0x4f,
0326     DESC_RATEVHT4SS_MCS6    = 0x50,
0327     DESC_RATEVHT4SS_MCS7    = 0x51,
0328     DESC_RATEVHT4SS_MCS8    = 0x52,
0329     DESC_RATEVHT4SS_MCS9    = 0x53,
0330 
0331     DESC_RATE_MAX,
0332 };
0333 
0334 enum rtw_regulatory_domains {
0335     RTW_REGD_FCC        = 0,
0336     RTW_REGD_MKK        = 1,
0337     RTW_REGD_ETSI       = 2,
0338     RTW_REGD_IC     = 3,
0339     RTW_REGD_KCC        = 4,
0340     RTW_REGD_ACMA       = 5,
0341     RTW_REGD_CHILE      = 6,
0342     RTW_REGD_UKRAINE    = 7,
0343     RTW_REGD_MEXICO     = 8,
0344     RTW_REGD_CN     = 9,
0345     RTW_REGD_WW,
0346 
0347     RTW_REGD_MAX
0348 };
0349 
0350 enum rtw_txq_flags {
0351     RTW_TXQ_AMPDU,
0352     RTW_TXQ_BLOCK_BA,
0353 };
0354 
0355 enum rtw_flags {
0356     RTW_FLAG_RUNNING,
0357     RTW_FLAG_FW_RUNNING,
0358     RTW_FLAG_SCANNING,
0359     RTW_FLAG_INACTIVE_PS,
0360     RTW_FLAG_LEISURE_PS,
0361     RTW_FLAG_LEISURE_PS_DEEP,
0362     RTW_FLAG_DIG_DISABLE,
0363     RTW_FLAG_BUSY_TRAFFIC,
0364     RTW_FLAG_WOWLAN,
0365     RTW_FLAG_RESTARTING,
0366     RTW_FLAG_RESTART_TRIGGERING,
0367     RTW_FLAG_FORCE_LOWEST_RATE,
0368 
0369     NUM_OF_RTW_FLAGS,
0370 };
0371 
0372 enum rtw_evm {
0373     RTW_EVM_OFDM = 0,
0374     RTW_EVM_1SS,
0375     RTW_EVM_2SS_A,
0376     RTW_EVM_2SS_B,
0377     /* keep it last */
0378     RTW_EVM_NUM
0379 };
0380 
0381 enum rtw_snr {
0382     RTW_SNR_OFDM_A = 0,
0383     RTW_SNR_OFDM_B,
0384     RTW_SNR_OFDM_C,
0385     RTW_SNR_OFDM_D,
0386     RTW_SNR_1SS_A,
0387     RTW_SNR_1SS_B,
0388     RTW_SNR_1SS_C,
0389     RTW_SNR_1SS_D,
0390     RTW_SNR_2SS_A,
0391     RTW_SNR_2SS_B,
0392     RTW_SNR_2SS_C,
0393     RTW_SNR_2SS_D,
0394     /* keep it last */
0395     RTW_SNR_NUM
0396 };
0397 
0398 enum rtw_wow_flags {
0399     RTW_WOW_FLAG_EN_MAGIC_PKT,
0400     RTW_WOW_FLAG_EN_REKEY_PKT,
0401     RTW_WOW_FLAG_EN_DISCONNECT,
0402 
0403     /* keep it last */
0404     RTW_WOW_FLAG_MAX,
0405 };
0406 
0407 /* the power index is represented by differences, which cck-1s & ht40-1s are
0408  * the base values, so for 1s's differences, there are only ht20 & ofdm
0409  */
0410 struct rtw_2g_1s_pwr_idx_diff {
0411 #ifdef __LITTLE_ENDIAN
0412     s8 ofdm:4;
0413     s8 bw20:4;
0414 #else
0415     s8 bw20:4;
0416     s8 ofdm:4;
0417 #endif
0418 } __packed;
0419 
0420 struct rtw_2g_ns_pwr_idx_diff {
0421 #ifdef __LITTLE_ENDIAN
0422     s8 bw20:4;
0423     s8 bw40:4;
0424     s8 cck:4;
0425     s8 ofdm:4;
0426 #else
0427     s8 ofdm:4;
0428     s8 cck:4;
0429     s8 bw40:4;
0430     s8 bw20:4;
0431 #endif
0432 } __packed;
0433 
0434 struct rtw_2g_txpwr_idx {
0435     u8 cck_base[6];
0436     u8 bw40_base[5];
0437     struct rtw_2g_1s_pwr_idx_diff ht_1s_diff;
0438     struct rtw_2g_ns_pwr_idx_diff ht_2s_diff;
0439     struct rtw_2g_ns_pwr_idx_diff ht_3s_diff;
0440     struct rtw_2g_ns_pwr_idx_diff ht_4s_diff;
0441 };
0442 
0443 struct rtw_5g_ht_1s_pwr_idx_diff {
0444 #ifdef __LITTLE_ENDIAN
0445     s8 ofdm:4;
0446     s8 bw20:4;
0447 #else
0448     s8 bw20:4;
0449     s8 ofdm:4;
0450 #endif
0451 } __packed;
0452 
0453 struct rtw_5g_ht_ns_pwr_idx_diff {
0454 #ifdef __LITTLE_ENDIAN
0455     s8 bw20:4;
0456     s8 bw40:4;
0457 #else
0458     s8 bw40:4;
0459     s8 bw20:4;
0460 #endif
0461 } __packed;
0462 
0463 struct rtw_5g_ofdm_ns_pwr_idx_diff {
0464 #ifdef __LITTLE_ENDIAN
0465     s8 ofdm_3s:4;
0466     s8 ofdm_2s:4;
0467     s8 ofdm_4s:4;
0468     s8 res:4;
0469 #else
0470     s8 res:4;
0471     s8 ofdm_4s:4;
0472     s8 ofdm_2s:4;
0473     s8 ofdm_3s:4;
0474 #endif
0475 } __packed;
0476 
0477 struct rtw_5g_vht_ns_pwr_idx_diff {
0478 #ifdef __LITTLE_ENDIAN
0479     s8 bw160:4;
0480     s8 bw80:4;
0481 #else
0482     s8 bw80:4;
0483     s8 bw160:4;
0484 #endif
0485 } __packed;
0486 
0487 struct rtw_5g_txpwr_idx {
0488     u8 bw40_base[14];
0489     struct rtw_5g_ht_1s_pwr_idx_diff ht_1s_diff;
0490     struct rtw_5g_ht_ns_pwr_idx_diff ht_2s_diff;
0491     struct rtw_5g_ht_ns_pwr_idx_diff ht_3s_diff;
0492     struct rtw_5g_ht_ns_pwr_idx_diff ht_4s_diff;
0493     struct rtw_5g_ofdm_ns_pwr_idx_diff ofdm_diff;
0494     struct rtw_5g_vht_ns_pwr_idx_diff vht_1s_diff;
0495     struct rtw_5g_vht_ns_pwr_idx_diff vht_2s_diff;
0496     struct rtw_5g_vht_ns_pwr_idx_diff vht_3s_diff;
0497     struct rtw_5g_vht_ns_pwr_idx_diff vht_4s_diff;
0498 };
0499 
0500 struct rtw_txpwr_idx {
0501     struct rtw_2g_txpwr_idx pwr_idx_2g;
0502     struct rtw_5g_txpwr_idx pwr_idx_5g;
0503 };
0504 
0505 struct rtw_timer_list {
0506     struct timer_list timer;
0507     void (*function)(void *data);
0508     void *args;
0509 };
0510 
0511 struct rtw_channel_params {
0512     u8 center_chan;
0513     u8 bandwidth;
0514     u8 primary_chan_idx;
0515     /* center channel by different available bandwidth,
0516      * val of (bw > current bandwidth) is invalid
0517      */
0518     u8 cch_by_bw[RTW_MAX_CHANNEL_WIDTH + 1];
0519 };
0520 
0521 struct rtw_hw_reg {
0522     u32 addr;
0523     u32 mask;
0524 };
0525 
0526 struct rtw_ltecoex_addr {
0527     u32 ctrl;
0528     u32 wdata;
0529     u32 rdata;
0530 };
0531 
0532 struct rtw_reg_domain {
0533     u32 addr;
0534     u32 mask;
0535 #define RTW_REG_DOMAIN_MAC32    0
0536 #define RTW_REG_DOMAIN_MAC16    1
0537 #define RTW_REG_DOMAIN_MAC8 2
0538 #define RTW_REG_DOMAIN_RF_A 3
0539 #define RTW_REG_DOMAIN_RF_B 4
0540 #define RTW_REG_DOMAIN_NL   0xFF
0541     u8 domain;
0542 };
0543 
0544 struct rtw_rf_sipi_addr {
0545     u32 hssi_1;
0546     u32 hssi_2;
0547     u32 lssi_read;
0548     u32 lssi_read_pi;
0549 };
0550 
0551 struct rtw_hw_reg_offset {
0552     struct rtw_hw_reg hw_reg;
0553     u8 offset;
0554 };
0555 
0556 struct rtw_backup_info {
0557     u8 len;
0558     u32 reg;
0559     u32 val;
0560 };
0561 
0562 enum rtw_vif_port_set {
0563     PORT_SET_MAC_ADDR   = BIT(0),
0564     PORT_SET_BSSID      = BIT(1),
0565     PORT_SET_NET_TYPE   = BIT(2),
0566     PORT_SET_AID        = BIT(3),
0567     PORT_SET_BCN_CTRL   = BIT(4),
0568 };
0569 
0570 struct rtw_vif_port {
0571     struct rtw_hw_reg mac_addr;
0572     struct rtw_hw_reg bssid;
0573     struct rtw_hw_reg net_type;
0574     struct rtw_hw_reg aid;
0575     struct rtw_hw_reg bcn_ctrl;
0576 };
0577 
0578 struct rtw_tx_pkt_info {
0579     u32 tx_pkt_size;
0580     u8 offset;
0581     u8 pkt_offset;
0582     u8 tim_offset;
0583     u8 mac_id;
0584     u8 rate_id;
0585     u8 rate;
0586     u8 qsel;
0587     u8 bw;
0588     u8 sec_type;
0589     u8 sn;
0590     bool ampdu_en;
0591     u8 ampdu_factor;
0592     u8 ampdu_density;
0593     u16 seq;
0594     bool stbc;
0595     bool ldpc;
0596     bool dis_rate_fallback;
0597     bool bmc;
0598     bool use_rate;
0599     bool ls;
0600     bool fs;
0601     bool short_gi;
0602     bool report;
0603     bool rts;
0604     bool dis_qselseq;
0605     bool en_hwseq;
0606     u8 hw_ssn_sel;
0607     bool nav_use_hdr;
0608     bool bt_null;
0609 };
0610 
0611 struct rtw_rx_pkt_stat {
0612     bool phy_status;
0613     bool icv_err;
0614     bool crc_err;
0615     bool decrypted;
0616     bool is_c2h;
0617 
0618     s32 signal_power;
0619     u16 pkt_len;
0620     u8 bw;
0621     u8 drv_info_sz;
0622     u8 shift;
0623     u8 rate;
0624     u8 mac_id;
0625     u8 cam_id;
0626     u8 ppdu_cnt;
0627     u32 tsf_low;
0628     s8 rx_power[RTW_RF_PATH_MAX];
0629     u8 rssi;
0630     u8 rxsc;
0631     s8 rx_snr[RTW_RF_PATH_MAX];
0632     u8 rx_evm[RTW_RF_PATH_MAX];
0633     s8 cfo_tail[RTW_RF_PATH_MAX];
0634     u16 freq;
0635     u8 band;
0636 
0637     struct rtw_sta_info *si;
0638     struct ieee80211_vif *vif;
0639     struct ieee80211_hdr *hdr;
0640 };
0641 
0642 DECLARE_EWMA(tp, 10, 2);
0643 
0644 struct rtw_traffic_stats {
0645     /* units in bytes */
0646     u64 tx_unicast;
0647     u64 rx_unicast;
0648 
0649     /* count for packets */
0650     u64 tx_cnt;
0651     u64 rx_cnt;
0652 
0653     /* units in Mbps */
0654     u32 tx_throughput;
0655     u32 rx_throughput;
0656     struct ewma_tp tx_ewma_tp;
0657     struct ewma_tp rx_ewma_tp;
0658 };
0659 
0660 enum rtw_lps_mode {
0661     RTW_MODE_ACTIVE = 0,
0662     RTW_MODE_LPS    = 1,
0663     RTW_MODE_WMM_PS = 2,
0664 };
0665 
0666 enum rtw_lps_deep_mode {
0667     LPS_DEEP_MODE_NONE  = 0,
0668     LPS_DEEP_MODE_LCLK  = 1,
0669     LPS_DEEP_MODE_PG    = 2,
0670 };
0671 
0672 enum rtw_pwr_state {
0673     RTW_RF_OFF  = 0x0,
0674     RTW_RF_ON   = 0x4,
0675     RTW_ALL_ON  = 0xc,
0676 };
0677 
0678 struct rtw_lps_conf {
0679     enum rtw_lps_mode mode;
0680     enum rtw_lps_deep_mode deep_mode;
0681     enum rtw_lps_deep_mode wow_deep_mode;
0682     enum rtw_pwr_state state;
0683     u8 awake_interval;
0684     u8 rlbm;
0685     u8 smart_ps;
0686     u8 port_id;
0687     bool sec_cam_backup;
0688     bool pattern_cam_backup;
0689 };
0690 
0691 enum rtw_hw_key_type {
0692     RTW_CAM_NONE    = 0,
0693     RTW_CAM_WEP40   = 1,
0694     RTW_CAM_TKIP    = 2,
0695     RTW_CAM_AES = 4,
0696     RTW_CAM_WEP104  = 5,
0697 };
0698 
0699 struct rtw_cam_entry {
0700     bool valid;
0701     bool group;
0702     u8 addr[ETH_ALEN];
0703     u8 hw_key_type;
0704     struct ieee80211_key_conf *key;
0705 };
0706 
0707 struct rtw_sec_desc {
0708     /* search strategy */
0709     bool default_key_search;
0710 
0711     u32 total_cam_num;
0712     struct rtw_cam_entry cam_table[RTW_MAX_SEC_CAM_NUM];
0713     DECLARE_BITMAP(cam_map, RTW_MAX_SEC_CAM_NUM);
0714 };
0715 
0716 struct rtw_tx_report {
0717     /* protect the tx report queue */
0718     spinlock_t q_lock;
0719     struct sk_buff_head queue;
0720     atomic_t sn;
0721     struct timer_list purge_timer;
0722 };
0723 
0724 struct rtw_ra_report {
0725     struct rate_info txrate;
0726     u32 bit_rate;
0727     u8 desc_rate;
0728 };
0729 
0730 struct rtw_txq {
0731     struct list_head list;
0732 
0733     unsigned long flags;
0734     unsigned long last_push;
0735 };
0736 
0737 #define RTW_BC_MC_MACID 1
0738 DECLARE_EWMA(rssi, 10, 16);
0739 
0740 struct rtw_sta_info {
0741     struct ieee80211_sta *sta;
0742     struct ieee80211_vif *vif;
0743 
0744     struct ewma_rssi avg_rssi;
0745     u8 rssi_level;
0746 
0747     u8 mac_id;
0748     u8 rate_id;
0749     enum rtw_bandwidth bw_mode;
0750     enum rtw_rf_type rf_type;
0751     enum rtw_wireless_set wireless_set;
0752     u8 stbc_en:2;
0753     u8 ldpc_en:2;
0754     bool sgi_enable;
0755     bool vht_enable;
0756     u8 init_ra_lv;
0757     u64 ra_mask;
0758 
0759     DECLARE_BITMAP(tid_ba, IEEE80211_NUM_TIDS);
0760 
0761     struct rtw_ra_report ra_report;
0762 
0763     bool use_cfg_mask;
0764     struct cfg80211_bitrate_mask *mask;
0765 };
0766 
0767 enum rtw_bfee_role {
0768     RTW_BFEE_NONE,
0769     RTW_BFEE_SU,
0770     RTW_BFEE_MU
0771 };
0772 
0773 struct rtw_bfee {
0774     enum rtw_bfee_role role;
0775 
0776     u16 p_aid;
0777     u8 g_id;
0778     u8 mac_addr[ETH_ALEN];
0779     u8 sound_dim;
0780 
0781     /* SU-MIMO */
0782     u8 su_reg_index;
0783 
0784     /* MU-MIMO */
0785     u16 aid;
0786 };
0787 
0788 struct rtw_bf_info {
0789     u8 bfer_mu_cnt;
0790     u8 bfer_su_cnt;
0791     DECLARE_BITMAP(bfer_su_reg_maping, 2);
0792     u8 cur_csi_rpt_rate;
0793 };
0794 
0795 struct rtw_vif {
0796     enum rtw_net_type net_type;
0797     u16 aid;
0798     u8 mac_addr[ETH_ALEN];
0799     u8 bssid[ETH_ALEN];
0800     u8 port;
0801     u8 bcn_ctrl;
0802     struct list_head rsvd_page_list;
0803     struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS];
0804     const struct rtw_vif_port *conf;
0805     struct cfg80211_scan_request *scan_req;
0806     struct ieee80211_scan_ies *scan_ies;
0807 
0808     struct rtw_traffic_stats stats;
0809 
0810     struct rtw_bfee bfee;
0811 };
0812 
0813 struct rtw_regulatory {
0814     char alpha2[2];
0815     u8 txpwr_regd_2g;
0816     u8 txpwr_regd_5g;
0817 };
0818 
0819 enum rtw_regd_state {
0820     RTW_REGD_STATE_WORLDWIDE,
0821     RTW_REGD_STATE_PROGRAMMED,
0822     RTW_REGD_STATE_SETTING,
0823 
0824     RTW_REGD_STATE_NR,
0825 };
0826 
0827 struct rtw_regd {
0828     enum rtw_regd_state state;
0829     const struct rtw_regulatory *regulatory;
0830     enum nl80211_dfs_regions dfs_region;
0831 };
0832 
0833 struct rtw_chip_ops {
0834     int (*mac_init)(struct rtw_dev *rtwdev);
0835     int (*dump_fw_crash)(struct rtw_dev *rtwdev);
0836     void (*shutdown)(struct rtw_dev *rtwdev);
0837     int (*read_efuse)(struct rtw_dev *rtwdev, u8 *map);
0838     void (*phy_set_param)(struct rtw_dev *rtwdev);
0839     void (*set_channel)(struct rtw_dev *rtwdev, u8 channel,
0840                 u8 bandwidth, u8 primary_chan_idx);
0841     void (*query_rx_desc)(struct rtw_dev *rtwdev, u8 *rx_desc,
0842                   struct rtw_rx_pkt_stat *pkt_stat,
0843                   struct ieee80211_rx_status *rx_status);
0844     u32 (*read_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
0845                u32 addr, u32 mask);
0846     bool (*write_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
0847              u32 addr, u32 mask, u32 data);
0848     void (*set_tx_power_index)(struct rtw_dev *rtwdev);
0849     int (*rsvd_page_dump)(struct rtw_dev *rtwdev, u8 *buf, u32 offset,
0850                   u32 size);
0851     int (*set_antenna)(struct rtw_dev *rtwdev,
0852                u32 antenna_tx,
0853                u32 antenna_rx);
0854     void (*cfg_ldo25)(struct rtw_dev *rtwdev, bool enable);
0855     void (*efuse_grant)(struct rtw_dev *rtwdev, bool enable);
0856     void (*false_alarm_statistics)(struct rtw_dev *rtwdev);
0857     void (*phy_calibration)(struct rtw_dev *rtwdev);
0858     void (*dpk_track)(struct rtw_dev *rtwdev);
0859     void (*cck_pd_set)(struct rtw_dev *rtwdev, u8 level);
0860     void (*pwr_track)(struct rtw_dev *rtwdev);
0861     void (*config_bfee)(struct rtw_dev *rtwdev, struct rtw_vif *vif,
0862                 struct rtw_bfee *bfee, bool enable);
0863     void (*set_gid_table)(struct rtw_dev *rtwdev,
0864                   struct ieee80211_vif *vif,
0865                   struct ieee80211_bss_conf *conf);
0866     void (*cfg_csi_rate)(struct rtw_dev *rtwdev, u8 rssi, u8 cur_rate,
0867                  u8 fixrate_en, u8 *new_rate);
0868     void (*adaptivity_init)(struct rtw_dev *rtwdev);
0869     void (*adaptivity)(struct rtw_dev *rtwdev);
0870     void (*cfo_init)(struct rtw_dev *rtwdev);
0871     void (*cfo_track)(struct rtw_dev *rtwdev);
0872     void (*config_tx_path)(struct rtw_dev *rtwdev, u8 tx_path,
0873                    enum rtw_bb_path tx_path_1ss,
0874                    enum rtw_bb_path tx_path_cck,
0875                    bool is_tx2_path);
0876     void (*config_txrx_mode)(struct rtw_dev *rtwdev, u8 tx_path,
0877                  u8 rx_path, bool is_tx2_path);
0878 
0879     /* for coex */
0880     void (*coex_set_init)(struct rtw_dev *rtwdev);
0881     void (*coex_set_ant_switch)(struct rtw_dev *rtwdev,
0882                     u8 ctrl_type, u8 pos_type);
0883     void (*coex_set_gnt_fix)(struct rtw_dev *rtwdev);
0884     void (*coex_set_gnt_debug)(struct rtw_dev *rtwdev);
0885     void (*coex_set_rfe_type)(struct rtw_dev *rtwdev);
0886     void (*coex_set_wl_tx_power)(struct rtw_dev *rtwdev, u8 wl_pwr);
0887     void (*coex_set_wl_rx_gain)(struct rtw_dev *rtwdev, bool low_gain);
0888 };
0889 
0890 #define RTW_PWR_POLLING_CNT 20000
0891 
0892 #define RTW_PWR_CMD_READ    0x00
0893 #define RTW_PWR_CMD_WRITE   0x01
0894 #define RTW_PWR_CMD_POLLING 0x02
0895 #define RTW_PWR_CMD_DELAY   0x03
0896 #define RTW_PWR_CMD_END     0x04
0897 
0898 /* define the base address of each block */
0899 #define RTW_PWR_ADDR_MAC    0x00
0900 #define RTW_PWR_ADDR_USB    0x01
0901 #define RTW_PWR_ADDR_PCIE   0x02
0902 #define RTW_PWR_ADDR_SDIO   0x03
0903 
0904 #define RTW_PWR_INTF_SDIO_MSK   BIT(0)
0905 #define RTW_PWR_INTF_USB_MSK    BIT(1)
0906 #define RTW_PWR_INTF_PCI_MSK    BIT(2)
0907 #define RTW_PWR_INTF_ALL_MSK    (BIT(0) | BIT(1) | BIT(2) | BIT(3))
0908 
0909 #define RTW_PWR_CUT_TEST_MSK    BIT(0)
0910 #define RTW_PWR_CUT_A_MSK   BIT(1)
0911 #define RTW_PWR_CUT_B_MSK   BIT(2)
0912 #define RTW_PWR_CUT_C_MSK   BIT(3)
0913 #define RTW_PWR_CUT_D_MSK   BIT(4)
0914 #define RTW_PWR_CUT_E_MSK   BIT(5)
0915 #define RTW_PWR_CUT_F_MSK   BIT(6)
0916 #define RTW_PWR_CUT_G_MSK   BIT(7)
0917 #define RTW_PWR_CUT_ALL_MSK 0xFF
0918 
0919 enum rtw_pwr_seq_cmd_delay_unit {
0920     RTW_PWR_DELAY_US,
0921     RTW_PWR_DELAY_MS,
0922 };
0923 
0924 struct rtw_pwr_seq_cmd {
0925     u16 offset;
0926     u8 cut_mask;
0927     u8 intf_mask;
0928     u8 base:4;
0929     u8 cmd:4;
0930     u8 mask;
0931     u8 value;
0932 };
0933 
0934 enum rtw_chip_ver {
0935     RTW_CHIP_VER_CUT_A = 0x00,
0936     RTW_CHIP_VER_CUT_B = 0x01,
0937     RTW_CHIP_VER_CUT_C = 0x02,
0938     RTW_CHIP_VER_CUT_D = 0x03,
0939     RTW_CHIP_VER_CUT_E = 0x04,
0940     RTW_CHIP_VER_CUT_F = 0x05,
0941     RTW_CHIP_VER_CUT_G = 0x06,
0942 };
0943 
0944 #define RTW_INTF_PHY_PLATFORM_ALL 0
0945 
0946 enum rtw_intf_phy_cut {
0947     RTW_INTF_PHY_CUT_A = BIT(0),
0948     RTW_INTF_PHY_CUT_B = BIT(1),
0949     RTW_INTF_PHY_CUT_C = BIT(2),
0950     RTW_INTF_PHY_CUT_D = BIT(3),
0951     RTW_INTF_PHY_CUT_E = BIT(4),
0952     RTW_INTF_PHY_CUT_F = BIT(5),
0953     RTW_INTF_PHY_CUT_G = BIT(6),
0954     RTW_INTF_PHY_CUT_ALL = 0xFFFF,
0955 };
0956 
0957 enum rtw_ip_sel {
0958     RTW_IP_SEL_PHY = 0,
0959     RTW_IP_SEL_MAC = 1,
0960     RTW_IP_SEL_DBI = 2,
0961 
0962     RTW_IP_SEL_UNDEF = 0xFFFF
0963 };
0964 
0965 enum rtw_pq_map_id {
0966     RTW_PQ_MAP_VO = 0x0,
0967     RTW_PQ_MAP_VI = 0x1,
0968     RTW_PQ_MAP_BE = 0x2,
0969     RTW_PQ_MAP_BK = 0x3,
0970     RTW_PQ_MAP_MG = 0x4,
0971     RTW_PQ_MAP_HI = 0x5,
0972     RTW_PQ_MAP_NUM = 0x6,
0973 
0974     RTW_PQ_MAP_UNDEF,
0975 };
0976 
0977 enum rtw_dma_mapping {
0978     RTW_DMA_MAPPING_EXTRA   = 0,
0979     RTW_DMA_MAPPING_LOW = 1,
0980     RTW_DMA_MAPPING_NORMAL  = 2,
0981     RTW_DMA_MAPPING_HIGH    = 3,
0982 
0983     RTW_DMA_MAPPING_MAX,
0984     RTW_DMA_MAPPING_UNDEF,
0985 };
0986 
0987 struct rtw_rqpn {
0988     enum rtw_dma_mapping dma_map_vo;
0989     enum rtw_dma_mapping dma_map_vi;
0990     enum rtw_dma_mapping dma_map_be;
0991     enum rtw_dma_mapping dma_map_bk;
0992     enum rtw_dma_mapping dma_map_mg;
0993     enum rtw_dma_mapping dma_map_hi;
0994 };
0995 
0996 struct rtw_prioq_addr {
0997     u32 rsvd;
0998     u32 avail;
0999 };
1000 
1001 struct rtw_prioq_addrs {
1002     struct rtw_prioq_addr prio[RTW_DMA_MAPPING_MAX];
1003     bool wsize;
1004 };
1005 
1006 struct rtw_page_table {
1007     u16 hq_num;
1008     u16 nq_num;
1009     u16 lq_num;
1010     u16 exq_num;
1011     u16 gapq_num;
1012 };
1013 
1014 struct rtw_intf_phy_para {
1015     u16 offset;
1016     u16 value;
1017     u16 ip_sel;
1018     u16 cut_mask;
1019     u16 platform;
1020 };
1021 
1022 struct rtw_wow_pattern {
1023     u16 crc;
1024     u8 type;
1025     u8 valid;
1026     u8 mask[RTW_MAX_PATTERN_MASK_SIZE];
1027 };
1028 
1029 struct rtw_pno_request {
1030     bool inited;
1031     u32 match_set_cnt;
1032     struct cfg80211_match_set *match_sets;
1033     u8 channel_cnt;
1034     struct ieee80211_channel *channels;
1035     struct cfg80211_sched_scan_plan scan_plan;
1036 };
1037 
1038 struct rtw_wow_param {
1039     struct ieee80211_vif *wow_vif;
1040     DECLARE_BITMAP(flags, RTW_WOW_FLAG_MAX);
1041     u8 txpause;
1042     u8 pattern_cnt;
1043     struct rtw_wow_pattern patterns[RTW_MAX_PATTERN_NUM];
1044 
1045     bool ips_enabled;
1046     struct rtw_pno_request pno_req;
1047 };
1048 
1049 struct rtw_intf_phy_para_table {
1050     const struct rtw_intf_phy_para *usb2_para;
1051     const struct rtw_intf_phy_para *usb3_para;
1052     const struct rtw_intf_phy_para *gen1_para;
1053     const struct rtw_intf_phy_para *gen2_para;
1054     u8 n_usb2_para;
1055     u8 n_usb3_para;
1056     u8 n_gen1_para;
1057     u8 n_gen2_para;
1058 };
1059 
1060 struct rtw_table {
1061     const void *data;
1062     const u32 size;
1063     void (*parse)(struct rtw_dev *rtwdev, const struct rtw_table *tbl);
1064     void (*do_cfg)(struct rtw_dev *rtwdev, const struct rtw_table *tbl,
1065                u32 addr, u32 data);
1066     enum rtw_rf_path rf_path;
1067 };
1068 
1069 static inline void rtw_load_table(struct rtw_dev *rtwdev,
1070                   const struct rtw_table *tbl)
1071 {
1072     (*tbl->parse)(rtwdev, tbl);
1073 }
1074 
1075 enum rtw_rfe_fem {
1076     RTW_RFE_IFEM,
1077     RTW_RFE_EFEM,
1078     RTW_RFE_IFEM2G_EFEM5G,
1079     RTW_RFE_NUM,
1080 };
1081 
1082 struct rtw_rfe_def {
1083     const struct rtw_table *phy_pg_tbl;
1084     const struct rtw_table *txpwr_lmt_tbl;
1085     const struct rtw_table *agc_btg_tbl;
1086 };
1087 
1088 #define RTW_DEF_RFE(chip, bb_pg, pwrlmt) {                \
1089     .phy_pg_tbl = &rtw ## chip ## _bb_pg_type ## bb_pg ## _tbl,   \
1090     .txpwr_lmt_tbl = &rtw ## chip ## _txpwr_lmt_type ## pwrlmt ## _tbl, \
1091     }
1092 
1093 #define RTW_DEF_RFE_EXT(chip, bb_pg, pwrlmt, btg) {           \
1094     .phy_pg_tbl = &rtw ## chip ## _bb_pg_type ## bb_pg ## _tbl,   \
1095     .txpwr_lmt_tbl = &rtw ## chip ## _txpwr_lmt_type ## pwrlmt ## _tbl, \
1096     .agc_btg_tbl = &rtw ## chip ## _agc_btg_type ## btg ## _tbl, \
1097     }
1098 
1099 #define RTW_PWR_TRK_5G_1        0
1100 #define RTW_PWR_TRK_5G_2        1
1101 #define RTW_PWR_TRK_5G_3        2
1102 #define RTW_PWR_TRK_5G_NUM      3
1103 
1104 #define RTW_PWR_TRK_TBL_SZ      30
1105 
1106 /* This table stores the values of TX power that will be adjusted by power
1107  * tracking.
1108  *
1109  * For 5G bands, there are 3 different settings.
1110  * For 2G there are cck rate and ofdm rate with different settings.
1111  */
1112 struct rtw_pwr_track_tbl {
1113     const u8 *pwrtrk_5gb_n[RTW_PWR_TRK_5G_NUM];
1114     const u8 *pwrtrk_5gb_p[RTW_PWR_TRK_5G_NUM];
1115     const u8 *pwrtrk_5ga_n[RTW_PWR_TRK_5G_NUM];
1116     const u8 *pwrtrk_5ga_p[RTW_PWR_TRK_5G_NUM];
1117     const u8 *pwrtrk_2gb_n;
1118     const u8 *pwrtrk_2gb_p;
1119     const u8 *pwrtrk_2ga_n;
1120     const u8 *pwrtrk_2ga_p;
1121     const u8 *pwrtrk_2g_cckb_n;
1122     const u8 *pwrtrk_2g_cckb_p;
1123     const u8 *pwrtrk_2g_ccka_n;
1124     const u8 *pwrtrk_2g_ccka_p;
1125     const s8 *pwrtrk_xtal_n;
1126     const s8 *pwrtrk_xtal_p;
1127 };
1128 
1129 enum rtw_wlan_cpu {
1130     RTW_WCPU_11AC,
1131     RTW_WCPU_11N,
1132 };
1133 
1134 enum rtw_fw_fifo_sel {
1135     RTW_FW_FIFO_SEL_TX,
1136     RTW_FW_FIFO_SEL_RX,
1137     RTW_FW_FIFO_SEL_RSVD_PAGE,
1138     RTW_FW_FIFO_SEL_REPORT,
1139     RTW_FW_FIFO_SEL_LLT,
1140     RTW_FW_FIFO_SEL_RXBUF_FW,
1141 
1142     RTW_FW_FIFO_MAX,
1143 };
1144 
1145 enum rtw_fwcd_item {
1146     RTW_FWCD_TLV,
1147     RTW_FWCD_REG,
1148     RTW_FWCD_ROM,
1149     RTW_FWCD_IMEM,
1150     RTW_FWCD_DMEM,
1151     RTW_FWCD_EMEM,
1152 };
1153 
1154 /* hardware configuration for each IC */
1155 struct rtw_chip_info {
1156     struct rtw_chip_ops *ops;
1157     u8 id;
1158 
1159     const char *fw_name;
1160     enum rtw_wlan_cpu wlan_cpu;
1161     u8 tx_pkt_desc_sz;
1162     u8 tx_buf_desc_sz;
1163     u8 rx_pkt_desc_sz;
1164     u8 rx_buf_desc_sz;
1165     u32 phy_efuse_size;
1166     u32 log_efuse_size;
1167     u32 ptct_efuse_size;
1168     u32 txff_size;
1169     u32 rxff_size;
1170     u32 fw_rxff_size;
1171     u8 band;
1172     u8 page_size;
1173     u8 csi_buf_pg_num;
1174     u8 dig_max;
1175     u8 dig_min;
1176     u8 txgi_factor;
1177     bool is_pwr_by_rate_dec;
1178     bool rx_ldpc;
1179     bool tx_stbc;
1180     u8 max_power_index;
1181     u8 ampdu_density;
1182 
1183     u16 fw_fifo_addr[RTW_FW_FIFO_MAX];
1184     const struct rtw_fwcd_segs *fwcd_segs;
1185 
1186     u8 default_1ss_tx_path;
1187 
1188     bool path_div_supported;
1189     bool ht_supported;
1190     bool vht_supported;
1191     u8 lps_deep_mode_supported;
1192 
1193     /* init values */
1194     u8 sys_func_en;
1195     const struct rtw_pwr_seq_cmd **pwr_on_seq;
1196     const struct rtw_pwr_seq_cmd **pwr_off_seq;
1197     const struct rtw_rqpn *rqpn_table;
1198     const struct rtw_prioq_addrs *prioq_addrs;
1199     const struct rtw_page_table *page_table;
1200     const struct rtw_intf_phy_para_table *intf_table;
1201 
1202     const struct rtw_hw_reg *dig;
1203     const struct rtw_hw_reg *dig_cck;
1204     u32 rf_base_addr[2];
1205     u32 rf_sipi_addr[2];
1206     const struct rtw_rf_sipi_addr *rf_sipi_read_addr;
1207     u8 fix_rf_phy_num;
1208     const struct rtw_ltecoex_addr *ltecoex_addr;
1209 
1210     const struct rtw_table *mac_tbl;
1211     const struct rtw_table *agc_tbl;
1212     const struct rtw_table *bb_tbl;
1213     const struct rtw_table *rf_tbl[RTW_RF_PATH_MAX];
1214     const struct rtw_table *rfk_init_tbl;
1215 
1216     const struct rtw_rfe_def *rfe_defs;
1217     u32 rfe_defs_size;
1218 
1219     bool en_dis_dpd;
1220     u16 dpd_ratemask;
1221     u8 iqk_threshold;
1222     u8 lck_threshold;
1223     const struct rtw_pwr_track_tbl *pwr_track_tbl;
1224 
1225     u8 bfer_su_max_num;
1226     u8 bfer_mu_max_num;
1227 
1228     struct rtw_hw_reg_offset *edcca_th;
1229     s8 l2h_th_ini_cs;
1230     s8 l2h_th_ini_ad;
1231 
1232     const char *wow_fw_name;
1233     const struct wiphy_wowlan_support *wowlan_stub;
1234     const u8 max_sched_scan_ssids;
1235 
1236     /* coex paras */
1237     u32 coex_para_ver;
1238     u8 bt_desired_ver;
1239     bool scbd_support;
1240     bool new_scbd10_def; /* true: fix 2M(8822c) */
1241     bool ble_hid_profile_support;
1242     bool wl_mimo_ps_support;
1243     u8 pstdma_type; /* 0: LPSoff, 1:LPSon */
1244     u8 bt_rssi_type;
1245     u8 ant_isolation;
1246     u8 rssi_tolerance;
1247     u8 table_sant_num;
1248     u8 table_nsant_num;
1249     u8 tdma_sant_num;
1250     u8 tdma_nsant_num;
1251     u8 bt_afh_span_bw20;
1252     u8 bt_afh_span_bw40;
1253     u8 afh_5g_num;
1254     u8 wl_rf_para_num;
1255     u8 coex_info_hw_regs_num;
1256     const u8 *bt_rssi_step;
1257     const u8 *wl_rssi_step;
1258     const struct coex_table_para *table_nsant;
1259     const struct coex_table_para *table_sant;
1260     const struct coex_tdma_para *tdma_sant;
1261     const struct coex_tdma_para *tdma_nsant;
1262     const struct coex_rf_para *wl_rf_para_tx;
1263     const struct coex_rf_para *wl_rf_para_rx;
1264     const struct coex_5g_afh_map *afh_5g;
1265     const struct rtw_hw_reg *btg_reg;
1266     const struct rtw_reg_domain *coex_info_hw_regs;
1267     u32 wl_fw_desired_ver;
1268 };
1269 
1270 enum rtw_coex_bt_state_cnt {
1271     COEX_CNT_BT_RETRY,
1272     COEX_CNT_BT_REINIT,
1273     COEX_CNT_BT_REENABLE,
1274     COEX_CNT_BT_POPEVENT,
1275     COEX_CNT_BT_SETUPLINK,
1276     COEX_CNT_BT_IGNWLANACT,
1277     COEX_CNT_BT_INQ,
1278     COEX_CNT_BT_PAGE,
1279     COEX_CNT_BT_ROLESWITCH,
1280     COEX_CNT_BT_AFHUPDATE,
1281     COEX_CNT_BT_INFOUPDATE,
1282     COEX_CNT_BT_IQK,
1283     COEX_CNT_BT_IQKFAIL,
1284 
1285     COEX_CNT_BT_MAX
1286 };
1287 
1288 enum rtw_coex_wl_state_cnt {
1289     COEX_CNT_WL_SCANAP,
1290     COEX_CNT_WL_CONNPKT,
1291     COEX_CNT_WL_COEXRUN,
1292     COEX_CNT_WL_NOISY0,
1293     COEX_CNT_WL_NOISY1,
1294     COEX_CNT_WL_NOISY2,
1295     COEX_CNT_WL_5MS_NOEXTEND,
1296     COEX_CNT_WL_FW_NOTIFY,
1297 
1298     COEX_CNT_WL_MAX
1299 };
1300 
1301 struct rtw_coex_rfe {
1302     bool ant_switch_exist;
1303     bool ant_switch_diversity;
1304     bool ant_switch_with_bt;
1305     u8 rfe_module_type;
1306     u8 ant_switch_polarity;
1307 
1308     /* true if WLG at BTG, else at WLAG */
1309     bool wlg_at_btg;
1310 };
1311 
1312 #define COEX_WL_TDMA_PARA_LENGTH    5
1313 
1314 struct rtw_coex_dm {
1315     bool cur_ps_tdma_on;
1316     bool cur_wl_rx_low_gain_en;
1317     bool ignore_wl_act;
1318 
1319     u8 reason;
1320     u8 bt_rssi_state[4];
1321     u8 wl_rssi_state[4];
1322     u8 wl_ch_info[3];
1323     u8 cur_ps_tdma;
1324     u8 cur_table;
1325     u8 ps_tdma_para[5];
1326     u8 cur_bt_pwr_lvl;
1327     u8 cur_bt_lna_lvl;
1328     u8 cur_wl_pwr_lvl;
1329     u8 bt_status;
1330     u32 cur_ant_pos_type;
1331     u32 cur_switch_status;
1332     u32 setting_tdma;
1333     u8 fw_tdma_para[COEX_WL_TDMA_PARA_LENGTH];
1334 };
1335 
1336 #define COEX_BTINFO_SRC_WL_FW   0x0
1337 #define COEX_BTINFO_SRC_BT_RSP  0x1
1338 #define COEX_BTINFO_SRC_BT_ACT  0x2
1339 #define COEX_BTINFO_SRC_BT_IQK  0x3
1340 #define COEX_BTINFO_SRC_BT_SCBD 0x4
1341 #define COEX_BTINFO_SRC_H2C60   0x5
1342 #define COEX_BTINFO_SRC_MAX 0x6
1343 
1344 #define COEX_INFO_FTP       BIT(7)
1345 #define COEX_INFO_A2DP      BIT(6)
1346 #define COEX_INFO_HID       BIT(5)
1347 #define COEX_INFO_SCO_BUSY  BIT(4)
1348 #define COEX_INFO_ACL_BUSY  BIT(3)
1349 #define COEX_INFO_INQ_PAGE  BIT(2)
1350 #define COEX_INFO_SCO_ESCO  BIT(1)
1351 #define COEX_INFO_CONNECTION    BIT(0)
1352 #define COEX_BTINFO_LENGTH_MAX  10
1353 #define COEX_BTINFO_LENGTH  7
1354 
1355 #define COEX_BT_HIDINFO_LIST    0x0
1356 #define COEX_BT_HIDINFO_A   0x1
1357 #define COEX_BT_HIDINFO_NAME    3
1358 
1359 #define COEX_BT_HIDINFO_LENGTH  6
1360 #define COEX_BT_HIDINFO_HANDLE_NUM  4
1361 #define COEX_BT_HIDINFO_C2H_HANDLE  0
1362 #define COEX_BT_HIDINFO_C2H_VENDOR  1
1363 #define COEX_BT_BLE_HANDLE_THRS 0x10
1364 #define COEX_BT_HIDINFO_NOTCON  0xff
1365 
1366 struct rtw_coex_hid {
1367     u8 hid_handle;
1368     u8 hid_vendor;
1369     u8 hid_name[COEX_BT_HIDINFO_NAME];
1370     bool hid_info_completed;
1371     bool is_game_hid;
1372 };
1373 
1374 struct rtw_coex_hid_handle_list {
1375     u8 cmd_id;
1376     u8 len;
1377     u8 subid;
1378     u8 handle_cnt;
1379     u8 handle[COEX_BT_HIDINFO_HANDLE_NUM];
1380 } __packed;
1381 
1382 struct rtw_coex_hid_info_a {
1383     u8 cmd_id;
1384     u8 len;
1385     u8 subid;
1386     u8 handle;
1387     u8 vendor;
1388     u8 name[COEX_BT_HIDINFO_NAME];
1389 } __packed;
1390 
1391 struct rtw_coex_stat {
1392     bool bt_disabled;
1393     bool bt_disabled_pre;
1394     bool bt_link_exist;
1395     bool bt_whck_test;
1396     bool bt_inq_page;
1397     bool bt_inq_remain;
1398     bool bt_inq;
1399     bool bt_page;
1400     bool bt_ble_voice;
1401     bool bt_ble_exist;
1402     bool bt_hfp_exist;
1403     bool bt_a2dp_exist;
1404     bool bt_hid_exist;
1405     bool bt_pan_exist; /* PAN or OPP */
1406     bool bt_opp_exist; /* OPP only */
1407     bool bt_acl_busy;
1408     bool bt_fix_2M;
1409     bool bt_setup_link;
1410     bool bt_multi_link;
1411     bool bt_multi_link_pre;
1412     bool bt_multi_link_remain;
1413     bool bt_a2dp_sink;
1414     bool bt_a2dp_active;
1415     bool bt_reenable;
1416     bool bt_ble_scan_en;
1417     bool bt_init_scan;
1418     bool bt_slave;
1419     bool bt_418_hid_exist;
1420     bool bt_ble_hid_exist;
1421     bool bt_game_hid_exist;
1422     bool bt_hid_handle_cnt;
1423     bool bt_mailbox_reply;
1424 
1425     bool wl_under_lps;
1426     bool wl_under_ips;
1427     bool wl_hi_pri_task1;
1428     bool wl_hi_pri_task2;
1429     bool wl_force_lps_ctrl;
1430     bool wl_gl_busy;
1431     bool wl_linkscan_proc;
1432     bool wl_ps_state_fail;
1433     bool wl_tx_limit_en;
1434     bool wl_ampdu_limit_en;
1435     bool wl_connected;
1436     bool wl_slot_extend;
1437     bool wl_cck_lock;
1438     bool wl_cck_lock_pre;
1439     bool wl_cck_lock_ever;
1440     bool wl_connecting;
1441     bool wl_slot_toggle;
1442     bool wl_slot_toggle_change; /* if toggle to no-toggle */
1443     bool wl_mimo_ps;
1444 
1445     u32 bt_supported_version;
1446     u32 bt_supported_feature;
1447     u32 hi_pri_tx;
1448     u32 hi_pri_rx;
1449     u32 lo_pri_tx;
1450     u32 lo_pri_rx;
1451     u32 patch_ver;
1452     u16 bt_reg_vendor_ae;
1453     u16 bt_reg_vendor_ac;
1454     s8 bt_rssi;
1455     u8 kt_ver;
1456     u8 gnt_workaround_state;
1457     u8 tdma_timer_base;
1458     u8 bt_profile_num;
1459     u8 bt_info_c2h[COEX_BTINFO_SRC_MAX][COEX_BTINFO_LENGTH_MAX];
1460     u8 bt_info_lb2;
1461     u8 bt_info_lb3;
1462     u8 bt_info_hb0;
1463     u8 bt_info_hb1;
1464     u8 bt_info_hb2;
1465     u8 bt_info_hb3;
1466     u8 bt_ble_scan_type;
1467     u8 bt_hid_pair_num;
1468     u8 bt_hid_slot;
1469     u8 bt_a2dp_bitpool;
1470     u8 bt_iqk_state;
1471 
1472     u16 wl_beacon_interval;
1473     u8 wl_noisy_level;
1474     u8 wl_fw_dbg_info[10];
1475     u8 wl_fw_dbg_info_pre[10];
1476     u8 wl_rx_rate;
1477     u8 wl_tx_rate;
1478     u8 wl_rts_rx_rate;
1479     u8 wl_coex_mode;
1480     u8 wl_iot_peer;
1481     u8 ampdu_max_time;
1482     u8 wl_tput_dir;
1483 
1484     u8 wl_toggle_para[6];
1485     u8 wl_toggle_interval;
1486 
1487     u16 score_board;
1488     u16 retry_limit;
1489 
1490     /* counters to record bt states */
1491     u32 cnt_bt[COEX_CNT_BT_MAX];
1492 
1493     /* counters to record wifi states */
1494     u32 cnt_wl[COEX_CNT_WL_MAX];
1495 
1496     /* counters to record bt c2h data */
1497     u32 cnt_bt_info_c2h[COEX_BTINFO_SRC_MAX];
1498 
1499     u32 darfrc;
1500     u32 darfrch;
1501 
1502     struct rtw_coex_hid hid_info[COEX_BT_HIDINFO_HANDLE_NUM];
1503     struct rtw_coex_hid_handle_list hid_handle_list;
1504 };
1505 
1506 struct rtw_coex {
1507     /* protects coex info request section */
1508     struct mutex mutex;
1509     struct sk_buff_head queue;
1510     wait_queue_head_t wait;
1511 
1512     bool under_5g;
1513     bool stop_dm;
1514     bool freeze;
1515     bool freerun;
1516     bool wl_rf_off;
1517     bool manual_control;
1518 
1519     struct rtw_coex_stat stat;
1520     struct rtw_coex_dm dm;
1521     struct rtw_coex_rfe rfe;
1522 
1523     struct delayed_work bt_relink_work;
1524     struct delayed_work bt_reenable_work;
1525     struct delayed_work defreeze_work;
1526     struct delayed_work wl_remain_work;
1527     struct delayed_work bt_remain_work;
1528     struct delayed_work wl_connecting_work;
1529     struct delayed_work bt_multi_link_remain_work;
1530     struct delayed_work wl_ccklock_work;
1531 
1532 };
1533 
1534 #define DPK_RF_REG_NUM 7
1535 #define DPK_RF_PATH_NUM 2
1536 #define DPK_BB_REG_NUM 18
1537 #define DPK_CHANNEL_WIDTH_80 1
1538 
1539 DECLARE_EWMA(thermal, 10, 4);
1540 
1541 struct rtw_dpk_info {
1542     bool is_dpk_pwr_on;
1543     bool is_reload;
1544 
1545     DECLARE_BITMAP(dpk_path_ok, DPK_RF_PATH_NUM);
1546 
1547     u8 thermal_dpk[DPK_RF_PATH_NUM];
1548     struct ewma_thermal avg_thermal[DPK_RF_PATH_NUM];
1549 
1550     u32 gnt_control;
1551     u32 gnt_value;
1552 
1553     u8 result[RTW_RF_PATH_MAX];
1554     u8 dpk_txagc[RTW_RF_PATH_MAX];
1555     u32 coef[RTW_RF_PATH_MAX][20];
1556     u16 dpk_gs[RTW_RF_PATH_MAX];
1557     u8 thermal_dpk_delta[RTW_RF_PATH_MAX];
1558     u8 pre_pwsf[RTW_RF_PATH_MAX];
1559 
1560     u8 dpk_band;
1561     u8 dpk_ch;
1562     u8 dpk_bw;
1563 };
1564 
1565 struct rtw_phy_cck_pd_reg {
1566     u32 reg_pd;
1567     u32 mask_pd;
1568     u32 reg_cs;
1569     u32 mask_cs;
1570 };
1571 
1572 #define DACK_MSBK_BACKUP_NUM    0xf
1573 #define DACK_DCK_BACKUP_NUM 0x2
1574 
1575 struct rtw_swing_table {
1576     const u8 *p[RTW_RF_PATH_MAX];
1577     const u8 *n[RTW_RF_PATH_MAX];
1578 };
1579 
1580 struct rtw_pkt_count {
1581     u16 num_bcn_pkt;
1582     u16 num_qry_pkt[DESC_RATE_MAX];
1583 };
1584 
1585 DECLARE_EWMA(evm, 10, 4);
1586 DECLARE_EWMA(snr, 10, 4);
1587 
1588 struct rtw_iqk_info {
1589     bool done;
1590     struct {
1591         u32 s1_x;
1592         u32 s1_y;
1593         u32 s0_x;
1594         u32 s0_y;
1595     } result;
1596 };
1597 
1598 enum rtw_rf_band {
1599     RF_BAND_2G_CCK,
1600     RF_BAND_2G_OFDM,
1601     RF_BAND_5G_L,
1602     RF_BAND_5G_M,
1603     RF_BAND_5G_H,
1604     RF_BAND_MAX
1605 };
1606 
1607 #define RF_GAIN_NUM 11
1608 #define RF_HW_OFFSET_NUM 10
1609 
1610 struct rtw_gapk_info {
1611     u32 rf3f_bp[RF_BAND_MAX][RF_GAIN_NUM][RTW_RF_PATH_MAX];
1612     u32 rf3f_fs[RTW_RF_PATH_MAX][RF_GAIN_NUM];
1613     bool txgapk_bp_done;
1614     s8 offset[RF_GAIN_NUM][RTW_RF_PATH_MAX];
1615     s8 fianl_offset[RF_GAIN_NUM][RTW_RF_PATH_MAX];
1616     u8 read_txgain;
1617     u8 channel;
1618 };
1619 
1620 #define EDCCA_TH_L2H_IDX 0
1621 #define EDCCA_TH_H2L_IDX 1
1622 #define EDCCA_TH_L2H_LB 48
1623 #define EDCCA_ADC_BACKOFF 12
1624 #define EDCCA_IGI_BASE 50
1625 #define EDCCA_IGI_L2H_DIFF 8
1626 #define EDCCA_L2H_H2L_DIFF 7
1627 #define EDCCA_L2H_H2L_DIFF_NORMAL 8
1628 
1629 enum rtw_edcca_mode {
1630     RTW_EDCCA_NORMAL    = 0,
1631     RTW_EDCCA_ADAPTIVITY    = 1,
1632 };
1633 
1634 struct rtw_cfo_track {
1635     bool is_adjust;
1636     u8 crystal_cap;
1637     s32 cfo_tail[RTW_RF_PATH_MAX];
1638     s32 cfo_cnt[RTW_RF_PATH_MAX];
1639     u32 packet_count;
1640     u32 packet_count_pre;
1641 };
1642 
1643 #define RRSR_INIT_2G 0x15f
1644 #define RRSR_INIT_5G 0x150
1645 
1646 enum rtw_dm_cap {
1647     RTW_DM_CAP_NA,
1648     RTW_DM_CAP_TXGAPK,
1649     RTW_DM_CAP_NUM
1650 };
1651 
1652 struct rtw_dm_info {
1653     u32 cck_fa_cnt;
1654     u32 ofdm_fa_cnt;
1655     u32 total_fa_cnt;
1656     u32 cck_cca_cnt;
1657     u32 ofdm_cca_cnt;
1658     u32 total_cca_cnt;
1659 
1660     u32 cck_ok_cnt;
1661     u32 cck_err_cnt;
1662     u32 ofdm_ok_cnt;
1663     u32 ofdm_err_cnt;
1664     u32 ht_ok_cnt;
1665     u32 ht_err_cnt;
1666     u32 vht_ok_cnt;
1667     u32 vht_err_cnt;
1668 
1669     u8 min_rssi;
1670     u8 pre_min_rssi;
1671     u16 fa_history[4];
1672     u8 igi_history[4];
1673     u8 igi_bitmap;
1674     bool damping;
1675     u8 damping_cnt;
1676     u8 damping_rssi;
1677 
1678     u8 cck_gi_u_bnd;
1679     u8 cck_gi_l_bnd;
1680 
1681     u8 fix_rate;
1682     u8 tx_rate;
1683     u32 rrsr_val_init;
1684     u32 rrsr_mask_min;
1685     u8 thermal_avg[RTW_RF_PATH_MAX];
1686     u8 thermal_meter_k;
1687     u8 thermal_meter_lck;
1688     s8 delta_power_index[RTW_RF_PATH_MAX];
1689     s8 delta_power_index_last[RTW_RF_PATH_MAX];
1690     u8 default_ofdm_index;
1691     bool pwr_trk_triggered;
1692     bool pwr_trk_init_trigger;
1693     struct ewma_thermal avg_thermal[RTW_RF_PATH_MAX];
1694     s8 txagc_remnant_cck;
1695     s8 txagc_remnant_ofdm;
1696 
1697     /* backup dack results for each path and I/Q */
1698     u32 dack_adck[RTW_RF_PATH_MAX];
1699     u16 dack_msbk[RTW_RF_PATH_MAX][2][DACK_MSBK_BACKUP_NUM];
1700     u8 dack_dck[RTW_RF_PATH_MAX][2][DACK_DCK_BACKUP_NUM];
1701 
1702     struct rtw_dpk_info dpk_info;
1703     struct rtw_cfo_track cfo_track;
1704 
1705     /* [bandwidth 0:20M/1:40M][number of path] */
1706     u8 cck_pd_lv[2][RTW_RF_PATH_MAX];
1707     u32 cck_fa_avg;
1708     u8 cck_pd_default;
1709 
1710     /* save the last rx phy status for debug */
1711     s8 rx_snr[RTW_RF_PATH_MAX];
1712     u8 rx_evm_dbm[RTW_RF_PATH_MAX];
1713     s16 cfo_tail[RTW_RF_PATH_MAX];
1714     u8 rssi[RTW_RF_PATH_MAX];
1715     u8 curr_rx_rate;
1716     struct rtw_pkt_count cur_pkt_count;
1717     struct rtw_pkt_count last_pkt_count;
1718     struct ewma_evm ewma_evm[RTW_EVM_NUM];
1719     struct ewma_snr ewma_snr[RTW_SNR_NUM];
1720 
1721     u32 dm_flags; /* enum rtw_dm_cap */
1722     struct rtw_iqk_info iqk;
1723     struct rtw_gapk_info gapk;
1724     bool is_bt_iqk_timeout;
1725 
1726     s8 l2h_th_ini;
1727     enum rtw_edcca_mode edcca_mode;
1728     u8 scan_density;
1729 };
1730 
1731 struct rtw_efuse {
1732     u32 size;
1733     u32 physical_size;
1734     u32 logical_size;
1735     u32 protect_size;
1736 
1737     u8 addr[ETH_ALEN];
1738     u8 channel_plan;
1739     u8 country_code[2];
1740     u8 rf_board_option;
1741     u8 rfe_option;
1742     u8 power_track_type;
1743     u8 thermal_meter[RTW_RF_PATH_MAX];
1744     u8 thermal_meter_k;
1745     u8 crystal_cap;
1746     u8 ant_div_cfg;
1747     u8 ant_div_type;
1748     u8 regd;
1749     u8 afe;
1750 
1751     u8 lna_type_2g;
1752     u8 lna_type_5g;
1753     u8 glna_type;
1754     u8 alna_type;
1755     bool ext_lna_2g;
1756     bool ext_lna_5g;
1757     u8 pa_type_2g;
1758     u8 pa_type_5g;
1759     u8 gpa_type;
1760     u8 apa_type;
1761     bool ext_pa_2g;
1762     bool ext_pa_5g;
1763     u8 tx_bb_swing_setting_2g;
1764     u8 tx_bb_swing_setting_5g;
1765 
1766     bool btcoex;
1767     /* bt share antenna with wifi */
1768     bool share_ant;
1769     u8 bt_setting;
1770 
1771     struct {
1772         u8 hci;
1773         u8 bw;
1774         u8 ptcl;
1775         u8 nss;
1776         u8 ant_num;
1777     } hw_cap;
1778 
1779     struct rtw_txpwr_idx txpwr_idx_table[4];
1780 };
1781 
1782 struct rtw_phy_cond {
1783 #ifdef __LITTLE_ENDIAN
1784     u32 rfe:8;
1785     u32 intf:4;
1786     u32 pkg:4;
1787     u32 plat:4;
1788     u32 intf_rsvd:4;
1789     u32 cut:4;
1790     u32 branch:2;
1791     u32 neg:1;
1792     u32 pos:1;
1793 #else
1794     u32 pos:1;
1795     u32 neg:1;
1796     u32 branch:2;
1797     u32 cut:4;
1798     u32 intf_rsvd:4;
1799     u32 plat:4;
1800     u32 pkg:4;
1801     u32 intf:4;
1802     u32 rfe:8;
1803 #endif
1804     /* for intf:4 */
1805     #define INTF_PCIE   BIT(0)
1806     #define INTF_USB    BIT(1)
1807     #define INTF_SDIO   BIT(2)
1808     /* for branch:2 */
1809     #define BRANCH_IF   0
1810     #define BRANCH_ELIF 1
1811     #define BRANCH_ELSE 2
1812     #define BRANCH_ENDIF    3
1813 };
1814 
1815 struct rtw_fifo_conf {
1816     /* tx fifo information */
1817     u16 rsvd_boundary;
1818     u16 rsvd_pg_num;
1819     u16 rsvd_drv_pg_num;
1820     u16 txff_pg_num;
1821     u16 acq_pg_num;
1822     u16 rsvd_drv_addr;
1823     u16 rsvd_h2c_info_addr;
1824     u16 rsvd_h2c_sta_info_addr;
1825     u16 rsvd_h2cq_addr;
1826     u16 rsvd_cpu_instr_addr;
1827     u16 rsvd_fw_txbuf_addr;
1828     u16 rsvd_csibuf_addr;
1829     const struct rtw_rqpn *rqpn;
1830 };
1831 
1832 struct rtw_fwcd_desc {
1833     u32 size;
1834     u8 *next;
1835     u8 *data;
1836 };
1837 
1838 struct rtw_fwcd_segs {
1839     const u32 *segs;
1840     u8 num;
1841 };
1842 
1843 #define FW_CD_TYPE 0xffff
1844 #define FW_CD_LEN 4
1845 #define FW_CD_VAL 0xaabbccdd
1846 struct rtw_fw_state {
1847     const struct firmware *firmware;
1848     struct rtw_dev *rtwdev;
1849     struct completion completion;
1850     struct rtw_fwcd_desc fwcd_desc;
1851     u16 version;
1852     u8 sub_version;
1853     u8 sub_index;
1854     u16 h2c_version;
1855     u32 feature;
1856 };
1857 
1858 enum rtw_sar_sources {
1859     RTW_SAR_SOURCE_NONE,
1860     RTW_SAR_SOURCE_COMMON,
1861 };
1862 
1863 enum rtw_sar_bands {
1864     RTW_SAR_BAND_0,
1865     RTW_SAR_BAND_1,
1866     /* RTW_SAR_BAND_2, not used now */
1867     RTW_SAR_BAND_3,
1868     RTW_SAR_BAND_4,
1869 
1870     RTW_SAR_BAND_NR,
1871 };
1872 
1873 /* the union is reserved for other knids of SAR sources
1874  * which might not re-use same format with array common.
1875  */
1876 union rtw_sar_cfg {
1877     s8 common[RTW_SAR_BAND_NR];
1878 };
1879 
1880 struct rtw_sar {
1881     enum rtw_sar_sources src;
1882     union rtw_sar_cfg cfg[RTW_RF_PATH_MAX][RTW_RATE_SECTION_MAX];
1883 };
1884 
1885 struct rtw_hal {
1886     u32 rcr;
1887 
1888     u32 chip_version;
1889     u8 cut_version;
1890     u8 mp_chip;
1891     u8 oem_id;
1892     struct rtw_phy_cond phy_cond;
1893 
1894     u8 ps_mode;
1895     u8 current_channel;
1896     u8 current_primary_channel_index;
1897     u8 current_band_width;
1898     u8 current_band_type;
1899 
1900     /* center channel for different available bandwidth,
1901      * val of (bw > current_band_width) is invalid
1902      */
1903     u8 cch_by_bw[RTW_MAX_CHANNEL_WIDTH + 1];
1904 
1905     u8 sec_ch_offset;
1906     u8 rf_type;
1907     u8 rf_path_num;
1908     u8 rf_phy_num;
1909     u32 antenna_tx;
1910     u32 antenna_rx;
1911     u8 bfee_sts_cap;
1912     bool txrx_1ss;
1913 
1914     /* protect tx power section */
1915     struct mutex tx_power_mutex;
1916     s8 tx_pwr_by_rate_offset_2g[RTW_RF_PATH_MAX]
1917                    [DESC_RATE_MAX];
1918     s8 tx_pwr_by_rate_offset_5g[RTW_RF_PATH_MAX]
1919                    [DESC_RATE_MAX];
1920     s8 tx_pwr_by_rate_base_2g[RTW_RF_PATH_MAX]
1921                  [RTW_RATE_SECTION_MAX];
1922     s8 tx_pwr_by_rate_base_5g[RTW_RF_PATH_MAX]
1923                  [RTW_RATE_SECTION_MAX];
1924     s8 tx_pwr_limit_2g[RTW_REGD_MAX]
1925               [RTW_CHANNEL_WIDTH_MAX]
1926               [RTW_RATE_SECTION_MAX]
1927               [RTW_MAX_CHANNEL_NUM_2G];
1928     s8 tx_pwr_limit_5g[RTW_REGD_MAX]
1929               [RTW_CHANNEL_WIDTH_MAX]
1930               [RTW_RATE_SECTION_MAX]
1931               [RTW_MAX_CHANNEL_NUM_5G];
1932     s8 tx_pwr_tbl[RTW_RF_PATH_MAX]
1933              [DESC_RATE_MAX];
1934 
1935     enum rtw_sar_bands sar_band;
1936     struct rtw_sar sar;
1937 
1938     /* for 8821c set channel */
1939     u32 ch_param[3];
1940 };
1941 
1942 struct rtw_path_div {
1943     enum rtw_bb_path current_tx_path;
1944     u32 path_a_sum;
1945     u32 path_b_sum;
1946     u16 path_a_cnt;
1947     u16 path_b_cnt;
1948 };
1949 
1950 struct rtw_chan_info {
1951     int pri_ch_idx;
1952     int action_id;
1953     int bw;
1954     u8 extra_info;
1955     u8 channel;
1956     u16 timeout;
1957 };
1958 
1959 struct rtw_chan_list {
1960     u32 buf_size;
1961     u32 ch_num;
1962     u32 size;
1963     u16 addr;
1964 };
1965 
1966 struct rtw_hw_scan_info {
1967     struct ieee80211_vif *scanning_vif;
1968     u8 probe_pg_size;
1969     u8 op_pri_ch_idx;
1970     u8 op_chan;
1971     u8 op_bw;
1972 };
1973 
1974 struct rtw_dev {
1975     struct ieee80211_hw *hw;
1976     struct device *dev;
1977 
1978     struct rtw_hci hci;
1979 
1980     struct rtw_hw_scan_info scan_info;
1981     struct rtw_chip_info *chip;
1982     struct rtw_hal hal;
1983     struct rtw_fifo_conf fifo;
1984     struct rtw_fw_state fw;
1985     struct rtw_efuse efuse;
1986     struct rtw_sec_desc sec;
1987     struct rtw_traffic_stats stats;
1988     struct rtw_regd regd;
1989     struct rtw_bf_info bf_info;
1990 
1991     struct rtw_dm_info dm_info;
1992     struct rtw_coex coex;
1993 
1994     /* ensures exclusive access from mac80211 callbacks */
1995     struct mutex mutex;
1996 
1997     /* read/write rf register */
1998     spinlock_t rf_lock;
1999 
2000     /* watch dog every 2 sec */
2001     struct delayed_work watch_dog_work;
2002     u32 watch_dog_cnt;
2003 
2004     struct list_head rsvd_page_list;
2005 
2006     /* c2h cmd queue & handler work */
2007     struct sk_buff_head c2h_queue;
2008     struct work_struct c2h_work;
2009     struct work_struct ips_work;
2010     struct work_struct fw_recovery_work;
2011     struct work_struct update_beacon_work;
2012 
2013     /* used to protect txqs list */
2014     spinlock_t txq_lock;
2015     struct list_head txqs;
2016     struct workqueue_struct *tx_wq;
2017     struct work_struct tx_work;
2018     struct work_struct ba_work;
2019 
2020     struct rtw_tx_report tx_report;
2021 
2022     struct {
2023         /* incicate the mail box to use with fw */
2024         u8 last_box_num;
2025         /* protect to send h2c to fw */
2026         spinlock_t lock;
2027         u32 seq;
2028     } h2c;
2029 
2030     /* lps power state & handler work */
2031     struct rtw_lps_conf lps_conf;
2032     bool ps_enabled;
2033     bool beacon_loss;
2034     struct completion lps_leave_check;
2035 
2036     struct dentry *debugfs;
2037 
2038     u8 sta_cnt;
2039     u32 rts_threshold;
2040 
2041     DECLARE_BITMAP(mac_id_map, RTW_MAX_MAC_ID_NUM);
2042     DECLARE_BITMAP(flags, NUM_OF_RTW_FLAGS);
2043 
2044     u8 mp_mode;
2045     struct rtw_path_div dm_path_div;
2046 
2047     struct rtw_fw_state wow_fw;
2048     struct rtw_wow_param wow;
2049 
2050     bool need_rfk;
2051     struct completion fw_scan_density;
2052 
2053     /* hci related data, must be last */
2054     u8 priv[] __aligned(sizeof(void *));
2055 };
2056 
2057 #include "hci.h"
2058 
2059 static inline bool rtw_is_assoc(struct rtw_dev *rtwdev)
2060 {
2061     return !!rtwdev->sta_cnt;
2062 }
2063 
2064 static inline struct ieee80211_txq *rtwtxq_to_txq(struct rtw_txq *rtwtxq)
2065 {
2066     void *p = rtwtxq;
2067 
2068     return container_of(p, struct ieee80211_txq, drv_priv);
2069 }
2070 
2071 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw_vif *rtwvif)
2072 {
2073     void *p = rtwvif;
2074 
2075     return container_of(p, struct ieee80211_vif, drv_priv);
2076 }
2077 
2078 static inline bool rtw_ssid_equal(struct cfg80211_ssid *a,
2079                   struct cfg80211_ssid *b)
2080 {
2081     if (!a || !b || a->ssid_len != b->ssid_len)
2082         return false;
2083 
2084     if (memcmp(a->ssid, b->ssid, a->ssid_len))
2085         return false;
2086 
2087     return true;
2088 }
2089 
2090 static inline void rtw_chip_efuse_grant_on(struct rtw_dev *rtwdev)
2091 {
2092     if (rtwdev->chip->ops->efuse_grant)
2093         rtwdev->chip->ops->efuse_grant(rtwdev, true);
2094 }
2095 
2096 static inline void rtw_chip_efuse_grant_off(struct rtw_dev *rtwdev)
2097 {
2098     if (rtwdev->chip->ops->efuse_grant)
2099         rtwdev->chip->ops->efuse_grant(rtwdev, false);
2100 }
2101 
2102 static inline bool rtw_chip_wcpu_11n(struct rtw_dev *rtwdev)
2103 {
2104     return rtwdev->chip->wlan_cpu == RTW_WCPU_11N;
2105 }
2106 
2107 static inline bool rtw_chip_wcpu_11ac(struct rtw_dev *rtwdev)
2108 {
2109     return rtwdev->chip->wlan_cpu == RTW_WCPU_11AC;
2110 }
2111 
2112 static inline bool rtw_chip_has_rx_ldpc(struct rtw_dev *rtwdev)
2113 {
2114     return rtwdev->chip->rx_ldpc;
2115 }
2116 
2117 static inline bool rtw_chip_has_tx_stbc(struct rtw_dev *rtwdev)
2118 {
2119     return rtwdev->chip->tx_stbc;
2120 }
2121 
2122 static inline void rtw_release_macid(struct rtw_dev *rtwdev, u8 mac_id)
2123 {
2124     clear_bit(mac_id, rtwdev->mac_id_map);
2125 }
2126 
2127 static inline int rtw_chip_dump_fw_crash(struct rtw_dev *rtwdev)
2128 {
2129     if (rtwdev->chip->ops->dump_fw_crash)
2130         return rtwdev->chip->ops->dump_fw_crash(rtwdev);
2131 
2132     return 0;
2133 }
2134 
2135 void rtw_set_rx_freq_band(struct rtw_rx_pkt_stat *pkt_stat, u8 channel);
2136 void rtw_set_dtim_period(struct rtw_dev *rtwdev, int dtim_period);
2137 void rtw_get_channel_params(struct cfg80211_chan_def *chandef,
2138                 struct rtw_channel_params *ch_param);
2139 bool check_hw_ready(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 target);
2140 bool ltecoex_read_reg(struct rtw_dev *rtwdev, u16 offset, u32 *val);
2141 bool ltecoex_reg_write(struct rtw_dev *rtwdev, u16 offset, u32 value);
2142 void rtw_restore_reg(struct rtw_dev *rtwdev,
2143              struct rtw_backup_info *bckp, u32 num);
2144 void rtw_desc_to_mcsrate(u16 rate, u8 *mcs, u8 *nss);
2145 void rtw_set_channel(struct rtw_dev *rtwdev);
2146 void rtw_chip_prepare_tx(struct rtw_dev *rtwdev);
2147 void rtw_vif_port_config(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif,
2148              u32 config);
2149 void rtw_tx_report_purge_timer(struct timer_list *t);
2150 void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si,
2151              bool reset_ra_mask);
2152 void rtw_core_scan_start(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif,
2153              const u8 *mac_addr, bool hw_scan);
2154 void rtw_core_scan_complete(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
2155                 bool hw_scan);
2156 int rtw_core_start(struct rtw_dev *rtwdev);
2157 void rtw_core_stop(struct rtw_dev *rtwdev);
2158 int rtw_chip_info_setup(struct rtw_dev *rtwdev);
2159 int rtw_core_init(struct rtw_dev *rtwdev);
2160 void rtw_core_deinit(struct rtw_dev *rtwdev);
2161 int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw);
2162 void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw);
2163 u16 rtw_desc_to_bitrate(u8 desc_rate);
2164 void rtw_vif_assoc_changed(struct rtw_vif *rtwvif,
2165                struct ieee80211_bss_conf *conf);
2166 int rtw_sta_add(struct rtw_dev *rtwdev, struct ieee80211_sta *sta,
2167         struct ieee80211_vif *vif);
2168 void rtw_sta_remove(struct rtw_dev *rtwdev, struct ieee80211_sta *sta,
2169             bool fw_exist);
2170 void rtw_fw_recovery(struct rtw_dev *rtwdev);
2171 void rtw_core_fw_scan_notify(struct rtw_dev *rtwdev, bool start);
2172 int rtw_dump_fw(struct rtw_dev *rtwdev, const u32 ocp_src, u32 size,
2173         u32 fwcd_item);
2174 int rtw_dump_reg(struct rtw_dev *rtwdev, const u32 addr, const u32 size);
2175 void rtw_set_txrx_1ss(struct rtw_dev *rtwdev, bool config_1ss);
2176 #endif
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