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0001 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
0002 /* Copyright(c) 2018-2019  Realtek Corporation
0003  */
0004 
0005 #include <linux/devcoredump.h>
0006 
0007 #include "main.h"
0008 #include "regd.h"
0009 #include "fw.h"
0010 #include "ps.h"
0011 #include "sec.h"
0012 #include "mac.h"
0013 #include "coex.h"
0014 #include "phy.h"
0015 #include "reg.h"
0016 #include "efuse.h"
0017 #include "tx.h"
0018 #include "debug.h"
0019 #include "bf.h"
0020 #include "sar.h"
0021 
0022 bool rtw_disable_lps_deep_mode;
0023 EXPORT_SYMBOL(rtw_disable_lps_deep_mode);
0024 bool rtw_bf_support = true;
0025 unsigned int rtw_debug_mask;
0026 EXPORT_SYMBOL(rtw_debug_mask);
0027 /* EDCCA is enabled during normal behavior. For debugging purpose in
0028  * a noisy environment, it can be disabled via edcca debugfs. Because
0029  * all rtw88 devices will probably be affected if environment is noisy,
0030  * rtw_edcca_enabled is just declared by driver instead of by device.
0031  * So, turning it off will take effect for all rtw88 devices before
0032  * there is a tough reason to maintain rtw_edcca_enabled by device.
0033  */
0034 bool rtw_edcca_enabled = true;
0035 
0036 module_param_named(disable_lps_deep, rtw_disable_lps_deep_mode, bool, 0644);
0037 module_param_named(support_bf, rtw_bf_support, bool, 0644);
0038 module_param_named(debug_mask, rtw_debug_mask, uint, 0644);
0039 
0040 MODULE_PARM_DESC(disable_lps_deep, "Set Y to disable Deep PS");
0041 MODULE_PARM_DESC(support_bf, "Set Y to enable beamformee support");
0042 MODULE_PARM_DESC(debug_mask, "Debugging mask");
0043 
0044 static struct ieee80211_channel rtw_channeltable_2g[] = {
0045     {.center_freq = 2412, .hw_value = 1,},
0046     {.center_freq = 2417, .hw_value = 2,},
0047     {.center_freq = 2422, .hw_value = 3,},
0048     {.center_freq = 2427, .hw_value = 4,},
0049     {.center_freq = 2432, .hw_value = 5,},
0050     {.center_freq = 2437, .hw_value = 6,},
0051     {.center_freq = 2442, .hw_value = 7,},
0052     {.center_freq = 2447, .hw_value = 8,},
0053     {.center_freq = 2452, .hw_value = 9,},
0054     {.center_freq = 2457, .hw_value = 10,},
0055     {.center_freq = 2462, .hw_value = 11,},
0056     {.center_freq = 2467, .hw_value = 12,},
0057     {.center_freq = 2472, .hw_value = 13,},
0058     {.center_freq = 2484, .hw_value = 14,},
0059 };
0060 
0061 static struct ieee80211_channel rtw_channeltable_5g[] = {
0062     {.center_freq = 5180, .hw_value = 36,},
0063     {.center_freq = 5200, .hw_value = 40,},
0064     {.center_freq = 5220, .hw_value = 44,},
0065     {.center_freq = 5240, .hw_value = 48,},
0066     {.center_freq = 5260, .hw_value = 52,},
0067     {.center_freq = 5280, .hw_value = 56,},
0068     {.center_freq = 5300, .hw_value = 60,},
0069     {.center_freq = 5320, .hw_value = 64,},
0070     {.center_freq = 5500, .hw_value = 100,},
0071     {.center_freq = 5520, .hw_value = 104,},
0072     {.center_freq = 5540, .hw_value = 108,},
0073     {.center_freq = 5560, .hw_value = 112,},
0074     {.center_freq = 5580, .hw_value = 116,},
0075     {.center_freq = 5600, .hw_value = 120,},
0076     {.center_freq = 5620, .hw_value = 124,},
0077     {.center_freq = 5640, .hw_value = 128,},
0078     {.center_freq = 5660, .hw_value = 132,},
0079     {.center_freq = 5680, .hw_value = 136,},
0080     {.center_freq = 5700, .hw_value = 140,},
0081     {.center_freq = 5720, .hw_value = 144,},
0082     {.center_freq = 5745, .hw_value = 149,},
0083     {.center_freq = 5765, .hw_value = 153,},
0084     {.center_freq = 5785, .hw_value = 157,},
0085     {.center_freq = 5805, .hw_value = 161,},
0086     {.center_freq = 5825, .hw_value = 165,
0087      .flags = IEEE80211_CHAN_NO_HT40MINUS},
0088 };
0089 
0090 static struct ieee80211_rate rtw_ratetable[] = {
0091     {.bitrate = 10, .hw_value = 0x00,},
0092     {.bitrate = 20, .hw_value = 0x01,},
0093     {.bitrate = 55, .hw_value = 0x02,},
0094     {.bitrate = 110, .hw_value = 0x03,},
0095     {.bitrate = 60, .hw_value = 0x04,},
0096     {.bitrate = 90, .hw_value = 0x05,},
0097     {.bitrate = 120, .hw_value = 0x06,},
0098     {.bitrate = 180, .hw_value = 0x07,},
0099     {.bitrate = 240, .hw_value = 0x08,},
0100     {.bitrate = 360, .hw_value = 0x09,},
0101     {.bitrate = 480, .hw_value = 0x0a,},
0102     {.bitrate = 540, .hw_value = 0x0b,},
0103 };
0104 
0105 u16 rtw_desc_to_bitrate(u8 desc_rate)
0106 {
0107     struct ieee80211_rate rate;
0108 
0109     if (WARN(desc_rate >= ARRAY_SIZE(rtw_ratetable), "invalid desc rate\n"))
0110         return 0;
0111 
0112     rate = rtw_ratetable[desc_rate];
0113 
0114     return rate.bitrate;
0115 }
0116 
0117 static struct ieee80211_supported_band rtw_band_2ghz = {
0118     .band = NL80211_BAND_2GHZ,
0119 
0120     .channels = rtw_channeltable_2g,
0121     .n_channels = ARRAY_SIZE(rtw_channeltable_2g),
0122 
0123     .bitrates = rtw_ratetable,
0124     .n_bitrates = ARRAY_SIZE(rtw_ratetable),
0125 
0126     .ht_cap = {0},
0127     .vht_cap = {0},
0128 };
0129 
0130 static struct ieee80211_supported_band rtw_band_5ghz = {
0131     .band = NL80211_BAND_5GHZ,
0132 
0133     .channels = rtw_channeltable_5g,
0134     .n_channels = ARRAY_SIZE(rtw_channeltable_5g),
0135 
0136     /* 5G has no CCK rates */
0137     .bitrates = rtw_ratetable + 4,
0138     .n_bitrates = ARRAY_SIZE(rtw_ratetable) - 4,
0139 
0140     .ht_cap = {0},
0141     .vht_cap = {0},
0142 };
0143 
0144 struct rtw_watch_dog_iter_data {
0145     struct rtw_dev *rtwdev;
0146     struct rtw_vif *rtwvif;
0147 };
0148 
0149 static void rtw_dynamic_csi_rate(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif)
0150 {
0151     struct rtw_bf_info *bf_info = &rtwdev->bf_info;
0152     u8 fix_rate_enable = 0;
0153     u8 new_csi_rate_idx;
0154 
0155     if (rtwvif->bfee.role != RTW_BFEE_SU &&
0156         rtwvif->bfee.role != RTW_BFEE_MU)
0157         return;
0158 
0159     rtw_chip_cfg_csi_rate(rtwdev, rtwdev->dm_info.min_rssi,
0160                   bf_info->cur_csi_rpt_rate,
0161                   fix_rate_enable, &new_csi_rate_idx);
0162 
0163     if (new_csi_rate_idx != bf_info->cur_csi_rpt_rate)
0164         bf_info->cur_csi_rpt_rate = new_csi_rate_idx;
0165 }
0166 
0167 static void rtw_vif_watch_dog_iter(void *data, u8 *mac,
0168                    struct ieee80211_vif *vif)
0169 {
0170     struct rtw_watch_dog_iter_data *iter_data = data;
0171     struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv;
0172 
0173     if (vif->type == NL80211_IFTYPE_STATION)
0174         if (vif->cfg.assoc)
0175             iter_data->rtwvif = rtwvif;
0176 
0177     rtw_dynamic_csi_rate(iter_data->rtwdev, rtwvif);
0178 
0179     rtwvif->stats.tx_unicast = 0;
0180     rtwvif->stats.rx_unicast = 0;
0181     rtwvif->stats.tx_cnt = 0;
0182     rtwvif->stats.rx_cnt = 0;
0183 }
0184 
0185 /* process TX/RX statistics periodically for hardware,
0186  * the information helps hardware to enhance performance
0187  */
0188 static void rtw_watch_dog_work(struct work_struct *work)
0189 {
0190     struct rtw_dev *rtwdev = container_of(work, struct rtw_dev,
0191                           watch_dog_work.work);
0192     struct rtw_traffic_stats *stats = &rtwdev->stats;
0193     struct rtw_watch_dog_iter_data data = {};
0194     bool busy_traffic = test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags);
0195     bool ps_active;
0196 
0197     mutex_lock(&rtwdev->mutex);
0198 
0199     if (!test_bit(RTW_FLAG_RUNNING, rtwdev->flags))
0200         goto unlock;
0201 
0202     ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->watch_dog_work,
0203                      RTW_WATCH_DOG_DELAY_TIME);
0204 
0205     if (rtwdev->stats.tx_cnt > 100 || rtwdev->stats.rx_cnt > 100)
0206         set_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags);
0207     else
0208         clear_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags);
0209 
0210     rtw_coex_wl_status_check(rtwdev);
0211     rtw_coex_query_bt_hid_list(rtwdev);
0212 
0213     if (busy_traffic != test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags))
0214         rtw_coex_wl_status_change_notify(rtwdev, 0);
0215 
0216     if (stats->tx_cnt > RTW_LPS_THRESHOLD ||
0217         stats->rx_cnt > RTW_LPS_THRESHOLD)
0218         ps_active = true;
0219     else
0220         ps_active = false;
0221 
0222     ewma_tp_add(&stats->tx_ewma_tp,
0223             (u32)(stats->tx_unicast >> RTW_TP_SHIFT));
0224     ewma_tp_add(&stats->rx_ewma_tp,
0225             (u32)(stats->rx_unicast >> RTW_TP_SHIFT));
0226     stats->tx_throughput = ewma_tp_read(&stats->tx_ewma_tp);
0227     stats->rx_throughput = ewma_tp_read(&stats->rx_ewma_tp);
0228 
0229     /* reset tx/rx statictics */
0230     stats->tx_unicast = 0;
0231     stats->rx_unicast = 0;
0232     stats->tx_cnt = 0;
0233     stats->rx_cnt = 0;
0234 
0235     if (test_bit(RTW_FLAG_SCANNING, rtwdev->flags))
0236         goto unlock;
0237 
0238     /* make sure BB/RF is working for dynamic mech */
0239     rtw_leave_lps(rtwdev);
0240 
0241     rtw_phy_dynamic_mechanism(rtwdev);
0242 
0243     data.rtwdev = rtwdev;
0244     /* use atomic version to avoid taking local->iflist_mtx mutex */
0245     rtw_iterate_vifs_atomic(rtwdev, rtw_vif_watch_dog_iter, &data);
0246 
0247     /* fw supports only one station associated to enter lps, if there are
0248      * more than two stations associated to the AP, then we can not enter
0249      * lps, because fw does not handle the overlapped beacon interval
0250      *
0251      * mac80211 should iterate vifs and determine if driver can enter
0252      * ps by passing IEEE80211_CONF_PS to us, all we need to do is to
0253      * get that vif and check if device is having traffic more than the
0254      * threshold.
0255      */
0256     if (rtwdev->ps_enabled && data.rtwvif && !ps_active &&
0257         !rtwdev->beacon_loss)
0258         rtw_enter_lps(rtwdev, data.rtwvif->port);
0259 
0260     rtwdev->watch_dog_cnt++;
0261 
0262 unlock:
0263     mutex_unlock(&rtwdev->mutex);
0264 }
0265 
0266 static void rtw_c2h_work(struct work_struct *work)
0267 {
0268     struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, c2h_work);
0269     struct sk_buff *skb, *tmp;
0270 
0271     skb_queue_walk_safe(&rtwdev->c2h_queue, skb, tmp) {
0272         skb_unlink(skb, &rtwdev->c2h_queue);
0273         rtw_fw_c2h_cmd_handle(rtwdev, skb);
0274         dev_kfree_skb_any(skb);
0275     }
0276 }
0277 
0278 static void rtw_ips_work(struct work_struct *work)
0279 {
0280     struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, ips_work);
0281 
0282     mutex_lock(&rtwdev->mutex);
0283     if (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE)
0284         rtw_enter_ips(rtwdev);
0285     mutex_unlock(&rtwdev->mutex);
0286 }
0287 
0288 static u8 rtw_acquire_macid(struct rtw_dev *rtwdev)
0289 {
0290     unsigned long mac_id;
0291 
0292     mac_id = find_first_zero_bit(rtwdev->mac_id_map, RTW_MAX_MAC_ID_NUM);
0293     if (mac_id < RTW_MAX_MAC_ID_NUM)
0294         set_bit(mac_id, rtwdev->mac_id_map);
0295 
0296     return mac_id;
0297 }
0298 
0299 int rtw_sta_add(struct rtw_dev *rtwdev, struct ieee80211_sta *sta,
0300         struct ieee80211_vif *vif)
0301 {
0302     struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv;
0303     int i;
0304 
0305     si->mac_id = rtw_acquire_macid(rtwdev);
0306     if (si->mac_id >= RTW_MAX_MAC_ID_NUM)
0307         return -ENOSPC;
0308 
0309     si->sta = sta;
0310     si->vif = vif;
0311     si->init_ra_lv = 1;
0312     ewma_rssi_init(&si->avg_rssi);
0313     for (i = 0; i < ARRAY_SIZE(sta->txq); i++)
0314         rtw_txq_init(rtwdev, sta->txq[i]);
0315 
0316     rtw_update_sta_info(rtwdev, si, true);
0317     rtw_fw_media_status_report(rtwdev, si->mac_id, true);
0318 
0319     rtwdev->sta_cnt++;
0320     rtwdev->beacon_loss = false;
0321     rtw_dbg(rtwdev, RTW_DBG_STATE, "sta %pM joined with macid %d\n",
0322         sta->addr, si->mac_id);
0323 
0324     return 0;
0325 }
0326 
0327 void rtw_sta_remove(struct rtw_dev *rtwdev, struct ieee80211_sta *sta,
0328             bool fw_exist)
0329 {
0330     struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv;
0331     int i;
0332 
0333     rtw_release_macid(rtwdev, si->mac_id);
0334     if (fw_exist)
0335         rtw_fw_media_status_report(rtwdev, si->mac_id, false);
0336 
0337     for (i = 0; i < ARRAY_SIZE(sta->txq); i++)
0338         rtw_txq_cleanup(rtwdev, sta->txq[i]);
0339 
0340     kfree(si->mask);
0341 
0342     rtwdev->sta_cnt--;
0343     rtw_dbg(rtwdev, RTW_DBG_STATE, "sta %pM with macid %d left\n",
0344         sta->addr, si->mac_id);
0345 }
0346 
0347 struct rtw_fwcd_hdr {
0348     u32 item;
0349     u32 size;
0350     u32 padding1;
0351     u32 padding2;
0352 } __packed;
0353 
0354 static int rtw_fwcd_prep(struct rtw_dev *rtwdev)
0355 {
0356     struct rtw_chip_info *chip = rtwdev->chip;
0357     struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc;
0358     const struct rtw_fwcd_segs *segs = chip->fwcd_segs;
0359     u32 prep_size = chip->fw_rxff_size + sizeof(struct rtw_fwcd_hdr);
0360     u8 i;
0361 
0362     if (segs) {
0363         prep_size += segs->num * sizeof(struct rtw_fwcd_hdr);
0364 
0365         for (i = 0; i < segs->num; i++)
0366             prep_size += segs->segs[i];
0367     }
0368 
0369     desc->data = vmalloc(prep_size);
0370     if (!desc->data)
0371         return -ENOMEM;
0372 
0373     desc->size = prep_size;
0374     desc->next = desc->data;
0375 
0376     return 0;
0377 }
0378 
0379 static u8 *rtw_fwcd_next(struct rtw_dev *rtwdev, u32 item, u32 size)
0380 {
0381     struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc;
0382     struct rtw_fwcd_hdr *hdr;
0383     u8 *next;
0384 
0385     if (!desc->data) {
0386         rtw_dbg(rtwdev, RTW_DBG_FW, "fwcd isn't prepared successfully\n");
0387         return NULL;
0388     }
0389 
0390     next = desc->next + sizeof(struct rtw_fwcd_hdr);
0391     if (next - desc->data + size > desc->size) {
0392         rtw_dbg(rtwdev, RTW_DBG_FW, "fwcd isn't prepared enough\n");
0393         return NULL;
0394     }
0395 
0396     hdr = (struct rtw_fwcd_hdr *)(desc->next);
0397     hdr->item = item;
0398     hdr->size = size;
0399     hdr->padding1 = 0x01234567;
0400     hdr->padding2 = 0x89abcdef;
0401     desc->next = next + size;
0402 
0403     return next;
0404 }
0405 
0406 static void rtw_fwcd_dump(struct rtw_dev *rtwdev)
0407 {
0408     struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc;
0409 
0410     rtw_dbg(rtwdev, RTW_DBG_FW, "dump fwcd\n");
0411 
0412     /* Data will be freed after lifetime of device coredump. After calling
0413      * dev_coredump, data is supposed to be handled by the device coredump
0414      * framework. Note that a new dump will be discarded if a previous one
0415      * hasn't been released yet.
0416      */
0417     dev_coredumpv(rtwdev->dev, desc->data, desc->size, GFP_KERNEL);
0418 }
0419 
0420 static void rtw_fwcd_free(struct rtw_dev *rtwdev, bool free_self)
0421 {
0422     struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc;
0423 
0424     if (free_self) {
0425         rtw_dbg(rtwdev, RTW_DBG_FW, "free fwcd by self\n");
0426         vfree(desc->data);
0427     }
0428 
0429     desc->data = NULL;
0430     desc->next = NULL;
0431 }
0432 
0433 static int rtw_fw_dump_crash_log(struct rtw_dev *rtwdev)
0434 {
0435     u32 size = rtwdev->chip->fw_rxff_size;
0436     u32 *buf;
0437     u8 seq;
0438 
0439     buf = (u32 *)rtw_fwcd_next(rtwdev, RTW_FWCD_TLV, size);
0440     if (!buf)
0441         return -ENOMEM;
0442 
0443     if (rtw_fw_dump_fifo(rtwdev, RTW_FW_FIFO_SEL_RXBUF_FW, 0, size, buf)) {
0444         rtw_dbg(rtwdev, RTW_DBG_FW, "dump fw fifo fail\n");
0445         return -EINVAL;
0446     }
0447 
0448     if (GET_FW_DUMP_LEN(buf) == 0) {
0449         rtw_dbg(rtwdev, RTW_DBG_FW, "fw crash dump's length is 0\n");
0450         return -EINVAL;
0451     }
0452 
0453     seq = GET_FW_DUMP_SEQ(buf);
0454     if (seq > 0) {
0455         rtw_dbg(rtwdev, RTW_DBG_FW,
0456             "fw crash dump's seq is wrong: %d\n", seq);
0457         return -EINVAL;
0458     }
0459 
0460     return 0;
0461 }
0462 
0463 int rtw_dump_fw(struct rtw_dev *rtwdev, const u32 ocp_src, u32 size,
0464         u32 fwcd_item)
0465 {
0466     u32 rxff = rtwdev->chip->fw_rxff_size;
0467     u32 dump_size, done_size = 0;
0468     u8 *buf;
0469     int ret;
0470 
0471     buf = rtw_fwcd_next(rtwdev, fwcd_item, size);
0472     if (!buf)
0473         return -ENOMEM;
0474 
0475     while (size) {
0476         dump_size = size > rxff ? rxff : size;
0477 
0478         ret = rtw_ddma_to_fw_fifo(rtwdev, ocp_src + done_size,
0479                       dump_size);
0480         if (ret) {
0481             rtw_err(rtwdev,
0482                 "ddma fw 0x%x [+0x%x] to fw fifo fail\n",
0483                 ocp_src, done_size);
0484             return ret;
0485         }
0486 
0487         ret = rtw_fw_dump_fifo(rtwdev, RTW_FW_FIFO_SEL_RXBUF_FW, 0,
0488                        dump_size, (u32 *)(buf + done_size));
0489         if (ret) {
0490             rtw_err(rtwdev,
0491                 "dump fw 0x%x [+0x%x] from fw fifo fail\n",
0492                 ocp_src, done_size);
0493             return ret;
0494         }
0495 
0496         size -= dump_size;
0497         done_size += dump_size;
0498     }
0499 
0500     return 0;
0501 }
0502 EXPORT_SYMBOL(rtw_dump_fw);
0503 
0504 int rtw_dump_reg(struct rtw_dev *rtwdev, const u32 addr, const u32 size)
0505 {
0506     u8 *buf;
0507     u32 i;
0508 
0509     if (addr & 0x3) {
0510         WARN(1, "should be 4-byte aligned, addr = 0x%08x\n", addr);
0511         return -EINVAL;
0512     }
0513 
0514     buf = rtw_fwcd_next(rtwdev, RTW_FWCD_REG, size);
0515     if (!buf)
0516         return -ENOMEM;
0517 
0518     for (i = 0; i < size; i += 4)
0519         *(u32 *)(buf + i) = rtw_read32(rtwdev, addr + i);
0520 
0521     return 0;
0522 }
0523 EXPORT_SYMBOL(rtw_dump_reg);
0524 
0525 void rtw_vif_assoc_changed(struct rtw_vif *rtwvif,
0526                struct ieee80211_bss_conf *conf)
0527 {
0528     struct ieee80211_vif *vif = NULL;
0529 
0530     if (conf)
0531         vif = container_of(conf, struct ieee80211_vif, bss_conf);
0532 
0533     if (conf && vif->cfg.assoc) {
0534         rtwvif->aid = vif->cfg.aid;
0535         rtwvif->net_type = RTW_NET_MGD_LINKED;
0536     } else {
0537         rtwvif->aid = 0;
0538         rtwvif->net_type = RTW_NET_NO_LINK;
0539     }
0540 }
0541 
0542 static void rtw_reset_key_iter(struct ieee80211_hw *hw,
0543                    struct ieee80211_vif *vif,
0544                    struct ieee80211_sta *sta,
0545                    struct ieee80211_key_conf *key,
0546                    void *data)
0547 {
0548     struct rtw_dev *rtwdev = (struct rtw_dev *)data;
0549     struct rtw_sec_desc *sec = &rtwdev->sec;
0550 
0551     rtw_sec_clear_cam(rtwdev, sec, key->hw_key_idx);
0552 }
0553 
0554 static void rtw_reset_sta_iter(void *data, struct ieee80211_sta *sta)
0555 {
0556     struct rtw_dev *rtwdev = (struct rtw_dev *)data;
0557 
0558     if (rtwdev->sta_cnt == 0) {
0559         rtw_warn(rtwdev, "sta count before reset should not be 0\n");
0560         return;
0561     }
0562     rtw_sta_remove(rtwdev, sta, false);
0563 }
0564 
0565 static void rtw_reset_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
0566 {
0567     struct rtw_dev *rtwdev = (struct rtw_dev *)data;
0568     struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv;
0569 
0570     rtw_bf_disassoc(rtwdev, vif, NULL);
0571     rtw_vif_assoc_changed(rtwvif, NULL);
0572     rtw_txq_cleanup(rtwdev, vif->txq);
0573 }
0574 
0575 void rtw_fw_recovery(struct rtw_dev *rtwdev)
0576 {
0577     if (!test_bit(RTW_FLAG_RESTARTING, rtwdev->flags))
0578         ieee80211_queue_work(rtwdev->hw, &rtwdev->fw_recovery_work);
0579 }
0580 
0581 static void __fw_recovery_work(struct rtw_dev *rtwdev)
0582 {
0583     int ret = 0;
0584 
0585     set_bit(RTW_FLAG_RESTARTING, rtwdev->flags);
0586     clear_bit(RTW_FLAG_RESTART_TRIGGERING, rtwdev->flags);
0587 
0588     ret = rtw_fwcd_prep(rtwdev);
0589     if (ret)
0590         goto free;
0591     ret = rtw_fw_dump_crash_log(rtwdev);
0592     if (ret)
0593         goto free;
0594     ret = rtw_chip_dump_fw_crash(rtwdev);
0595     if (ret)
0596         goto free;
0597 
0598     rtw_fwcd_dump(rtwdev);
0599 free:
0600     rtw_fwcd_free(rtwdev, !!ret);
0601     rtw_write8(rtwdev, REG_MCU_TST_CFG, 0);
0602 
0603     WARN(1, "firmware crash, start reset and recover\n");
0604 
0605     rcu_read_lock();
0606     rtw_iterate_keys_rcu(rtwdev, NULL, rtw_reset_key_iter, rtwdev);
0607     rcu_read_unlock();
0608     rtw_iterate_stas_atomic(rtwdev, rtw_reset_sta_iter, rtwdev);
0609     rtw_iterate_vifs_atomic(rtwdev, rtw_reset_vif_iter, rtwdev);
0610     rtw_enter_ips(rtwdev);
0611 }
0612 
0613 static void rtw_fw_recovery_work(struct work_struct *work)
0614 {
0615     struct rtw_dev *rtwdev = container_of(work, struct rtw_dev,
0616                           fw_recovery_work);
0617 
0618     mutex_lock(&rtwdev->mutex);
0619     __fw_recovery_work(rtwdev);
0620     mutex_unlock(&rtwdev->mutex);
0621 
0622     ieee80211_restart_hw(rtwdev->hw);
0623 }
0624 
0625 struct rtw_txq_ba_iter_data {
0626 };
0627 
0628 static void rtw_txq_ba_iter(void *data, struct ieee80211_sta *sta)
0629 {
0630     struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv;
0631     int ret;
0632     u8 tid;
0633 
0634     tid = find_first_bit(si->tid_ba, IEEE80211_NUM_TIDS);
0635     while (tid != IEEE80211_NUM_TIDS) {
0636         clear_bit(tid, si->tid_ba);
0637         ret = ieee80211_start_tx_ba_session(sta, tid, 0);
0638         if (ret == -EINVAL) {
0639             struct ieee80211_txq *txq;
0640             struct rtw_txq *rtwtxq;
0641 
0642             txq = sta->txq[tid];
0643             rtwtxq = (struct rtw_txq *)txq->drv_priv;
0644             set_bit(RTW_TXQ_BLOCK_BA, &rtwtxq->flags);
0645         }
0646 
0647         tid = find_first_bit(si->tid_ba, IEEE80211_NUM_TIDS);
0648     }
0649 }
0650 
0651 static void rtw_txq_ba_work(struct work_struct *work)
0652 {
0653     struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, ba_work);
0654     struct rtw_txq_ba_iter_data data;
0655 
0656     rtw_iterate_stas_atomic(rtwdev, rtw_txq_ba_iter, &data);
0657 }
0658 
0659 void rtw_set_rx_freq_band(struct rtw_rx_pkt_stat *pkt_stat, u8 channel)
0660 {
0661     if (IS_CH_2G_BAND(channel))
0662         pkt_stat->band = NL80211_BAND_2GHZ;
0663     else if (IS_CH_5G_BAND(channel))
0664         pkt_stat->band = NL80211_BAND_5GHZ;
0665     else
0666         return;
0667 
0668     pkt_stat->freq = ieee80211_channel_to_frequency(channel, pkt_stat->band);
0669 }
0670 EXPORT_SYMBOL(rtw_set_rx_freq_band);
0671 
0672 void rtw_set_dtim_period(struct rtw_dev *rtwdev, int dtim_period)
0673 {
0674     rtw_write32_set(rtwdev, REG_TCR, BIT_TCR_UPDATE_TIMIE);
0675     rtw_write8(rtwdev, REG_DTIM_COUNTER_ROOT, dtim_period - 1);
0676 }
0677 
0678 void rtw_get_channel_params(struct cfg80211_chan_def *chandef,
0679                 struct rtw_channel_params *chan_params)
0680 {
0681     struct ieee80211_channel *channel = chandef->chan;
0682     enum nl80211_chan_width width = chandef->width;
0683     u8 *cch_by_bw = chan_params->cch_by_bw;
0684     u32 primary_freq, center_freq;
0685     u8 center_chan;
0686     u8 bandwidth = RTW_CHANNEL_WIDTH_20;
0687     u8 primary_chan_idx = 0;
0688     u8 i;
0689 
0690     center_chan = channel->hw_value;
0691     primary_freq = channel->center_freq;
0692     center_freq = chandef->center_freq1;
0693 
0694     /* assign the center channel used while 20M bw is selected */
0695     cch_by_bw[RTW_CHANNEL_WIDTH_20] = channel->hw_value;
0696 
0697     switch (width) {
0698     case NL80211_CHAN_WIDTH_20_NOHT:
0699     case NL80211_CHAN_WIDTH_20:
0700         bandwidth = RTW_CHANNEL_WIDTH_20;
0701         primary_chan_idx = RTW_SC_DONT_CARE;
0702         break;
0703     case NL80211_CHAN_WIDTH_40:
0704         bandwidth = RTW_CHANNEL_WIDTH_40;
0705         if (primary_freq > center_freq) {
0706             primary_chan_idx = RTW_SC_20_UPPER;
0707             center_chan -= 2;
0708         } else {
0709             primary_chan_idx = RTW_SC_20_LOWER;
0710             center_chan += 2;
0711         }
0712         break;
0713     case NL80211_CHAN_WIDTH_80:
0714         bandwidth = RTW_CHANNEL_WIDTH_80;
0715         if (primary_freq > center_freq) {
0716             if (primary_freq - center_freq == 10) {
0717                 primary_chan_idx = RTW_SC_20_UPPER;
0718                 center_chan -= 2;
0719             } else {
0720                 primary_chan_idx = RTW_SC_20_UPMOST;
0721                 center_chan -= 6;
0722             }
0723             /* assign the center channel used
0724              * while 40M bw is selected
0725              */
0726             cch_by_bw[RTW_CHANNEL_WIDTH_40] = center_chan + 4;
0727         } else {
0728             if (center_freq - primary_freq == 10) {
0729                 primary_chan_idx = RTW_SC_20_LOWER;
0730                 center_chan += 2;
0731             } else {
0732                 primary_chan_idx = RTW_SC_20_LOWEST;
0733                 center_chan += 6;
0734             }
0735             /* assign the center channel used
0736              * while 40M bw is selected
0737              */
0738             cch_by_bw[RTW_CHANNEL_WIDTH_40] = center_chan - 4;
0739         }
0740         break;
0741     default:
0742         center_chan = 0;
0743         break;
0744     }
0745 
0746     chan_params->center_chan = center_chan;
0747     chan_params->bandwidth = bandwidth;
0748     chan_params->primary_chan_idx = primary_chan_idx;
0749 
0750     /* assign the center channel used while current bw is selected */
0751     cch_by_bw[bandwidth] = center_chan;
0752 
0753     for (i = bandwidth + 1; i <= RTW_MAX_CHANNEL_WIDTH; i++)
0754         cch_by_bw[i] = 0;
0755 }
0756 
0757 void rtw_set_channel(struct rtw_dev *rtwdev)
0758 {
0759     struct ieee80211_hw *hw = rtwdev->hw;
0760     struct rtw_hal *hal = &rtwdev->hal;
0761     struct rtw_chip_info *chip = rtwdev->chip;
0762     struct rtw_channel_params ch_param;
0763     u8 center_chan, bandwidth, primary_chan_idx;
0764     u8 i;
0765 
0766     rtw_get_channel_params(&hw->conf.chandef, &ch_param);
0767     if (WARN(ch_param.center_chan == 0, "Invalid channel\n"))
0768         return;
0769 
0770     center_chan = ch_param.center_chan;
0771     bandwidth = ch_param.bandwidth;
0772     primary_chan_idx = ch_param.primary_chan_idx;
0773 
0774     hal->current_band_width = bandwidth;
0775     hal->current_channel = center_chan;
0776     hal->current_primary_channel_index = primary_chan_idx;
0777     hal->current_band_type = center_chan > 14 ? RTW_BAND_5G : RTW_BAND_2G;
0778 
0779     switch (center_chan) {
0780     case 1 ... 14:
0781         hal->sar_band = RTW_SAR_BAND_0;
0782         break;
0783     case 36 ... 64:
0784         hal->sar_band = RTW_SAR_BAND_1;
0785         break;
0786     case 100 ... 144:
0787         hal->sar_band = RTW_SAR_BAND_3;
0788         break;
0789     case 149 ... 177:
0790         hal->sar_band = RTW_SAR_BAND_4;
0791         break;
0792     default:
0793         WARN(1, "unknown ch(%u) to SAR band\n", center_chan);
0794         hal->sar_band = RTW_SAR_BAND_0;
0795         break;
0796     }
0797 
0798     for (i = RTW_CHANNEL_WIDTH_20; i <= RTW_MAX_CHANNEL_WIDTH; i++)
0799         hal->cch_by_bw[i] = ch_param.cch_by_bw[i];
0800 
0801     chip->ops->set_channel(rtwdev, center_chan, bandwidth, primary_chan_idx);
0802 
0803     if (hal->current_band_type == RTW_BAND_5G) {
0804         rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_5G);
0805     } else {
0806         if (test_bit(RTW_FLAG_SCANNING, rtwdev->flags))
0807             rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_24G);
0808         else
0809             rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_24G_NOFORSCAN);
0810     }
0811 
0812     rtw_phy_set_tx_power_level(rtwdev, center_chan);
0813 
0814     /* if the channel isn't set for scanning, we will do RF calibration
0815      * in ieee80211_ops::mgd_prepare_tx(). Performing the calibration
0816      * during scanning on each channel takes too long.
0817      */
0818     if (!test_bit(RTW_FLAG_SCANNING, rtwdev->flags))
0819         rtwdev->need_rfk = true;
0820 }
0821 
0822 void rtw_chip_prepare_tx(struct rtw_dev *rtwdev)
0823 {
0824     struct rtw_chip_info *chip = rtwdev->chip;
0825 
0826     if (rtwdev->need_rfk) {
0827         rtwdev->need_rfk = false;
0828         chip->ops->phy_calibration(rtwdev);
0829     }
0830 }
0831 
0832 static void rtw_vif_write_addr(struct rtw_dev *rtwdev, u32 start, u8 *addr)
0833 {
0834     int i;
0835 
0836     for (i = 0; i < ETH_ALEN; i++)
0837         rtw_write8(rtwdev, start + i, addr[i]);
0838 }
0839 
0840 void rtw_vif_port_config(struct rtw_dev *rtwdev,
0841              struct rtw_vif *rtwvif,
0842              u32 config)
0843 {
0844     u32 addr, mask;
0845 
0846     if (config & PORT_SET_MAC_ADDR) {
0847         addr = rtwvif->conf->mac_addr.addr;
0848         rtw_vif_write_addr(rtwdev, addr, rtwvif->mac_addr);
0849     }
0850     if (config & PORT_SET_BSSID) {
0851         addr = rtwvif->conf->bssid.addr;
0852         rtw_vif_write_addr(rtwdev, addr, rtwvif->bssid);
0853     }
0854     if (config & PORT_SET_NET_TYPE) {
0855         addr = rtwvif->conf->net_type.addr;
0856         mask = rtwvif->conf->net_type.mask;
0857         rtw_write32_mask(rtwdev, addr, mask, rtwvif->net_type);
0858     }
0859     if (config & PORT_SET_AID) {
0860         addr = rtwvif->conf->aid.addr;
0861         mask = rtwvif->conf->aid.mask;
0862         rtw_write32_mask(rtwdev, addr, mask, rtwvif->aid);
0863     }
0864     if (config & PORT_SET_BCN_CTRL) {
0865         addr = rtwvif->conf->bcn_ctrl.addr;
0866         mask = rtwvif->conf->bcn_ctrl.mask;
0867         rtw_write8_mask(rtwdev, addr, mask, rtwvif->bcn_ctrl);
0868     }
0869 }
0870 
0871 static u8 hw_bw_cap_to_bitamp(u8 bw_cap)
0872 {
0873     u8 bw = 0;
0874 
0875     switch (bw_cap) {
0876     case EFUSE_HW_CAP_IGNORE:
0877     case EFUSE_HW_CAP_SUPP_BW80:
0878         bw |= BIT(RTW_CHANNEL_WIDTH_80);
0879         fallthrough;
0880     case EFUSE_HW_CAP_SUPP_BW40:
0881         bw |= BIT(RTW_CHANNEL_WIDTH_40);
0882         fallthrough;
0883     default:
0884         bw |= BIT(RTW_CHANNEL_WIDTH_20);
0885         break;
0886     }
0887 
0888     return bw;
0889 }
0890 
0891 static void rtw_hw_config_rf_ant_num(struct rtw_dev *rtwdev, u8 hw_ant_num)
0892 {
0893     struct rtw_hal *hal = &rtwdev->hal;
0894     struct rtw_chip_info *chip = rtwdev->chip;
0895 
0896     if (hw_ant_num == EFUSE_HW_CAP_IGNORE ||
0897         hw_ant_num >= hal->rf_path_num)
0898         return;
0899 
0900     switch (hw_ant_num) {
0901     case 1:
0902         hal->rf_type = RF_1T1R;
0903         hal->rf_path_num = 1;
0904         if (!chip->fix_rf_phy_num)
0905             hal->rf_phy_num = hal->rf_path_num;
0906         hal->antenna_tx = BB_PATH_A;
0907         hal->antenna_rx = BB_PATH_A;
0908         break;
0909     default:
0910         WARN(1, "invalid hw configuration from efuse\n");
0911         break;
0912     }
0913 }
0914 
0915 static u64 get_vht_ra_mask(struct ieee80211_sta *sta)
0916 {
0917     u64 ra_mask = 0;
0918     u16 mcs_map = le16_to_cpu(sta->deflink.vht_cap.vht_mcs.rx_mcs_map);
0919     u8 vht_mcs_cap;
0920     int i, nss;
0921 
0922     /* 4SS, every two bits for MCS7/8/9 */
0923     for (i = 0, nss = 12; i < 4; i++, mcs_map >>= 2, nss += 10) {
0924         vht_mcs_cap = mcs_map & 0x3;
0925         switch (vht_mcs_cap) {
0926         case 2: /* MCS9 */
0927             ra_mask |= 0x3ffULL << nss;
0928             break;
0929         case 1: /* MCS8 */
0930             ra_mask |= 0x1ffULL << nss;
0931             break;
0932         case 0: /* MCS7 */
0933             ra_mask |= 0x0ffULL << nss;
0934             break;
0935         default:
0936             break;
0937         }
0938     }
0939 
0940     return ra_mask;
0941 }
0942 
0943 static u8 get_rate_id(u8 wireless_set, enum rtw_bandwidth bw_mode, u8 tx_num)
0944 {
0945     u8 rate_id = 0;
0946 
0947     switch (wireless_set) {
0948     case WIRELESS_CCK:
0949         rate_id = RTW_RATEID_B_20M;
0950         break;
0951     case WIRELESS_OFDM:
0952         rate_id = RTW_RATEID_G;
0953         break;
0954     case WIRELESS_CCK | WIRELESS_OFDM:
0955         rate_id = RTW_RATEID_BG;
0956         break;
0957     case WIRELESS_OFDM | WIRELESS_HT:
0958         if (tx_num == 1)
0959             rate_id = RTW_RATEID_GN_N1SS;
0960         else if (tx_num == 2)
0961             rate_id = RTW_RATEID_GN_N2SS;
0962         else if (tx_num == 3)
0963             rate_id = RTW_RATEID_ARFR5_N_3SS;
0964         break;
0965     case WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_HT:
0966         if (bw_mode == RTW_CHANNEL_WIDTH_40) {
0967             if (tx_num == 1)
0968                 rate_id = RTW_RATEID_BGN_40M_1SS;
0969             else if (tx_num == 2)
0970                 rate_id = RTW_RATEID_BGN_40M_2SS;
0971             else if (tx_num == 3)
0972                 rate_id = RTW_RATEID_ARFR5_N_3SS;
0973             else if (tx_num == 4)
0974                 rate_id = RTW_RATEID_ARFR7_N_4SS;
0975         } else {
0976             if (tx_num == 1)
0977                 rate_id = RTW_RATEID_BGN_20M_1SS;
0978             else if (tx_num == 2)
0979                 rate_id = RTW_RATEID_BGN_20M_2SS;
0980             else if (tx_num == 3)
0981                 rate_id = RTW_RATEID_ARFR5_N_3SS;
0982             else if (tx_num == 4)
0983                 rate_id = RTW_RATEID_ARFR7_N_4SS;
0984         }
0985         break;
0986     case WIRELESS_OFDM | WIRELESS_VHT:
0987         if (tx_num == 1)
0988             rate_id = RTW_RATEID_ARFR1_AC_1SS;
0989         else if (tx_num == 2)
0990             rate_id = RTW_RATEID_ARFR0_AC_2SS;
0991         else if (tx_num == 3)
0992             rate_id = RTW_RATEID_ARFR4_AC_3SS;
0993         else if (tx_num == 4)
0994             rate_id = RTW_RATEID_ARFR6_AC_4SS;
0995         break;
0996     case WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_VHT:
0997         if (bw_mode >= RTW_CHANNEL_WIDTH_80) {
0998             if (tx_num == 1)
0999                 rate_id = RTW_RATEID_ARFR1_AC_1SS;
1000             else if (tx_num == 2)
1001                 rate_id = RTW_RATEID_ARFR0_AC_2SS;
1002             else if (tx_num == 3)
1003                 rate_id = RTW_RATEID_ARFR4_AC_3SS;
1004             else if (tx_num == 4)
1005                 rate_id = RTW_RATEID_ARFR6_AC_4SS;
1006         } else {
1007             if (tx_num == 1)
1008                 rate_id = RTW_RATEID_ARFR2_AC_2G_1SS;
1009             else if (tx_num == 2)
1010                 rate_id = RTW_RATEID_ARFR3_AC_2G_2SS;
1011             else if (tx_num == 3)
1012                 rate_id = RTW_RATEID_ARFR4_AC_3SS;
1013             else if (tx_num == 4)
1014                 rate_id = RTW_RATEID_ARFR6_AC_4SS;
1015         }
1016         break;
1017     default:
1018         break;
1019     }
1020 
1021     return rate_id;
1022 }
1023 
1024 #define RA_MASK_CCK_RATES   0x0000f
1025 #define RA_MASK_OFDM_RATES  0x00ff0
1026 #define RA_MASK_HT_RATES_1SS    (0xff000ULL << 0)
1027 #define RA_MASK_HT_RATES_2SS    (0xff000ULL << 8)
1028 #define RA_MASK_HT_RATES_3SS    (0xff000ULL << 16)
1029 #define RA_MASK_HT_RATES    (RA_MASK_HT_RATES_1SS | \
1030                  RA_MASK_HT_RATES_2SS | \
1031                  RA_MASK_HT_RATES_3SS)
1032 #define RA_MASK_VHT_RATES_1SS   (0x3ff000ULL << 0)
1033 #define RA_MASK_VHT_RATES_2SS   (0x3ff000ULL << 10)
1034 #define RA_MASK_VHT_RATES_3SS   (0x3ff000ULL << 20)
1035 #define RA_MASK_VHT_RATES   (RA_MASK_VHT_RATES_1SS | \
1036                  RA_MASK_VHT_RATES_2SS | \
1037                  RA_MASK_VHT_RATES_3SS)
1038 #define RA_MASK_CCK_IN_BG   0x00005
1039 #define RA_MASK_CCK_IN_HT   0x00005
1040 #define RA_MASK_CCK_IN_VHT  0x00005
1041 #define RA_MASK_OFDM_IN_VHT 0x00010
1042 #define RA_MASK_OFDM_IN_HT_2G   0x00010
1043 #define RA_MASK_OFDM_IN_HT_5G   0x00030
1044 
1045 static u64 rtw_rate_mask_rssi(struct rtw_sta_info *si, u8 wireless_set)
1046 {
1047     u8 rssi_level = si->rssi_level;
1048 
1049     if (wireless_set == WIRELESS_CCK)
1050         return 0xffffffffffffffffULL;
1051 
1052     if (rssi_level == 0)
1053         return 0xffffffffffffffffULL;
1054     else if (rssi_level == 1)
1055         return 0xfffffffffffffff0ULL;
1056     else if (rssi_level == 2)
1057         return 0xffffffffffffefe0ULL;
1058     else if (rssi_level == 3)
1059         return 0xffffffffffffcfc0ULL;
1060     else if (rssi_level == 4)
1061         return 0xffffffffffff8f80ULL;
1062     else
1063         return 0xffffffffffff0f00ULL;
1064 }
1065 
1066 static u64 rtw_rate_mask_recover(u64 ra_mask, u64 ra_mask_bak)
1067 {
1068     if ((ra_mask & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)) == 0)
1069         ra_mask |= (ra_mask_bak & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES));
1070 
1071     if (ra_mask == 0)
1072         ra_mask |= (ra_mask_bak & (RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES));
1073 
1074     return ra_mask;
1075 }
1076 
1077 static u64 rtw_rate_mask_cfg(struct rtw_dev *rtwdev, struct rtw_sta_info *si,
1078                  u64 ra_mask, bool is_vht_enable)
1079 {
1080     struct rtw_hal *hal = &rtwdev->hal;
1081     const struct cfg80211_bitrate_mask *mask = si->mask;
1082     u64 cfg_mask = GENMASK_ULL(63, 0);
1083     u8 band;
1084 
1085     if (!si->use_cfg_mask)
1086         return ra_mask;
1087 
1088     band = hal->current_band_type;
1089     if (band == RTW_BAND_2G) {
1090         band = NL80211_BAND_2GHZ;
1091         cfg_mask = mask->control[band].legacy;
1092     } else if (band == RTW_BAND_5G) {
1093         band = NL80211_BAND_5GHZ;
1094         cfg_mask = u64_encode_bits(mask->control[band].legacy,
1095                        RA_MASK_OFDM_RATES);
1096     }
1097 
1098     if (!is_vht_enable) {
1099         if (ra_mask & RA_MASK_HT_RATES_1SS)
1100             cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[0],
1101                             RA_MASK_HT_RATES_1SS);
1102         if (ra_mask & RA_MASK_HT_RATES_2SS)
1103             cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[1],
1104                             RA_MASK_HT_RATES_2SS);
1105     } else {
1106         if (ra_mask & RA_MASK_VHT_RATES_1SS)
1107             cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[0],
1108                             RA_MASK_VHT_RATES_1SS);
1109         if (ra_mask & RA_MASK_VHT_RATES_2SS)
1110             cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[1],
1111                             RA_MASK_VHT_RATES_2SS);
1112     }
1113 
1114     ra_mask &= cfg_mask;
1115 
1116     return ra_mask;
1117 }
1118 
1119 void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si,
1120              bool reset_ra_mask)
1121 {
1122     struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1123     struct ieee80211_sta *sta = si->sta;
1124     struct rtw_efuse *efuse = &rtwdev->efuse;
1125     struct rtw_hal *hal = &rtwdev->hal;
1126     u8 wireless_set;
1127     u8 bw_mode;
1128     u8 rate_id;
1129     u8 rf_type = RF_1T1R;
1130     u8 stbc_en = 0;
1131     u8 ldpc_en = 0;
1132     u8 tx_num = 1;
1133     u64 ra_mask = 0;
1134     u64 ra_mask_bak = 0;
1135     bool is_vht_enable = false;
1136     bool is_support_sgi = false;
1137 
1138     if (sta->deflink.vht_cap.vht_supported) {
1139         is_vht_enable = true;
1140         ra_mask |= get_vht_ra_mask(sta);
1141         if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK)
1142             stbc_en = VHT_STBC_EN;
1143         if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC)
1144             ldpc_en = VHT_LDPC_EN;
1145     } else if (sta->deflink.ht_cap.ht_supported) {
1146         ra_mask |= (sta->deflink.ht_cap.mcs.rx_mask[1] << 20) |
1147                (sta->deflink.ht_cap.mcs.rx_mask[0] << 12);
1148         if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_RX_STBC)
1149             stbc_en = HT_STBC_EN;
1150         if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING)
1151             ldpc_en = HT_LDPC_EN;
1152     }
1153 
1154     if (efuse->hw_cap.nss == 1 || rtwdev->hal.txrx_1ss)
1155         ra_mask &= RA_MASK_VHT_RATES_1SS | RA_MASK_HT_RATES_1SS;
1156 
1157     if (hal->current_band_type == RTW_BAND_5G) {
1158         ra_mask |= (u64)sta->deflink.supp_rates[NL80211_BAND_5GHZ] << 4;
1159         ra_mask_bak = ra_mask;
1160         if (sta->deflink.vht_cap.vht_supported) {
1161             ra_mask &= RA_MASK_VHT_RATES | RA_MASK_OFDM_IN_VHT;
1162             wireless_set = WIRELESS_OFDM | WIRELESS_VHT;
1163         } else if (sta->deflink.ht_cap.ht_supported) {
1164             ra_mask &= RA_MASK_HT_RATES | RA_MASK_OFDM_IN_HT_5G;
1165             wireless_set = WIRELESS_OFDM | WIRELESS_HT;
1166         } else {
1167             wireless_set = WIRELESS_OFDM;
1168         }
1169         dm_info->rrsr_val_init = RRSR_INIT_5G;
1170     } else if (hal->current_band_type == RTW_BAND_2G) {
1171         ra_mask |= sta->deflink.supp_rates[NL80211_BAND_2GHZ];
1172         ra_mask_bak = ra_mask;
1173         if (sta->deflink.vht_cap.vht_supported) {
1174             ra_mask &= RA_MASK_VHT_RATES | RA_MASK_CCK_IN_VHT |
1175                    RA_MASK_OFDM_IN_VHT;
1176             wireless_set = WIRELESS_CCK | WIRELESS_OFDM |
1177                        WIRELESS_HT | WIRELESS_VHT;
1178         } else if (sta->deflink.ht_cap.ht_supported) {
1179             ra_mask &= RA_MASK_HT_RATES | RA_MASK_CCK_IN_HT |
1180                    RA_MASK_OFDM_IN_HT_2G;
1181             wireless_set = WIRELESS_CCK | WIRELESS_OFDM |
1182                        WIRELESS_HT;
1183         } else if (sta->deflink.supp_rates[0] <= 0xf) {
1184             wireless_set = WIRELESS_CCK;
1185         } else {
1186             ra_mask &= RA_MASK_OFDM_RATES | RA_MASK_CCK_IN_BG;
1187             wireless_set = WIRELESS_CCK | WIRELESS_OFDM;
1188         }
1189         dm_info->rrsr_val_init = RRSR_INIT_2G;
1190     } else {
1191         rtw_err(rtwdev, "Unknown band type\n");
1192         ra_mask_bak = ra_mask;
1193         wireless_set = 0;
1194     }
1195 
1196     switch (sta->deflink.bandwidth) {
1197     case IEEE80211_STA_RX_BW_80:
1198         bw_mode = RTW_CHANNEL_WIDTH_80;
1199         is_support_sgi = sta->deflink.vht_cap.vht_supported &&
1200                  (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80);
1201         break;
1202     case IEEE80211_STA_RX_BW_40:
1203         bw_mode = RTW_CHANNEL_WIDTH_40;
1204         is_support_sgi = sta->deflink.ht_cap.ht_supported &&
1205                  (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40);
1206         break;
1207     default:
1208         bw_mode = RTW_CHANNEL_WIDTH_20;
1209         is_support_sgi = sta->deflink.ht_cap.ht_supported &&
1210                  (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20);
1211         break;
1212     }
1213 
1214     if (sta->deflink.vht_cap.vht_supported && ra_mask & 0xffc00000) {
1215         tx_num = 2;
1216         rf_type = RF_2T2R;
1217     } else if (sta->deflink.ht_cap.ht_supported && ra_mask & 0xfff00000) {
1218         tx_num = 2;
1219         rf_type = RF_2T2R;
1220     }
1221 
1222     rate_id = get_rate_id(wireless_set, bw_mode, tx_num);
1223 
1224     ra_mask &= rtw_rate_mask_rssi(si, wireless_set);
1225     ra_mask = rtw_rate_mask_recover(ra_mask, ra_mask_bak);
1226     ra_mask = rtw_rate_mask_cfg(rtwdev, si, ra_mask, is_vht_enable);
1227 
1228     si->bw_mode = bw_mode;
1229     si->stbc_en = stbc_en;
1230     si->ldpc_en = ldpc_en;
1231     si->rf_type = rf_type;
1232     si->wireless_set = wireless_set;
1233     si->sgi_enable = is_support_sgi;
1234     si->vht_enable = is_vht_enable;
1235     si->ra_mask = ra_mask;
1236     si->rate_id = rate_id;
1237 
1238     rtw_fw_send_ra_info(rtwdev, si, reset_ra_mask);
1239 }
1240 
1241 static int rtw_wait_firmware_completion(struct rtw_dev *rtwdev)
1242 {
1243     struct rtw_chip_info *chip = rtwdev->chip;
1244     struct rtw_fw_state *fw;
1245 
1246     fw = &rtwdev->fw;
1247     wait_for_completion(&fw->completion);
1248     if (!fw->firmware)
1249         return -EINVAL;
1250 
1251     if (chip->wow_fw_name) {
1252         fw = &rtwdev->wow_fw;
1253         wait_for_completion(&fw->completion);
1254         if (!fw->firmware)
1255             return -EINVAL;
1256     }
1257 
1258     return 0;
1259 }
1260 
1261 static enum rtw_lps_deep_mode rtw_update_lps_deep_mode(struct rtw_dev *rtwdev,
1262                                struct rtw_fw_state *fw)
1263 {
1264     struct rtw_chip_info *chip = rtwdev->chip;
1265 
1266     if (rtw_disable_lps_deep_mode || !chip->lps_deep_mode_supported ||
1267         !fw->feature)
1268         return LPS_DEEP_MODE_NONE;
1269 
1270     if ((chip->lps_deep_mode_supported & BIT(LPS_DEEP_MODE_PG)) &&
1271         rtw_fw_feature_check(fw, FW_FEATURE_PG))
1272         return LPS_DEEP_MODE_PG;
1273 
1274     if ((chip->lps_deep_mode_supported & BIT(LPS_DEEP_MODE_LCLK)) &&
1275         rtw_fw_feature_check(fw, FW_FEATURE_LCLK))
1276         return LPS_DEEP_MODE_LCLK;
1277 
1278     return LPS_DEEP_MODE_NONE;
1279 }
1280 
1281 static int rtw_power_on(struct rtw_dev *rtwdev)
1282 {
1283     struct rtw_chip_info *chip = rtwdev->chip;
1284     struct rtw_fw_state *fw = &rtwdev->fw;
1285     bool wifi_only;
1286     int ret;
1287 
1288     ret = rtw_hci_setup(rtwdev);
1289     if (ret) {
1290         rtw_err(rtwdev, "failed to setup hci\n");
1291         goto err;
1292     }
1293 
1294     /* power on MAC before firmware downloaded */
1295     ret = rtw_mac_power_on(rtwdev);
1296     if (ret) {
1297         rtw_err(rtwdev, "failed to power on mac\n");
1298         goto err;
1299     }
1300 
1301     ret = rtw_wait_firmware_completion(rtwdev);
1302     if (ret) {
1303         rtw_err(rtwdev, "failed to wait firmware completion\n");
1304         goto err_off;
1305     }
1306 
1307     ret = rtw_download_firmware(rtwdev, fw);
1308     if (ret) {
1309         rtw_err(rtwdev, "failed to download firmware\n");
1310         goto err_off;
1311     }
1312 
1313     /* config mac after firmware downloaded */
1314     ret = rtw_mac_init(rtwdev);
1315     if (ret) {
1316         rtw_err(rtwdev, "failed to configure mac\n");
1317         goto err_off;
1318     }
1319 
1320     chip->ops->phy_set_param(rtwdev);
1321 
1322     ret = rtw_hci_start(rtwdev);
1323     if (ret) {
1324         rtw_err(rtwdev, "failed to start hci\n");
1325         goto err_off;
1326     }
1327 
1328     /* send H2C after HCI has started */
1329     rtw_fw_send_general_info(rtwdev);
1330     rtw_fw_send_phydm_info(rtwdev);
1331 
1332     wifi_only = !rtwdev->efuse.btcoex;
1333     rtw_coex_power_on_setting(rtwdev);
1334     rtw_coex_init_hw_config(rtwdev, wifi_only);
1335 
1336     return 0;
1337 
1338 err_off:
1339     rtw_mac_power_off(rtwdev);
1340 
1341 err:
1342     return ret;
1343 }
1344 
1345 void rtw_core_fw_scan_notify(struct rtw_dev *rtwdev, bool start)
1346 {
1347     if (!rtw_fw_feature_check(&rtwdev->fw, FW_FEATURE_NOTIFY_SCAN))
1348         return;
1349 
1350     if (start) {
1351         rtw_fw_scan_notify(rtwdev, true);
1352     } else {
1353         reinit_completion(&rtwdev->fw_scan_density);
1354         rtw_fw_scan_notify(rtwdev, false);
1355         if (!wait_for_completion_timeout(&rtwdev->fw_scan_density,
1356                          SCAN_NOTIFY_TIMEOUT))
1357             rtw_warn(rtwdev, "firmware failed to report density after scan\n");
1358     }
1359 }
1360 
1361 void rtw_core_scan_start(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif,
1362              const u8 *mac_addr, bool hw_scan)
1363 {
1364     u32 config = 0;
1365     int ret = 0;
1366 
1367     rtw_leave_lps(rtwdev);
1368 
1369     if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE)) {
1370         ret = rtw_leave_ips(rtwdev);
1371         if (ret) {
1372             rtw_err(rtwdev, "failed to leave idle state\n");
1373             return;
1374         }
1375     }
1376 
1377     ether_addr_copy(rtwvif->mac_addr, mac_addr);
1378     config |= PORT_SET_MAC_ADDR;
1379     rtw_vif_port_config(rtwdev, rtwvif, config);
1380 
1381     rtw_coex_scan_notify(rtwdev, COEX_SCAN_START);
1382     rtw_core_fw_scan_notify(rtwdev, true);
1383 
1384     set_bit(RTW_FLAG_DIG_DISABLE, rtwdev->flags);
1385     set_bit(RTW_FLAG_SCANNING, rtwdev->flags);
1386 }
1387 
1388 void rtw_core_scan_complete(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
1389                 bool hw_scan)
1390 {
1391     struct rtw_vif *rtwvif = vif ? (struct rtw_vif *)vif->drv_priv : NULL;
1392     u32 config = 0;
1393 
1394     if (!rtwvif)
1395         return;
1396 
1397     clear_bit(RTW_FLAG_SCANNING, rtwdev->flags);
1398     clear_bit(RTW_FLAG_DIG_DISABLE, rtwdev->flags);
1399 
1400     rtw_core_fw_scan_notify(rtwdev, false);
1401 
1402     ether_addr_copy(rtwvif->mac_addr, vif->addr);
1403     config |= PORT_SET_MAC_ADDR;
1404     rtw_vif_port_config(rtwdev, rtwvif, config);
1405 
1406     rtw_coex_scan_notify(rtwdev, COEX_SCAN_FINISH);
1407 
1408     if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE))
1409         ieee80211_queue_work(rtwdev->hw, &rtwdev->ips_work);
1410 }
1411 
1412 int rtw_core_start(struct rtw_dev *rtwdev)
1413 {
1414     int ret;
1415 
1416     ret = rtw_power_on(rtwdev);
1417     if (ret)
1418         return ret;
1419 
1420     rtw_sec_enable_sec_engine(rtwdev);
1421 
1422     rtwdev->lps_conf.deep_mode = rtw_update_lps_deep_mode(rtwdev, &rtwdev->fw);
1423     rtwdev->lps_conf.wow_deep_mode = rtw_update_lps_deep_mode(rtwdev, &rtwdev->wow_fw);
1424 
1425     /* rcr reset after powered on */
1426     rtw_write32(rtwdev, REG_RCR, rtwdev->hal.rcr);
1427 
1428     ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->watch_dog_work,
1429                      RTW_WATCH_DOG_DELAY_TIME);
1430 
1431     set_bit(RTW_FLAG_RUNNING, rtwdev->flags);
1432 
1433     return 0;
1434 }
1435 
1436 static void rtw_power_off(struct rtw_dev *rtwdev)
1437 {
1438     rtw_hci_stop(rtwdev);
1439     rtw_coex_power_off_setting(rtwdev);
1440     rtw_mac_power_off(rtwdev);
1441 }
1442 
1443 void rtw_core_stop(struct rtw_dev *rtwdev)
1444 {
1445     struct rtw_coex *coex = &rtwdev->coex;
1446 
1447     clear_bit(RTW_FLAG_RUNNING, rtwdev->flags);
1448     clear_bit(RTW_FLAG_FW_RUNNING, rtwdev->flags);
1449 
1450     mutex_unlock(&rtwdev->mutex);
1451 
1452     cancel_work_sync(&rtwdev->c2h_work);
1453     cancel_work_sync(&rtwdev->update_beacon_work);
1454     cancel_delayed_work_sync(&rtwdev->watch_dog_work);
1455     cancel_delayed_work_sync(&coex->bt_relink_work);
1456     cancel_delayed_work_sync(&coex->bt_reenable_work);
1457     cancel_delayed_work_sync(&coex->defreeze_work);
1458     cancel_delayed_work_sync(&coex->wl_remain_work);
1459     cancel_delayed_work_sync(&coex->bt_remain_work);
1460     cancel_delayed_work_sync(&coex->wl_connecting_work);
1461     cancel_delayed_work_sync(&coex->bt_multi_link_remain_work);
1462     cancel_delayed_work_sync(&coex->wl_ccklock_work);
1463 
1464     mutex_lock(&rtwdev->mutex);
1465 
1466     rtw_power_off(rtwdev);
1467 }
1468 
1469 static void rtw_init_ht_cap(struct rtw_dev *rtwdev,
1470                 struct ieee80211_sta_ht_cap *ht_cap)
1471 {
1472     struct rtw_efuse *efuse = &rtwdev->efuse;
1473     struct rtw_chip_info *chip = rtwdev->chip;
1474 
1475     ht_cap->ht_supported = true;
1476     ht_cap->cap = 0;
1477     ht_cap->cap |= IEEE80211_HT_CAP_SGI_20 |
1478             IEEE80211_HT_CAP_MAX_AMSDU |
1479             (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT);
1480 
1481     if (rtw_chip_has_rx_ldpc(rtwdev))
1482         ht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING;
1483     if (rtw_chip_has_tx_stbc(rtwdev))
1484         ht_cap->cap |= IEEE80211_HT_CAP_TX_STBC;
1485 
1486     if (efuse->hw_cap.bw & BIT(RTW_CHANNEL_WIDTH_40))
1487         ht_cap->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
1488                 IEEE80211_HT_CAP_DSSSCCK40 |
1489                 IEEE80211_HT_CAP_SGI_40;
1490     ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
1491     ht_cap->ampdu_density = chip->ampdu_density;
1492     ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
1493     if (efuse->hw_cap.nss > 1) {
1494         ht_cap->mcs.rx_mask[0] = 0xFF;
1495         ht_cap->mcs.rx_mask[1] = 0xFF;
1496         ht_cap->mcs.rx_mask[4] = 0x01;
1497         ht_cap->mcs.rx_highest = cpu_to_le16(300);
1498     } else {
1499         ht_cap->mcs.rx_mask[0] = 0xFF;
1500         ht_cap->mcs.rx_mask[1] = 0x00;
1501         ht_cap->mcs.rx_mask[4] = 0x01;
1502         ht_cap->mcs.rx_highest = cpu_to_le16(150);
1503     }
1504 }
1505 
1506 static void rtw_init_vht_cap(struct rtw_dev *rtwdev,
1507                  struct ieee80211_sta_vht_cap *vht_cap)
1508 {
1509     struct rtw_efuse *efuse = &rtwdev->efuse;
1510     u16 mcs_map;
1511     __le16 highest;
1512 
1513     if (efuse->hw_cap.ptcl != EFUSE_HW_CAP_IGNORE &&
1514         efuse->hw_cap.ptcl != EFUSE_HW_CAP_PTCL_VHT)
1515         return;
1516 
1517     vht_cap->vht_supported = true;
1518     vht_cap->cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 |
1519                IEEE80211_VHT_CAP_SHORT_GI_80 |
1520                IEEE80211_VHT_CAP_RXSTBC_1 |
1521                IEEE80211_VHT_CAP_HTC_VHT |
1522                IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK |
1523                0;
1524     if (rtwdev->hal.rf_path_num > 1)
1525         vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC;
1526     vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE |
1527             IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE;
1528     vht_cap->cap |= (rtwdev->hal.bfee_sts_cap <<
1529             IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT);
1530 
1531     if (rtw_chip_has_rx_ldpc(rtwdev))
1532         vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC;
1533 
1534     mcs_map = IEEE80211_VHT_MCS_SUPPORT_0_9 << 0 |
1535           IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 |
1536           IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 |
1537           IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 |
1538           IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 |
1539           IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 |
1540           IEEE80211_VHT_MCS_NOT_SUPPORTED << 14;
1541     if (efuse->hw_cap.nss > 1) {
1542         highest = cpu_to_le16(780);
1543         mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << 2;
1544     } else {
1545         highest = cpu_to_le16(390);
1546         mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << 2;
1547     }
1548 
1549     vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(mcs_map);
1550     vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(mcs_map);
1551     vht_cap->vht_mcs.rx_highest = highest;
1552     vht_cap->vht_mcs.tx_highest = highest;
1553 }
1554 
1555 static void rtw_set_supported_band(struct ieee80211_hw *hw,
1556                    struct rtw_chip_info *chip)
1557 {
1558     struct rtw_dev *rtwdev = hw->priv;
1559     struct ieee80211_supported_band *sband;
1560 
1561     if (chip->band & RTW_BAND_2G) {
1562         sband = kmemdup(&rtw_band_2ghz, sizeof(*sband), GFP_KERNEL);
1563         if (!sband)
1564             goto err_out;
1565         if (chip->ht_supported)
1566             rtw_init_ht_cap(rtwdev, &sband->ht_cap);
1567         hw->wiphy->bands[NL80211_BAND_2GHZ] = sband;
1568     }
1569 
1570     if (chip->band & RTW_BAND_5G) {
1571         sband = kmemdup(&rtw_band_5ghz, sizeof(*sband), GFP_KERNEL);
1572         if (!sband)
1573             goto err_out;
1574         if (chip->ht_supported)
1575             rtw_init_ht_cap(rtwdev, &sband->ht_cap);
1576         if (chip->vht_supported)
1577             rtw_init_vht_cap(rtwdev, &sband->vht_cap);
1578         hw->wiphy->bands[NL80211_BAND_5GHZ] = sband;
1579     }
1580 
1581     return;
1582 
1583 err_out:
1584     rtw_err(rtwdev, "failed to set supported band\n");
1585 }
1586 
1587 static void rtw_unset_supported_band(struct ieee80211_hw *hw,
1588                      struct rtw_chip_info *chip)
1589 {
1590     kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]);
1591     kfree(hw->wiphy->bands[NL80211_BAND_5GHZ]);
1592 }
1593 
1594 static void rtw_vif_smps_iter(void *data, u8 *mac,
1595                   struct ieee80211_vif *vif)
1596 {
1597     struct rtw_dev *rtwdev = (struct rtw_dev *)data;
1598 
1599     if (vif->type != NL80211_IFTYPE_STATION || !vif->cfg.assoc)
1600         return;
1601 
1602     if (rtwdev->hal.txrx_1ss)
1603         ieee80211_request_smps(vif, 0, IEEE80211_SMPS_STATIC);
1604     else
1605         ieee80211_request_smps(vif, 0, IEEE80211_SMPS_OFF);
1606 }
1607 
1608 void rtw_set_txrx_1ss(struct rtw_dev *rtwdev, bool txrx_1ss)
1609 {
1610     struct rtw_chip_info *chip = rtwdev->chip;
1611     struct rtw_hal *hal = &rtwdev->hal;
1612 
1613     if (!chip->ops->config_txrx_mode || rtwdev->hal.txrx_1ss == txrx_1ss)
1614         return;
1615 
1616     rtwdev->hal.txrx_1ss = txrx_1ss;
1617     if (txrx_1ss)
1618         chip->ops->config_txrx_mode(rtwdev, BB_PATH_A, BB_PATH_A, false);
1619     else
1620         chip->ops->config_txrx_mode(rtwdev, hal->antenna_tx,
1621                         hal->antenna_rx, false);
1622     rtw_iterate_vifs_atomic(rtwdev, rtw_vif_smps_iter, rtwdev);
1623 }
1624 
1625 static void __update_firmware_feature(struct rtw_dev *rtwdev,
1626                       struct rtw_fw_state *fw)
1627 {
1628     u32 feature;
1629     const struct rtw_fw_hdr *fw_hdr =
1630                 (const struct rtw_fw_hdr *)fw->firmware->data;
1631 
1632     feature = le32_to_cpu(fw_hdr->feature);
1633     fw->feature = feature & FW_FEATURE_SIG ? feature : 0;
1634 }
1635 
1636 static void __update_firmware_info(struct rtw_dev *rtwdev,
1637                    struct rtw_fw_state *fw)
1638 {
1639     const struct rtw_fw_hdr *fw_hdr =
1640                 (const struct rtw_fw_hdr *)fw->firmware->data;
1641 
1642     fw->h2c_version = le16_to_cpu(fw_hdr->h2c_fmt_ver);
1643     fw->version = le16_to_cpu(fw_hdr->version);
1644     fw->sub_version = fw_hdr->subversion;
1645     fw->sub_index = fw_hdr->subindex;
1646 
1647     __update_firmware_feature(rtwdev, fw);
1648 }
1649 
1650 static void __update_firmware_info_legacy(struct rtw_dev *rtwdev,
1651                       struct rtw_fw_state *fw)
1652 {
1653     struct rtw_fw_hdr_legacy *legacy =
1654                 (struct rtw_fw_hdr_legacy *)fw->firmware->data;
1655 
1656     fw->h2c_version = 0;
1657     fw->version = le16_to_cpu(legacy->version);
1658     fw->sub_version = legacy->subversion1;
1659     fw->sub_index = legacy->subversion2;
1660 }
1661 
1662 static void update_firmware_info(struct rtw_dev *rtwdev,
1663                  struct rtw_fw_state *fw)
1664 {
1665     if (rtw_chip_wcpu_11n(rtwdev))
1666         __update_firmware_info_legacy(rtwdev, fw);
1667     else
1668         __update_firmware_info(rtwdev, fw);
1669 }
1670 
1671 static void rtw_load_firmware_cb(const struct firmware *firmware, void *context)
1672 {
1673     struct rtw_fw_state *fw = context;
1674     struct rtw_dev *rtwdev = fw->rtwdev;
1675 
1676     if (!firmware || !firmware->data) {
1677         rtw_err(rtwdev, "failed to request firmware\n");
1678         complete_all(&fw->completion);
1679         return;
1680     }
1681 
1682     fw->firmware = firmware;
1683     update_firmware_info(rtwdev, fw);
1684     complete_all(&fw->completion);
1685 
1686     rtw_info(rtwdev, "Firmware version %u.%u.%u, H2C version %u\n",
1687          fw->version, fw->sub_version, fw->sub_index, fw->h2c_version);
1688 }
1689 
1690 static int rtw_load_firmware(struct rtw_dev *rtwdev, enum rtw_fw_type type)
1691 {
1692     const char *fw_name;
1693     struct rtw_fw_state *fw;
1694     int ret;
1695 
1696     switch (type) {
1697     case RTW_WOWLAN_FW:
1698         fw = &rtwdev->wow_fw;
1699         fw_name = rtwdev->chip->wow_fw_name;
1700         break;
1701 
1702     case RTW_NORMAL_FW:
1703         fw = &rtwdev->fw;
1704         fw_name = rtwdev->chip->fw_name;
1705         break;
1706 
1707     default:
1708         rtw_warn(rtwdev, "unsupported firmware type\n");
1709         return -ENOENT;
1710     }
1711 
1712     fw->rtwdev = rtwdev;
1713     init_completion(&fw->completion);
1714 
1715     ret = request_firmware_nowait(THIS_MODULE, true, fw_name, rtwdev->dev,
1716                       GFP_KERNEL, fw, rtw_load_firmware_cb);
1717     if (ret) {
1718         rtw_err(rtwdev, "failed to async firmware request\n");
1719         return ret;
1720     }
1721 
1722     return 0;
1723 }
1724 
1725 static int rtw_chip_parameter_setup(struct rtw_dev *rtwdev)
1726 {
1727     struct rtw_chip_info *chip = rtwdev->chip;
1728     struct rtw_hal *hal = &rtwdev->hal;
1729     struct rtw_efuse *efuse = &rtwdev->efuse;
1730 
1731     switch (rtw_hci_type(rtwdev)) {
1732     case RTW_HCI_TYPE_PCIE:
1733         rtwdev->hci.rpwm_addr = 0x03d9;
1734         rtwdev->hci.cpwm_addr = 0x03da;
1735         break;
1736     default:
1737         rtw_err(rtwdev, "unsupported hci type\n");
1738         return -EINVAL;
1739     }
1740 
1741     hal->chip_version = rtw_read32(rtwdev, REG_SYS_CFG1);
1742     hal->cut_version = BIT_GET_CHIP_VER(hal->chip_version);
1743     hal->mp_chip = (hal->chip_version & BIT_RTL_ID) ? 0 : 1;
1744     if (hal->chip_version & BIT_RF_TYPE_ID) {
1745         hal->rf_type = RF_2T2R;
1746         hal->rf_path_num = 2;
1747         hal->antenna_tx = BB_PATH_AB;
1748         hal->antenna_rx = BB_PATH_AB;
1749     } else {
1750         hal->rf_type = RF_1T1R;
1751         hal->rf_path_num = 1;
1752         hal->antenna_tx = BB_PATH_A;
1753         hal->antenna_rx = BB_PATH_A;
1754     }
1755     hal->rf_phy_num = chip->fix_rf_phy_num ? chip->fix_rf_phy_num :
1756               hal->rf_path_num;
1757 
1758     efuse->physical_size = chip->phy_efuse_size;
1759     efuse->logical_size = chip->log_efuse_size;
1760     efuse->protect_size = chip->ptct_efuse_size;
1761 
1762     /* default use ack */
1763     rtwdev->hal.rcr |= BIT_VHT_DACK;
1764 
1765     hal->bfee_sts_cap = 3;
1766 
1767     return 0;
1768 }
1769 
1770 static int rtw_chip_efuse_enable(struct rtw_dev *rtwdev)
1771 {
1772     struct rtw_fw_state *fw = &rtwdev->fw;
1773     int ret;
1774 
1775     ret = rtw_hci_setup(rtwdev);
1776     if (ret) {
1777         rtw_err(rtwdev, "failed to setup hci\n");
1778         goto err;
1779     }
1780 
1781     ret = rtw_mac_power_on(rtwdev);
1782     if (ret) {
1783         rtw_err(rtwdev, "failed to power on mac\n");
1784         goto err;
1785     }
1786 
1787     rtw_write8(rtwdev, REG_C2HEVT, C2H_HW_FEATURE_DUMP);
1788 
1789     wait_for_completion(&fw->completion);
1790     if (!fw->firmware) {
1791         ret = -EINVAL;
1792         rtw_err(rtwdev, "failed to load firmware\n");
1793         goto err;
1794     }
1795 
1796     ret = rtw_download_firmware(rtwdev, fw);
1797     if (ret) {
1798         rtw_err(rtwdev, "failed to download firmware\n");
1799         goto err_off;
1800     }
1801 
1802     return 0;
1803 
1804 err_off:
1805     rtw_mac_power_off(rtwdev);
1806 
1807 err:
1808     return ret;
1809 }
1810 
1811 static int rtw_dump_hw_feature(struct rtw_dev *rtwdev)
1812 {
1813     struct rtw_efuse *efuse = &rtwdev->efuse;
1814     u8 hw_feature[HW_FEATURE_LEN];
1815     u8 id;
1816     u8 bw;
1817     int i;
1818 
1819     id = rtw_read8(rtwdev, REG_C2HEVT);
1820     if (id != C2H_HW_FEATURE_REPORT) {
1821         rtw_err(rtwdev, "failed to read hw feature report\n");
1822         return -EBUSY;
1823     }
1824 
1825     for (i = 0; i < HW_FEATURE_LEN; i++)
1826         hw_feature[i] = rtw_read8(rtwdev, REG_C2HEVT + 2 + i);
1827 
1828     rtw_write8(rtwdev, REG_C2HEVT, 0);
1829 
1830     bw = GET_EFUSE_HW_CAP_BW(hw_feature);
1831     efuse->hw_cap.bw = hw_bw_cap_to_bitamp(bw);
1832     efuse->hw_cap.hci = GET_EFUSE_HW_CAP_HCI(hw_feature);
1833     efuse->hw_cap.nss = GET_EFUSE_HW_CAP_NSS(hw_feature);
1834     efuse->hw_cap.ptcl = GET_EFUSE_HW_CAP_PTCL(hw_feature);
1835     efuse->hw_cap.ant_num = GET_EFUSE_HW_CAP_ANT_NUM(hw_feature);
1836 
1837     rtw_hw_config_rf_ant_num(rtwdev, efuse->hw_cap.ant_num);
1838 
1839     if (efuse->hw_cap.nss == EFUSE_HW_CAP_IGNORE ||
1840         efuse->hw_cap.nss > rtwdev->hal.rf_path_num)
1841         efuse->hw_cap.nss = rtwdev->hal.rf_path_num;
1842 
1843     rtw_dbg(rtwdev, RTW_DBG_EFUSE,
1844         "hw cap: hci=0x%02x, bw=0x%02x, ptcl=0x%02x, ant_num=%d, nss=%d\n",
1845         efuse->hw_cap.hci, efuse->hw_cap.bw, efuse->hw_cap.ptcl,
1846         efuse->hw_cap.ant_num, efuse->hw_cap.nss);
1847 
1848     return 0;
1849 }
1850 
1851 static void rtw_chip_efuse_disable(struct rtw_dev *rtwdev)
1852 {
1853     rtw_hci_stop(rtwdev);
1854     rtw_mac_power_off(rtwdev);
1855 }
1856 
1857 static int rtw_chip_efuse_info_setup(struct rtw_dev *rtwdev)
1858 {
1859     struct rtw_efuse *efuse = &rtwdev->efuse;
1860     int ret;
1861 
1862     mutex_lock(&rtwdev->mutex);
1863 
1864     /* power on mac to read efuse */
1865     ret = rtw_chip_efuse_enable(rtwdev);
1866     if (ret)
1867         goto out_unlock;
1868 
1869     ret = rtw_parse_efuse_map(rtwdev);
1870     if (ret)
1871         goto out_disable;
1872 
1873     ret = rtw_dump_hw_feature(rtwdev);
1874     if (ret)
1875         goto out_disable;
1876 
1877     ret = rtw_check_supported_rfe(rtwdev);
1878     if (ret)
1879         goto out_disable;
1880 
1881     if (efuse->crystal_cap == 0xff)
1882         efuse->crystal_cap = 0;
1883     if (efuse->pa_type_2g == 0xff)
1884         efuse->pa_type_2g = 0;
1885     if (efuse->pa_type_5g == 0xff)
1886         efuse->pa_type_5g = 0;
1887     if (efuse->lna_type_2g == 0xff)
1888         efuse->lna_type_2g = 0;
1889     if (efuse->lna_type_5g == 0xff)
1890         efuse->lna_type_5g = 0;
1891     if (efuse->channel_plan == 0xff)
1892         efuse->channel_plan = 0x7f;
1893     if (efuse->rf_board_option == 0xff)
1894         efuse->rf_board_option = 0;
1895     if (efuse->bt_setting & BIT(0))
1896         efuse->share_ant = true;
1897     if (efuse->regd == 0xff)
1898         efuse->regd = 0;
1899     if (efuse->tx_bb_swing_setting_2g == 0xff)
1900         efuse->tx_bb_swing_setting_2g = 0;
1901     if (efuse->tx_bb_swing_setting_5g == 0xff)
1902         efuse->tx_bb_swing_setting_5g = 0;
1903 
1904     efuse->btcoex = (efuse->rf_board_option & 0xe0) == 0x20;
1905     efuse->ext_pa_2g = efuse->pa_type_2g & BIT(4) ? 1 : 0;
1906     efuse->ext_lna_2g = efuse->lna_type_2g & BIT(3) ? 1 : 0;
1907     efuse->ext_pa_5g = efuse->pa_type_5g & BIT(0) ? 1 : 0;
1908     efuse->ext_lna_2g = efuse->lna_type_5g & BIT(3) ? 1 : 0;
1909 
1910 out_disable:
1911     rtw_chip_efuse_disable(rtwdev);
1912 
1913 out_unlock:
1914     mutex_unlock(&rtwdev->mutex);
1915     return ret;
1916 }
1917 
1918 static int rtw_chip_board_info_setup(struct rtw_dev *rtwdev)
1919 {
1920     struct rtw_hal *hal = &rtwdev->hal;
1921     const struct rtw_rfe_def *rfe_def = rtw_get_rfe_def(rtwdev);
1922 
1923     if (!rfe_def)
1924         return -ENODEV;
1925 
1926     rtw_phy_setup_phy_cond(rtwdev, 0);
1927 
1928     rtw_phy_init_tx_power(rtwdev);
1929     if (rfe_def->agc_btg_tbl)
1930         rtw_load_table(rtwdev, rfe_def->agc_btg_tbl);
1931     rtw_load_table(rtwdev, rfe_def->phy_pg_tbl);
1932     rtw_load_table(rtwdev, rfe_def->txpwr_lmt_tbl);
1933     rtw_phy_tx_power_by_rate_config(hal);
1934     rtw_phy_tx_power_limit_config(hal);
1935 
1936     return 0;
1937 }
1938 
1939 int rtw_chip_info_setup(struct rtw_dev *rtwdev)
1940 {
1941     int ret;
1942 
1943     ret = rtw_chip_parameter_setup(rtwdev);
1944     if (ret) {
1945         rtw_err(rtwdev, "failed to setup chip parameters\n");
1946         goto err_out;
1947     }
1948 
1949     ret = rtw_chip_efuse_info_setup(rtwdev);
1950     if (ret) {
1951         rtw_err(rtwdev, "failed to setup chip efuse info\n");
1952         goto err_out;
1953     }
1954 
1955     ret = rtw_chip_board_info_setup(rtwdev);
1956     if (ret) {
1957         rtw_err(rtwdev, "failed to setup chip board info\n");
1958         goto err_out;
1959     }
1960 
1961     return 0;
1962 
1963 err_out:
1964     return ret;
1965 }
1966 EXPORT_SYMBOL(rtw_chip_info_setup);
1967 
1968 static void rtw_stats_init(struct rtw_dev *rtwdev)
1969 {
1970     struct rtw_traffic_stats *stats = &rtwdev->stats;
1971     struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1972     int i;
1973 
1974     ewma_tp_init(&stats->tx_ewma_tp);
1975     ewma_tp_init(&stats->rx_ewma_tp);
1976 
1977     for (i = 0; i < RTW_EVM_NUM; i++)
1978         ewma_evm_init(&dm_info->ewma_evm[i]);
1979     for (i = 0; i < RTW_SNR_NUM; i++)
1980         ewma_snr_init(&dm_info->ewma_snr[i]);
1981 }
1982 
1983 int rtw_core_init(struct rtw_dev *rtwdev)
1984 {
1985     struct rtw_chip_info *chip = rtwdev->chip;
1986     struct rtw_coex *coex = &rtwdev->coex;
1987     int ret;
1988 
1989     INIT_LIST_HEAD(&rtwdev->rsvd_page_list);
1990     INIT_LIST_HEAD(&rtwdev->txqs);
1991 
1992     timer_setup(&rtwdev->tx_report.purge_timer,
1993             rtw_tx_report_purge_timer, 0);
1994     rtwdev->tx_wq = alloc_workqueue("rtw_tx_wq", WQ_UNBOUND | WQ_HIGHPRI, 0);
1995     if (!rtwdev->tx_wq) {
1996         rtw_warn(rtwdev, "alloc_workqueue rtw_tx_wq failed\n");
1997         return -ENOMEM;
1998     }
1999 
2000     INIT_DELAYED_WORK(&rtwdev->watch_dog_work, rtw_watch_dog_work);
2001     INIT_DELAYED_WORK(&coex->bt_relink_work, rtw_coex_bt_relink_work);
2002     INIT_DELAYED_WORK(&coex->bt_reenable_work, rtw_coex_bt_reenable_work);
2003     INIT_DELAYED_WORK(&coex->defreeze_work, rtw_coex_defreeze_work);
2004     INIT_DELAYED_WORK(&coex->wl_remain_work, rtw_coex_wl_remain_work);
2005     INIT_DELAYED_WORK(&coex->bt_remain_work, rtw_coex_bt_remain_work);
2006     INIT_DELAYED_WORK(&coex->wl_connecting_work, rtw_coex_wl_connecting_work);
2007     INIT_DELAYED_WORK(&coex->bt_multi_link_remain_work,
2008               rtw_coex_bt_multi_link_remain_work);
2009     INIT_DELAYED_WORK(&coex->wl_ccklock_work, rtw_coex_wl_ccklock_work);
2010     INIT_WORK(&rtwdev->tx_work, rtw_tx_work);
2011     INIT_WORK(&rtwdev->c2h_work, rtw_c2h_work);
2012     INIT_WORK(&rtwdev->ips_work, rtw_ips_work);
2013     INIT_WORK(&rtwdev->fw_recovery_work, rtw_fw_recovery_work);
2014     INIT_WORK(&rtwdev->update_beacon_work, rtw_fw_update_beacon_work);
2015     INIT_WORK(&rtwdev->ba_work, rtw_txq_ba_work);
2016     skb_queue_head_init(&rtwdev->c2h_queue);
2017     skb_queue_head_init(&rtwdev->coex.queue);
2018     skb_queue_head_init(&rtwdev->tx_report.queue);
2019 
2020     spin_lock_init(&rtwdev->rf_lock);
2021     spin_lock_init(&rtwdev->h2c.lock);
2022     spin_lock_init(&rtwdev->txq_lock);
2023     spin_lock_init(&rtwdev->tx_report.q_lock);
2024 
2025     mutex_init(&rtwdev->mutex);
2026     mutex_init(&rtwdev->coex.mutex);
2027     mutex_init(&rtwdev->hal.tx_power_mutex);
2028 
2029     init_waitqueue_head(&rtwdev->coex.wait);
2030     init_completion(&rtwdev->lps_leave_check);
2031     init_completion(&rtwdev->fw_scan_density);
2032 
2033     rtwdev->sec.total_cam_num = 32;
2034     rtwdev->hal.current_channel = 1;
2035     rtwdev->dm_info.fix_rate = U8_MAX;
2036     set_bit(RTW_BC_MC_MACID, rtwdev->mac_id_map);
2037 
2038     rtw_stats_init(rtwdev);
2039 
2040     /* default rx filter setting */
2041     rtwdev->hal.rcr = BIT_APP_FCS | BIT_APP_MIC | BIT_APP_ICV |
2042               BIT_PKTCTL_DLEN | BIT_HTC_LOC_CTRL | BIT_APP_PHYSTS |
2043               BIT_AB | BIT_AM | BIT_APM;
2044 
2045     ret = rtw_load_firmware(rtwdev, RTW_NORMAL_FW);
2046     if (ret) {
2047         rtw_warn(rtwdev, "no firmware loaded\n");
2048         return ret;
2049     }
2050 
2051     if (chip->wow_fw_name) {
2052         ret = rtw_load_firmware(rtwdev, RTW_WOWLAN_FW);
2053         if (ret) {
2054             rtw_warn(rtwdev, "no wow firmware loaded\n");
2055             wait_for_completion(&rtwdev->fw.completion);
2056             if (rtwdev->fw.firmware)
2057                 release_firmware(rtwdev->fw.firmware);
2058             return ret;
2059         }
2060     }
2061 
2062     return 0;
2063 }
2064 EXPORT_SYMBOL(rtw_core_init);
2065 
2066 void rtw_core_deinit(struct rtw_dev *rtwdev)
2067 {
2068     struct rtw_fw_state *fw = &rtwdev->fw;
2069     struct rtw_fw_state *wow_fw = &rtwdev->wow_fw;
2070     struct rtw_rsvd_page *rsvd_pkt, *tmp;
2071     unsigned long flags;
2072 
2073     rtw_wait_firmware_completion(rtwdev);
2074 
2075     if (fw->firmware)
2076         release_firmware(fw->firmware);
2077 
2078     if (wow_fw->firmware)
2079         release_firmware(wow_fw->firmware);
2080 
2081     destroy_workqueue(rtwdev->tx_wq);
2082     spin_lock_irqsave(&rtwdev->tx_report.q_lock, flags);
2083     skb_queue_purge(&rtwdev->tx_report.queue);
2084     skb_queue_purge(&rtwdev->coex.queue);
2085     spin_unlock_irqrestore(&rtwdev->tx_report.q_lock, flags);
2086 
2087     list_for_each_entry_safe(rsvd_pkt, tmp, &rtwdev->rsvd_page_list,
2088                  build_list) {
2089         list_del(&rsvd_pkt->build_list);
2090         kfree(rsvd_pkt);
2091     }
2092 
2093     mutex_destroy(&rtwdev->mutex);
2094     mutex_destroy(&rtwdev->coex.mutex);
2095     mutex_destroy(&rtwdev->hal.tx_power_mutex);
2096 }
2097 EXPORT_SYMBOL(rtw_core_deinit);
2098 
2099 int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw)
2100 {
2101     struct rtw_hal *hal = &rtwdev->hal;
2102     int max_tx_headroom = 0;
2103     int ret;
2104 
2105     /* TODO: USB & SDIO may need extra room? */
2106     max_tx_headroom = rtwdev->chip->tx_pkt_desc_sz;
2107 
2108     hw->extra_tx_headroom = max_tx_headroom;
2109     hw->queues = IEEE80211_NUM_ACS;
2110     hw->txq_data_size = sizeof(struct rtw_txq);
2111     hw->sta_data_size = sizeof(struct rtw_sta_info);
2112     hw->vif_data_size = sizeof(struct rtw_vif);
2113 
2114     ieee80211_hw_set(hw, SIGNAL_DBM);
2115     ieee80211_hw_set(hw, RX_INCLUDES_FCS);
2116     ieee80211_hw_set(hw, AMPDU_AGGREGATION);
2117     ieee80211_hw_set(hw, MFP_CAPABLE);
2118     ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS);
2119     ieee80211_hw_set(hw, SUPPORTS_PS);
2120     ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS);
2121     ieee80211_hw_set(hw, SUPPORT_FAST_XMIT);
2122     ieee80211_hw_set(hw, SUPPORTS_AMSDU_IN_AMPDU);
2123     ieee80211_hw_set(hw, HAS_RATE_CONTROL);
2124     ieee80211_hw_set(hw, TX_AMSDU);
2125     ieee80211_hw_set(hw, SINGLE_SCAN_ON_ALL_BANDS);
2126 
2127     hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) |
2128                      BIT(NL80211_IFTYPE_AP) |
2129                      BIT(NL80211_IFTYPE_ADHOC) |
2130                      BIT(NL80211_IFTYPE_MESH_POINT);
2131     hw->wiphy->available_antennas_tx = hal->antenna_tx;
2132     hw->wiphy->available_antennas_rx = hal->antenna_rx;
2133 
2134     hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS |
2135                 WIPHY_FLAG_TDLS_EXTERNAL_SETUP;
2136 
2137     hw->wiphy->features |= NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR;
2138     hw->wiphy->max_scan_ssids = RTW_SCAN_MAX_SSIDS;
2139     hw->wiphy->max_scan_ie_len = RTW_SCAN_MAX_IE_LEN;
2140 
2141     wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0);
2142     wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SCAN_RANDOM_SN);
2143     wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SET_SCAN_DWELL);
2144 
2145 #ifdef CONFIG_PM
2146     hw->wiphy->wowlan = rtwdev->chip->wowlan_stub;
2147     hw->wiphy->max_sched_scan_ssids = rtwdev->chip->max_sched_scan_ssids;
2148 #endif
2149     rtw_set_supported_band(hw, rtwdev->chip);
2150     SET_IEEE80211_PERM_ADDR(hw, rtwdev->efuse.addr);
2151 
2152     hw->wiphy->sar_capa = &rtw_sar_capa;
2153 
2154     ret = rtw_regd_init(rtwdev);
2155     if (ret) {
2156         rtw_err(rtwdev, "failed to init regd\n");
2157         return ret;
2158     }
2159 
2160     ret = ieee80211_register_hw(hw);
2161     if (ret) {
2162         rtw_err(rtwdev, "failed to register hw\n");
2163         return ret;
2164     }
2165 
2166     ret = rtw_regd_hint(rtwdev);
2167     if (ret) {
2168         rtw_err(rtwdev, "failed to hint regd\n");
2169         return ret;
2170     }
2171 
2172     rtw_debugfs_init(rtwdev);
2173 
2174     rtwdev->bf_info.bfer_mu_cnt = 0;
2175     rtwdev->bf_info.bfer_su_cnt = 0;
2176 
2177     return 0;
2178 }
2179 EXPORT_SYMBOL(rtw_register_hw);
2180 
2181 void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw)
2182 {
2183     struct rtw_chip_info *chip = rtwdev->chip;
2184 
2185     ieee80211_unregister_hw(hw);
2186     rtw_unset_supported_band(hw, chip);
2187 }
2188 EXPORT_SYMBOL(rtw_unregister_hw);
2189 
2190 MODULE_AUTHOR("Realtek Corporation");
2191 MODULE_DESCRIPTION("Realtek 802.11ac wireless core module");
2192 MODULE_LICENSE("Dual BSD/GPL");
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