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0001 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
0002 /* Copyright(c) 2018-2019  Realtek Corporation
0003  */
0004 
0005 #include "main.h"
0006 #include "mac.h"
0007 #include "reg.h"
0008 #include "fw.h"
0009 #include "debug.h"
0010 
0011 void rtw_set_channel_mac(struct rtw_dev *rtwdev, u8 channel, u8 bw,
0012              u8 primary_ch_idx)
0013 {
0014     u8 txsc40 = 0, txsc20 = 0;
0015     u32 value32;
0016     u8 value8;
0017 
0018     txsc20 = primary_ch_idx;
0019     if (bw == RTW_CHANNEL_WIDTH_80) {
0020         if (txsc20 == RTW_SC_20_UPPER || txsc20 == RTW_SC_20_UPMOST)
0021             txsc40 = RTW_SC_40_UPPER;
0022         else
0023             txsc40 = RTW_SC_40_LOWER;
0024     }
0025     rtw_write8(rtwdev, REG_DATA_SC,
0026            BIT_TXSC_20M(txsc20) | BIT_TXSC_40M(txsc40));
0027 
0028     value32 = rtw_read32(rtwdev, REG_WMAC_TRXPTCL_CTL);
0029     value32 &= ~BIT_RFMOD;
0030     switch (bw) {
0031     case RTW_CHANNEL_WIDTH_80:
0032         value32 |= BIT_RFMOD_80M;
0033         break;
0034     case RTW_CHANNEL_WIDTH_40:
0035         value32 |= BIT_RFMOD_40M;
0036         break;
0037     case RTW_CHANNEL_WIDTH_20:
0038     default:
0039         break;
0040     }
0041     rtw_write32(rtwdev, REG_WMAC_TRXPTCL_CTL, value32);
0042 
0043     if (rtw_chip_wcpu_11n(rtwdev))
0044         return;
0045 
0046     value32 = rtw_read32(rtwdev, REG_AFE_CTRL1) & ~(BIT_MAC_CLK_SEL);
0047     value32 |= (MAC_CLK_HW_DEF_80M << BIT_SHIFT_MAC_CLK_SEL);
0048     rtw_write32(rtwdev, REG_AFE_CTRL1, value32);
0049 
0050     rtw_write8(rtwdev, REG_USTIME_TSF, MAC_CLK_SPEED);
0051     rtw_write8(rtwdev, REG_USTIME_EDCA, MAC_CLK_SPEED);
0052 
0053     value8 = rtw_read8(rtwdev, REG_CCK_CHECK);
0054     value8 = value8 & ~BIT_CHECK_CCK_EN;
0055     if (IS_CH_5G_BAND(channel))
0056         value8 |= BIT_CHECK_CCK_EN;
0057     rtw_write8(rtwdev, REG_CCK_CHECK, value8);
0058 }
0059 EXPORT_SYMBOL(rtw_set_channel_mac);
0060 
0061 static int rtw_mac_pre_system_cfg(struct rtw_dev *rtwdev)
0062 {
0063     u32 value32;
0064     u8 value8;
0065 
0066     rtw_write8(rtwdev, REG_RSV_CTRL, 0);
0067 
0068     if (rtw_chip_wcpu_11n(rtwdev)) {
0069         if (rtw_read32(rtwdev, REG_SYS_CFG1) & BIT_LDO)
0070             rtw_write8(rtwdev, REG_LDO_SWR_CTRL, LDO_SEL);
0071         else
0072             rtw_write8(rtwdev, REG_LDO_SWR_CTRL, SPS_SEL);
0073         return 0;
0074     }
0075 
0076     switch (rtw_hci_type(rtwdev)) {
0077     case RTW_HCI_TYPE_PCIE:
0078         rtw_write32_set(rtwdev, REG_HCI_OPT_CTRL, BIT_USB_SUS_DIS);
0079         break;
0080     case RTW_HCI_TYPE_USB:
0081         break;
0082     default:
0083         return -EINVAL;
0084     }
0085 
0086     /* config PIN Mux */
0087     value32 = rtw_read32(rtwdev, REG_PAD_CTRL1);
0088     value32 |= BIT_PAPE_WLBT_SEL | BIT_LNAON_WLBT_SEL;
0089     rtw_write32(rtwdev, REG_PAD_CTRL1, value32);
0090 
0091     value32 = rtw_read32(rtwdev, REG_LED_CFG);
0092     value32 &= ~(BIT_PAPE_SEL_EN | BIT_LNAON_SEL_EN);
0093     rtw_write32(rtwdev, REG_LED_CFG, value32);
0094 
0095     value32 = rtw_read32(rtwdev, REG_GPIO_MUXCFG);
0096     value32 |= BIT_WLRFE_4_5_EN;
0097     rtw_write32(rtwdev, REG_GPIO_MUXCFG, value32);
0098 
0099     /* disable BB/RF */
0100     value8 = rtw_read8(rtwdev, REG_SYS_FUNC_EN);
0101     value8 &= ~(BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST);
0102     rtw_write8(rtwdev, REG_SYS_FUNC_EN, value8);
0103 
0104     value8 = rtw_read8(rtwdev, REG_RF_CTRL);
0105     value8 &= ~(BIT_RF_SDM_RSTB | BIT_RF_RSTB | BIT_RF_EN);
0106     rtw_write8(rtwdev, REG_RF_CTRL, value8);
0107 
0108     value32 = rtw_read32(rtwdev, REG_WLRF1);
0109     value32 &= ~BIT_WLRF1_BBRF_EN;
0110     rtw_write32(rtwdev, REG_WLRF1, value32);
0111 
0112     return 0;
0113 }
0114 
0115 static bool do_pwr_poll_cmd(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 target)
0116 {
0117     u32 val;
0118 
0119     target &= mask;
0120 
0121     return read_poll_timeout_atomic(rtw_read8, val, (val & mask) == target,
0122                     50, 50 * RTW_PWR_POLLING_CNT, false,
0123                     rtwdev, addr) == 0;
0124 }
0125 
0126 static int rtw_pwr_cmd_polling(struct rtw_dev *rtwdev,
0127                    const struct rtw_pwr_seq_cmd *cmd)
0128 {
0129     u8 value;
0130     u32 offset;
0131 
0132     if (cmd->base == RTW_PWR_ADDR_SDIO)
0133         offset = cmd->offset | SDIO_LOCAL_OFFSET;
0134     else
0135         offset = cmd->offset;
0136 
0137     if (do_pwr_poll_cmd(rtwdev, offset, cmd->mask, cmd->value))
0138         return 0;
0139 
0140     if (rtw_hci_type(rtwdev) != RTW_HCI_TYPE_PCIE)
0141         goto err;
0142 
0143     /* if PCIE, toggle BIT_PFM_WOWL and try again */
0144     value = rtw_read8(rtwdev, REG_SYS_PW_CTRL);
0145     if (rtwdev->chip->id == RTW_CHIP_TYPE_8723D)
0146         rtw_write8(rtwdev, REG_SYS_PW_CTRL, value & ~BIT_PFM_WOWL);
0147     rtw_write8(rtwdev, REG_SYS_PW_CTRL, value | BIT_PFM_WOWL);
0148     rtw_write8(rtwdev, REG_SYS_PW_CTRL, value & ~BIT_PFM_WOWL);
0149     if (rtwdev->chip->id == RTW_CHIP_TYPE_8723D)
0150         rtw_write8(rtwdev, REG_SYS_PW_CTRL, value | BIT_PFM_WOWL);
0151 
0152     if (do_pwr_poll_cmd(rtwdev, offset, cmd->mask, cmd->value))
0153         return 0;
0154 
0155 err:
0156     rtw_err(rtwdev, "failed to poll offset=0x%x mask=0x%x value=0x%x\n",
0157         offset, cmd->mask, cmd->value);
0158     return -EBUSY;
0159 }
0160 
0161 static int rtw_sub_pwr_seq_parser(struct rtw_dev *rtwdev, u8 intf_mask,
0162                   u8 cut_mask,
0163                   const struct rtw_pwr_seq_cmd *cmd)
0164 {
0165     const struct rtw_pwr_seq_cmd *cur_cmd;
0166     u32 offset;
0167     u8 value;
0168 
0169     for (cur_cmd = cmd; cur_cmd->cmd != RTW_PWR_CMD_END; cur_cmd++) {
0170         if (!(cur_cmd->intf_mask & intf_mask) ||
0171             !(cur_cmd->cut_mask & cut_mask))
0172             continue;
0173 
0174         switch (cur_cmd->cmd) {
0175         case RTW_PWR_CMD_WRITE:
0176             offset = cur_cmd->offset;
0177 
0178             if (cur_cmd->base == RTW_PWR_ADDR_SDIO)
0179                 offset |= SDIO_LOCAL_OFFSET;
0180 
0181             value = rtw_read8(rtwdev, offset);
0182             value &= ~cur_cmd->mask;
0183             value |= (cur_cmd->value & cur_cmd->mask);
0184             rtw_write8(rtwdev, offset, value);
0185             break;
0186         case RTW_PWR_CMD_POLLING:
0187             if (rtw_pwr_cmd_polling(rtwdev, cur_cmd))
0188                 return -EBUSY;
0189             break;
0190         case RTW_PWR_CMD_DELAY:
0191             if (cur_cmd->value == RTW_PWR_DELAY_US)
0192                 udelay(cur_cmd->offset);
0193             else
0194                 mdelay(cur_cmd->offset);
0195             break;
0196         case RTW_PWR_CMD_READ:
0197             break;
0198         default:
0199             return -EINVAL;
0200         }
0201     }
0202 
0203     return 0;
0204 }
0205 
0206 static int rtw_pwr_seq_parser(struct rtw_dev *rtwdev,
0207                   const struct rtw_pwr_seq_cmd **cmd_seq)
0208 {
0209     u8 cut_mask;
0210     u8 intf_mask;
0211     u8 cut;
0212     u32 idx = 0;
0213     const struct rtw_pwr_seq_cmd *cmd;
0214     int ret;
0215 
0216     cut = rtwdev->hal.cut_version;
0217     cut_mask = cut_version_to_mask(cut);
0218     switch (rtw_hci_type(rtwdev)) {
0219     case RTW_HCI_TYPE_PCIE:
0220         intf_mask = BIT(2);
0221         break;
0222     case RTW_HCI_TYPE_USB:
0223         intf_mask = BIT(1);
0224         break;
0225     default:
0226         return -EINVAL;
0227     }
0228 
0229     do {
0230         cmd = cmd_seq[idx];
0231         if (!cmd)
0232             break;
0233 
0234         ret = rtw_sub_pwr_seq_parser(rtwdev, intf_mask, cut_mask, cmd);
0235         if (ret)
0236             return -EBUSY;
0237 
0238         idx++;
0239     } while (1);
0240 
0241     return 0;
0242 }
0243 
0244 static int rtw_mac_power_switch(struct rtw_dev *rtwdev, bool pwr_on)
0245 {
0246     struct rtw_chip_info *chip = rtwdev->chip;
0247     const struct rtw_pwr_seq_cmd **pwr_seq;
0248     u8 rpwm;
0249     bool cur_pwr;
0250 
0251     if (rtw_chip_wcpu_11ac(rtwdev)) {
0252         rpwm = rtw_read8(rtwdev, rtwdev->hci.rpwm_addr);
0253 
0254         /* Check FW still exist or not */
0255         if (rtw_read16(rtwdev, REG_MCUFW_CTRL) == 0xC078) {
0256             rpwm = (rpwm ^ BIT_RPWM_TOGGLE) & BIT_RPWM_TOGGLE;
0257             rtw_write8(rtwdev, rtwdev->hci.rpwm_addr, rpwm);
0258         }
0259     }
0260 
0261     if (rtw_read8(rtwdev, REG_CR) == 0xea)
0262         cur_pwr = false;
0263     else if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB &&
0264          (rtw_read8(rtwdev, REG_SYS_STATUS1 + 1) & BIT(0)))
0265         cur_pwr = false;
0266     else
0267         cur_pwr = true;
0268 
0269     if (pwr_on == cur_pwr)
0270         return -EALREADY;
0271 
0272     pwr_seq = pwr_on ? chip->pwr_on_seq : chip->pwr_off_seq;
0273     if (rtw_pwr_seq_parser(rtwdev, pwr_seq))
0274         return -EINVAL;
0275 
0276     return 0;
0277 }
0278 
0279 static int __rtw_mac_init_system_cfg(struct rtw_dev *rtwdev)
0280 {
0281     u8 sys_func_en = rtwdev->chip->sys_func_en;
0282     u8 value8;
0283     u32 value, tmp;
0284 
0285     value = rtw_read32(rtwdev, REG_CPU_DMEM_CON);
0286     value |= BIT_WL_PLATFORM_RST | BIT_DDMA_EN;
0287     rtw_write32(rtwdev, REG_CPU_DMEM_CON, value);
0288 
0289     rtw_write8_set(rtwdev, REG_SYS_FUNC_EN + 1, sys_func_en);
0290     value8 = (rtw_read8(rtwdev, REG_CR_EXT + 3) & 0xF0) | 0x0C;
0291     rtw_write8(rtwdev, REG_CR_EXT + 3, value8);
0292 
0293     /* disable boot-from-flash for driver's DL FW */
0294     tmp = rtw_read32(rtwdev, REG_MCUFW_CTRL);
0295     if (tmp & BIT_BOOT_FSPI_EN) {
0296         rtw_write32(rtwdev, REG_MCUFW_CTRL, tmp & (~BIT_BOOT_FSPI_EN));
0297         value = rtw_read32(rtwdev, REG_GPIO_MUXCFG) & (~BIT_FSPI_EN);
0298         rtw_write32(rtwdev, REG_GPIO_MUXCFG, value);
0299     }
0300 
0301     return 0;
0302 }
0303 
0304 static int __rtw_mac_init_system_cfg_legacy(struct rtw_dev *rtwdev)
0305 {
0306     rtw_write8(rtwdev, REG_CR, 0xff);
0307     mdelay(2);
0308     rtw_write8(rtwdev, REG_HWSEQ_CTRL, 0x7f);
0309     mdelay(2);
0310 
0311     rtw_write8_set(rtwdev, REG_SYS_CLKR, BIT_WAKEPAD_EN);
0312     rtw_write16_clr(rtwdev, REG_GPIO_MUXCFG, BIT_EN_SIC);
0313 
0314     rtw_write16(rtwdev, REG_CR, 0x2ff);
0315 
0316     return 0;
0317 }
0318 
0319 static int rtw_mac_init_system_cfg(struct rtw_dev *rtwdev)
0320 {
0321     if (rtw_chip_wcpu_11n(rtwdev))
0322         return __rtw_mac_init_system_cfg_legacy(rtwdev);
0323 
0324     return __rtw_mac_init_system_cfg(rtwdev);
0325 }
0326 
0327 int rtw_mac_power_on(struct rtw_dev *rtwdev)
0328 {
0329     int ret = 0;
0330 
0331     ret = rtw_mac_pre_system_cfg(rtwdev);
0332     if (ret)
0333         goto err;
0334 
0335     ret = rtw_mac_power_switch(rtwdev, true);
0336     if (ret == -EALREADY) {
0337         rtw_mac_power_switch(rtwdev, false);
0338         ret = rtw_mac_power_switch(rtwdev, true);
0339         if (ret)
0340             goto err;
0341     } else if (ret) {
0342         goto err;
0343     }
0344 
0345     ret = rtw_mac_init_system_cfg(rtwdev);
0346     if (ret)
0347         goto err;
0348 
0349     return 0;
0350 
0351 err:
0352     rtw_err(rtwdev, "mac power on failed");
0353     return ret;
0354 }
0355 
0356 void rtw_mac_power_off(struct rtw_dev *rtwdev)
0357 {
0358     rtw_mac_power_switch(rtwdev, false);
0359 }
0360 
0361 static bool check_firmware_size(const u8 *data, u32 size)
0362 {
0363     const struct rtw_fw_hdr *fw_hdr = (const struct rtw_fw_hdr *)data;
0364     u32 dmem_size;
0365     u32 imem_size;
0366     u32 emem_size;
0367     u32 real_size;
0368 
0369     dmem_size = le32_to_cpu(fw_hdr->dmem_size);
0370     imem_size = le32_to_cpu(fw_hdr->imem_size);
0371     emem_size = (fw_hdr->mem_usage & BIT(4)) ?
0372             le32_to_cpu(fw_hdr->emem_size) : 0;
0373 
0374     dmem_size += FW_HDR_CHKSUM_SIZE;
0375     imem_size += FW_HDR_CHKSUM_SIZE;
0376     emem_size += emem_size ? FW_HDR_CHKSUM_SIZE : 0;
0377     real_size = FW_HDR_SIZE + dmem_size + imem_size + emem_size;
0378     if (real_size != size)
0379         return false;
0380 
0381     return true;
0382 }
0383 
0384 static void wlan_cpu_enable(struct rtw_dev *rtwdev, bool enable)
0385 {
0386     if (enable) {
0387         /* cpu io interface enable */
0388         rtw_write8_set(rtwdev, REG_RSV_CTRL + 1, BIT_WLMCU_IOIF);
0389 
0390         /* cpu enable */
0391         rtw_write8_set(rtwdev, REG_SYS_FUNC_EN + 1, BIT_FEN_CPUEN);
0392     } else {
0393         /* cpu io interface disable */
0394         rtw_write8_clr(rtwdev, REG_SYS_FUNC_EN + 1, BIT_FEN_CPUEN);
0395 
0396         /* cpu disable */
0397         rtw_write8_clr(rtwdev, REG_RSV_CTRL + 1, BIT_WLMCU_IOIF);
0398     }
0399 }
0400 
0401 #define DLFW_RESTORE_REG_NUM 6
0402 
0403 static void download_firmware_reg_backup(struct rtw_dev *rtwdev,
0404                      struct rtw_backup_info *bckp)
0405 {
0406     u8 tmp;
0407     u8 bckp_idx = 0;
0408 
0409     /* set HIQ to hi priority */
0410     bckp[bckp_idx].len = 1;
0411     bckp[bckp_idx].reg = REG_TXDMA_PQ_MAP + 1;
0412     bckp[bckp_idx].val = rtw_read8(rtwdev, REG_TXDMA_PQ_MAP + 1);
0413     bckp_idx++;
0414     tmp = RTW_DMA_MAPPING_HIGH << 6;
0415     rtw_write8(rtwdev, REG_TXDMA_PQ_MAP + 1, tmp);
0416 
0417     /* DLFW only use HIQ, map HIQ to hi priority */
0418     bckp[bckp_idx].len = 1;
0419     bckp[bckp_idx].reg = REG_CR;
0420     bckp[bckp_idx].val = rtw_read8(rtwdev, REG_CR);
0421     bckp_idx++;
0422     bckp[bckp_idx].len = 4;
0423     bckp[bckp_idx].reg = REG_H2CQ_CSR;
0424     bckp[bckp_idx].val = BIT_H2CQ_FULL;
0425     bckp_idx++;
0426     tmp = BIT_HCI_TXDMA_EN | BIT_TXDMA_EN;
0427     rtw_write8(rtwdev, REG_CR, tmp);
0428     rtw_write32(rtwdev, REG_H2CQ_CSR, BIT_H2CQ_FULL);
0429 
0430     /* Config hi priority queue and public priority queue page number */
0431     bckp[bckp_idx].len = 2;
0432     bckp[bckp_idx].reg = REG_FIFOPAGE_INFO_1;
0433     bckp[bckp_idx].val = rtw_read16(rtwdev, REG_FIFOPAGE_INFO_1);
0434     bckp_idx++;
0435     bckp[bckp_idx].len = 4;
0436     bckp[bckp_idx].reg = REG_RQPN_CTRL_2;
0437     bckp[bckp_idx].val = rtw_read32(rtwdev, REG_RQPN_CTRL_2) | BIT_LD_RQPN;
0438     bckp_idx++;
0439     rtw_write16(rtwdev, REG_FIFOPAGE_INFO_1, 0x200);
0440     rtw_write32(rtwdev, REG_RQPN_CTRL_2, bckp[bckp_idx - 1].val);
0441 
0442     /* Disable beacon related functions */
0443     tmp = rtw_read8(rtwdev, REG_BCN_CTRL);
0444     bckp[bckp_idx].len = 1;
0445     bckp[bckp_idx].reg = REG_BCN_CTRL;
0446     bckp[bckp_idx].val = tmp;
0447     bckp_idx++;
0448     tmp = (u8)((tmp & (~BIT_EN_BCN_FUNCTION)) | BIT_DIS_TSF_UDT);
0449     rtw_write8(rtwdev, REG_BCN_CTRL, tmp);
0450 
0451     WARN(bckp_idx != DLFW_RESTORE_REG_NUM, "wrong backup number\n");
0452 }
0453 
0454 static void download_firmware_reset_platform(struct rtw_dev *rtwdev)
0455 {
0456     rtw_write8_clr(rtwdev, REG_CPU_DMEM_CON + 2, BIT_WL_PLATFORM_RST >> 16);
0457     rtw_write8_clr(rtwdev, REG_SYS_CLK_CTRL + 1, BIT_CPU_CLK_EN >> 8);
0458     rtw_write8_set(rtwdev, REG_CPU_DMEM_CON + 2, BIT_WL_PLATFORM_RST >> 16);
0459     rtw_write8_set(rtwdev, REG_SYS_CLK_CTRL + 1, BIT_CPU_CLK_EN >> 8);
0460 }
0461 
0462 static void download_firmware_reg_restore(struct rtw_dev *rtwdev,
0463                       struct rtw_backup_info *bckp,
0464                       u8 bckp_num)
0465 {
0466     rtw_restore_reg(rtwdev, bckp, bckp_num);
0467 }
0468 
0469 #define TX_DESC_SIZE 48
0470 
0471 static int send_firmware_pkt_rsvd_page(struct rtw_dev *rtwdev, u16 pg_addr,
0472                        const u8 *data, u32 size)
0473 {
0474     u8 *buf;
0475     int ret;
0476 
0477     buf = kmemdup(data, size, GFP_KERNEL);
0478     if (!buf)
0479         return -ENOMEM;
0480 
0481     ret = rtw_fw_write_data_rsvd_page(rtwdev, pg_addr, buf, size);
0482     kfree(buf);
0483     return ret;
0484 }
0485 
0486 static int
0487 send_firmware_pkt(struct rtw_dev *rtwdev, u16 pg_addr, const u8 *data, u32 size)
0488 {
0489     int ret;
0490 
0491     if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB &&
0492         !((size + TX_DESC_SIZE) & (512 - 1)))
0493         size += 1;
0494 
0495     ret = send_firmware_pkt_rsvd_page(rtwdev, pg_addr, data, size);
0496     if (ret)
0497         rtw_err(rtwdev, "failed to download rsvd page\n");
0498 
0499     return ret;
0500 }
0501 
0502 static int
0503 iddma_enable(struct rtw_dev *rtwdev, u32 src, u32 dst, u32 ctrl)
0504 {
0505     rtw_write32(rtwdev, REG_DDMA_CH0SA, src);
0506     rtw_write32(rtwdev, REG_DDMA_CH0DA, dst);
0507     rtw_write32(rtwdev, REG_DDMA_CH0CTRL, ctrl);
0508 
0509     if (!check_hw_ready(rtwdev, REG_DDMA_CH0CTRL, BIT_DDMACH0_OWN, 0))
0510         return -EBUSY;
0511 
0512     return 0;
0513 }
0514 
0515 static int iddma_download_firmware(struct rtw_dev *rtwdev, u32 src, u32 dst,
0516                    u32 len, u8 first)
0517 {
0518     u32 ch0_ctrl = BIT_DDMACH0_CHKSUM_EN | BIT_DDMACH0_OWN;
0519 
0520     if (!check_hw_ready(rtwdev, REG_DDMA_CH0CTRL, BIT_DDMACH0_OWN, 0))
0521         return -EBUSY;
0522 
0523     ch0_ctrl |= len & BIT_MASK_DDMACH0_DLEN;
0524     if (!first)
0525         ch0_ctrl |= BIT_DDMACH0_CHKSUM_CONT;
0526 
0527     if (iddma_enable(rtwdev, src, dst, ch0_ctrl))
0528         return -EBUSY;
0529 
0530     return 0;
0531 }
0532 
0533 int rtw_ddma_to_fw_fifo(struct rtw_dev *rtwdev, u32 ocp_src, u32 size)
0534 {
0535     u32 ch0_ctrl = BIT_DDMACH0_OWN | BIT_DDMACH0_DDMA_MODE;
0536 
0537     if (!check_hw_ready(rtwdev, REG_DDMA_CH0CTRL, BIT_DDMACH0_OWN, 0)) {
0538         rtw_dbg(rtwdev, RTW_DBG_FW, "busy to start ddma\n");
0539         return -EBUSY;
0540     }
0541 
0542     ch0_ctrl |= size & BIT_MASK_DDMACH0_DLEN;
0543 
0544     if (iddma_enable(rtwdev, ocp_src, OCPBASE_RXBUF_FW_88XX, ch0_ctrl)) {
0545         rtw_dbg(rtwdev, RTW_DBG_FW, "busy to complete ddma\n");
0546         return -EBUSY;
0547     }
0548 
0549     return 0;
0550 }
0551 
0552 static bool
0553 check_fw_checksum(struct rtw_dev *rtwdev, u32 addr)
0554 {
0555     u8 fw_ctrl;
0556 
0557     fw_ctrl = rtw_read8(rtwdev, REG_MCUFW_CTRL);
0558 
0559     if (rtw_read32(rtwdev, REG_DDMA_CH0CTRL) & BIT_DDMACH0_CHKSUM_STS) {
0560         if (addr < OCPBASE_DMEM_88XX) {
0561             fw_ctrl |= BIT_IMEM_DW_OK;
0562             fw_ctrl &= ~BIT_IMEM_CHKSUM_OK;
0563             rtw_write8(rtwdev, REG_MCUFW_CTRL, fw_ctrl);
0564         } else {
0565             fw_ctrl |= BIT_DMEM_DW_OK;
0566             fw_ctrl &= ~BIT_DMEM_CHKSUM_OK;
0567             rtw_write8(rtwdev, REG_MCUFW_CTRL, fw_ctrl);
0568         }
0569 
0570         rtw_err(rtwdev, "invalid fw checksum\n");
0571 
0572         return false;
0573     }
0574 
0575     if (addr < OCPBASE_DMEM_88XX) {
0576         fw_ctrl |= (BIT_IMEM_DW_OK | BIT_IMEM_CHKSUM_OK);
0577         rtw_write8(rtwdev, REG_MCUFW_CTRL, fw_ctrl);
0578     } else {
0579         fw_ctrl |= (BIT_DMEM_DW_OK | BIT_DMEM_CHKSUM_OK);
0580         rtw_write8(rtwdev, REG_MCUFW_CTRL, fw_ctrl);
0581     }
0582 
0583     return true;
0584 }
0585 
0586 static int
0587 download_firmware_to_mem(struct rtw_dev *rtwdev, const u8 *data,
0588              u32 src, u32 dst, u32 size)
0589 {
0590     struct rtw_chip_info *chip = rtwdev->chip;
0591     u32 desc_size = chip->tx_pkt_desc_sz;
0592     u8 first_part;
0593     u32 mem_offset;
0594     u32 residue_size;
0595     u32 pkt_size;
0596     u32 max_size = 0x1000;
0597     u32 val;
0598     int ret;
0599 
0600     mem_offset = 0;
0601     first_part = 1;
0602     residue_size = size;
0603 
0604     val = rtw_read32(rtwdev, REG_DDMA_CH0CTRL);
0605     val |= BIT_DDMACH0_RESET_CHKSUM_STS;
0606     rtw_write32(rtwdev, REG_DDMA_CH0CTRL, val);
0607 
0608     while (residue_size) {
0609         if (residue_size >= max_size)
0610             pkt_size = max_size;
0611         else
0612             pkt_size = residue_size;
0613 
0614         ret = send_firmware_pkt(rtwdev, (u16)(src >> 7),
0615                     data + mem_offset, pkt_size);
0616         if (ret)
0617             return ret;
0618 
0619         ret = iddma_download_firmware(rtwdev, OCPBASE_TXBUF_88XX +
0620                           src + desc_size,
0621                           dst + mem_offset, pkt_size,
0622                           first_part);
0623         if (ret)
0624             return ret;
0625 
0626         first_part = 0;
0627         mem_offset += pkt_size;
0628         residue_size -= pkt_size;
0629     }
0630 
0631     if (!check_fw_checksum(rtwdev, dst))
0632         return -EINVAL;
0633 
0634     return 0;
0635 }
0636 
0637 static int
0638 start_download_firmware(struct rtw_dev *rtwdev, const u8 *data, u32 size)
0639 {
0640     const struct rtw_fw_hdr *fw_hdr = (const struct rtw_fw_hdr *)data;
0641     const u8 *cur_fw;
0642     u16 val;
0643     u32 imem_size;
0644     u32 dmem_size;
0645     u32 emem_size;
0646     u32 addr;
0647     int ret;
0648 
0649     dmem_size = le32_to_cpu(fw_hdr->dmem_size);
0650     imem_size = le32_to_cpu(fw_hdr->imem_size);
0651     emem_size = (fw_hdr->mem_usage & BIT(4)) ?
0652             le32_to_cpu(fw_hdr->emem_size) : 0;
0653     dmem_size += FW_HDR_CHKSUM_SIZE;
0654     imem_size += FW_HDR_CHKSUM_SIZE;
0655     emem_size += emem_size ? FW_HDR_CHKSUM_SIZE : 0;
0656 
0657     val = (u16)(rtw_read16(rtwdev, REG_MCUFW_CTRL) & 0x3800);
0658     val |= BIT_MCUFWDL_EN;
0659     rtw_write16(rtwdev, REG_MCUFW_CTRL, val);
0660 
0661     cur_fw = data + FW_HDR_SIZE;
0662     addr = le32_to_cpu(fw_hdr->dmem_addr);
0663     addr &= ~BIT(31);
0664     ret = download_firmware_to_mem(rtwdev, cur_fw, 0, addr, dmem_size);
0665     if (ret)
0666         return ret;
0667 
0668     cur_fw = data + FW_HDR_SIZE + dmem_size;
0669     addr = le32_to_cpu(fw_hdr->imem_addr);
0670     addr &= ~BIT(31);
0671     ret = download_firmware_to_mem(rtwdev, cur_fw, 0, addr, imem_size);
0672     if (ret)
0673         return ret;
0674 
0675     if (emem_size) {
0676         cur_fw = data + FW_HDR_SIZE + dmem_size + imem_size;
0677         addr = le32_to_cpu(fw_hdr->emem_addr);
0678         addr &= ~BIT(31);
0679         ret = download_firmware_to_mem(rtwdev, cur_fw, 0, addr,
0680                            emem_size);
0681         if (ret)
0682             return ret;
0683     }
0684 
0685     return 0;
0686 }
0687 
0688 static int download_firmware_validate(struct rtw_dev *rtwdev)
0689 {
0690     u32 fw_key;
0691 
0692     if (!check_hw_ready(rtwdev, REG_MCUFW_CTRL, FW_READY_MASK, FW_READY)) {
0693         fw_key = rtw_read32(rtwdev, REG_FW_DBG7) & FW_KEY_MASK;
0694         if (fw_key == ILLEGAL_KEY_GROUP)
0695             rtw_err(rtwdev, "invalid fw key\n");
0696         return -EINVAL;
0697     }
0698 
0699     return 0;
0700 }
0701 
0702 static void download_firmware_end_flow(struct rtw_dev *rtwdev)
0703 {
0704     u16 fw_ctrl;
0705 
0706     rtw_write32(rtwdev, REG_TXDMA_STATUS, BTI_PAGE_OVF);
0707 
0708     /* Check IMEM & DMEM checksum is OK or not */
0709     fw_ctrl = rtw_read16(rtwdev, REG_MCUFW_CTRL);
0710     if ((fw_ctrl & BIT_CHECK_SUM_OK) != BIT_CHECK_SUM_OK)
0711         return;
0712 
0713     fw_ctrl = (fw_ctrl | BIT_FW_DW_RDY) & ~BIT_MCUFWDL_EN;
0714     rtw_write16(rtwdev, REG_MCUFW_CTRL, fw_ctrl);
0715 }
0716 
0717 static int __rtw_download_firmware(struct rtw_dev *rtwdev,
0718                    struct rtw_fw_state *fw)
0719 {
0720     struct rtw_backup_info bckp[DLFW_RESTORE_REG_NUM];
0721     const u8 *data = fw->firmware->data;
0722     u32 size = fw->firmware->size;
0723     u32 ltecoex_bckp;
0724     int ret;
0725 
0726     if (!check_firmware_size(data, size))
0727         return -EINVAL;
0728 
0729     if (!ltecoex_read_reg(rtwdev, 0x38, &ltecoex_bckp))
0730         return -EBUSY;
0731 
0732     wlan_cpu_enable(rtwdev, false);
0733 
0734     download_firmware_reg_backup(rtwdev, bckp);
0735     download_firmware_reset_platform(rtwdev);
0736 
0737     ret = start_download_firmware(rtwdev, data, size);
0738     if (ret)
0739         goto dlfw_fail;
0740 
0741     download_firmware_reg_restore(rtwdev, bckp, DLFW_RESTORE_REG_NUM);
0742 
0743     download_firmware_end_flow(rtwdev);
0744 
0745     wlan_cpu_enable(rtwdev, true);
0746 
0747     if (!ltecoex_reg_write(rtwdev, 0x38, ltecoex_bckp))
0748         return -EBUSY;
0749 
0750     ret = download_firmware_validate(rtwdev);
0751     if (ret)
0752         goto dlfw_fail;
0753 
0754     /* reset desc and index */
0755     rtw_hci_setup(rtwdev);
0756 
0757     rtwdev->h2c.last_box_num = 0;
0758     rtwdev->h2c.seq = 0;
0759 
0760     set_bit(RTW_FLAG_FW_RUNNING, rtwdev->flags);
0761 
0762     return 0;
0763 
0764 dlfw_fail:
0765     /* Disable FWDL_EN */
0766     rtw_write8_clr(rtwdev, REG_MCUFW_CTRL, BIT_MCUFWDL_EN);
0767     rtw_write8_set(rtwdev, REG_SYS_FUNC_EN + 1, BIT_FEN_CPUEN);
0768 
0769     return ret;
0770 }
0771 
0772 static void en_download_firmware_legacy(struct rtw_dev *rtwdev, bool en)
0773 {
0774     int try;
0775 
0776     if (en) {
0777         wlan_cpu_enable(rtwdev, false);
0778         wlan_cpu_enable(rtwdev, true);
0779 
0780         rtw_write8_set(rtwdev, REG_MCUFW_CTRL, BIT_MCUFWDL_EN);
0781 
0782         for (try = 0; try < 10; try++) {
0783             if (rtw_read8(rtwdev, REG_MCUFW_CTRL) & BIT_MCUFWDL_EN)
0784                 goto fwdl_ready;
0785             rtw_write8_set(rtwdev, REG_MCUFW_CTRL, BIT_MCUFWDL_EN);
0786             msleep(20);
0787         }
0788         rtw_err(rtwdev, "failed to check fw download ready\n");
0789 fwdl_ready:
0790         rtw_write32_clr(rtwdev, REG_MCUFW_CTRL, BIT_ROM_DLEN);
0791     } else {
0792         rtw_write8_clr(rtwdev, REG_MCUFW_CTRL, BIT_MCUFWDL_EN);
0793     }
0794 }
0795 
0796 static void
0797 write_firmware_page(struct rtw_dev *rtwdev, u32 page, const u8 *data, u32 size)
0798 {
0799     u32 val32;
0800     u32 block_nr;
0801     u32 remain_size;
0802     u32 write_addr = FW_START_ADDR_LEGACY;
0803     const __le32 *ptr = (const __le32 *)data;
0804     u32 block;
0805     __le32 remain_data = 0;
0806 
0807     block_nr = size >> DLFW_BLK_SIZE_SHIFT_LEGACY;
0808     remain_size = size & (DLFW_BLK_SIZE_LEGACY - 1);
0809 
0810     val32 = rtw_read32(rtwdev, REG_MCUFW_CTRL);
0811     val32 &= ~BIT_ROM_PGE;
0812     val32 |= (page << BIT_SHIFT_ROM_PGE) & BIT_ROM_PGE;
0813     rtw_write32(rtwdev, REG_MCUFW_CTRL, val32);
0814 
0815     for (block = 0; block < block_nr; block++) {
0816         rtw_write32(rtwdev, write_addr, le32_to_cpu(*ptr));
0817 
0818         write_addr += DLFW_BLK_SIZE_LEGACY;
0819         ptr++;
0820     }
0821 
0822     if (remain_size) {
0823         memcpy(&remain_data, ptr, remain_size);
0824         rtw_write32(rtwdev, write_addr, le32_to_cpu(remain_data));
0825     }
0826 }
0827 
0828 static int
0829 download_firmware_legacy(struct rtw_dev *rtwdev, const u8 *data, u32 size)
0830 {
0831     u32 page;
0832     u32 total_page;
0833     u32 last_page_size;
0834 
0835     data += sizeof(struct rtw_fw_hdr_legacy);
0836     size -= sizeof(struct rtw_fw_hdr_legacy);
0837 
0838     total_page = size >> DLFW_PAGE_SIZE_SHIFT_LEGACY;
0839     last_page_size = size & (DLFW_PAGE_SIZE_LEGACY - 1);
0840 
0841     rtw_write8_set(rtwdev, REG_MCUFW_CTRL, BIT_FWDL_CHK_RPT);
0842 
0843     for (page = 0; page < total_page; page++) {
0844         write_firmware_page(rtwdev, page, data, DLFW_PAGE_SIZE_LEGACY);
0845         data += DLFW_PAGE_SIZE_LEGACY;
0846     }
0847     if (last_page_size)
0848         write_firmware_page(rtwdev, page, data, last_page_size);
0849 
0850     if (!check_hw_ready(rtwdev, REG_MCUFW_CTRL, BIT_FWDL_CHK_RPT, 1)) {
0851         rtw_err(rtwdev, "failed to check download firmware report\n");
0852         return -EINVAL;
0853     }
0854 
0855     return 0;
0856 }
0857 
0858 static int download_firmware_validate_legacy(struct rtw_dev *rtwdev)
0859 {
0860     u32 val32;
0861     int try;
0862 
0863     val32 = rtw_read32(rtwdev, REG_MCUFW_CTRL);
0864     val32 |= BIT_MCUFWDL_RDY;
0865     val32 &= ~BIT_WINTINI_RDY;
0866     rtw_write32(rtwdev, REG_MCUFW_CTRL, val32);
0867 
0868     wlan_cpu_enable(rtwdev, false);
0869     wlan_cpu_enable(rtwdev, true);
0870 
0871     for (try = 0; try < 10; try++) {
0872         val32 = rtw_read32(rtwdev, REG_MCUFW_CTRL);
0873         if ((val32 & FW_READY_LEGACY) == FW_READY_LEGACY)
0874             return 0;
0875         msleep(20);
0876     }
0877 
0878     rtw_err(rtwdev, "failed to validate firmware\n");
0879     return -EINVAL;
0880 }
0881 
0882 static int __rtw_download_firmware_legacy(struct rtw_dev *rtwdev,
0883                       struct rtw_fw_state *fw)
0884 {
0885     int ret = 0;
0886 
0887     en_download_firmware_legacy(rtwdev, true);
0888     ret = download_firmware_legacy(rtwdev, fw->firmware->data, fw->firmware->size);
0889     en_download_firmware_legacy(rtwdev, false);
0890     if (ret)
0891         goto out;
0892 
0893     ret = download_firmware_validate_legacy(rtwdev);
0894     if (ret)
0895         goto out;
0896 
0897     /* reset desc and index */
0898     rtw_hci_setup(rtwdev);
0899 
0900     rtwdev->h2c.last_box_num = 0;
0901     rtwdev->h2c.seq = 0;
0902 
0903     set_bit(RTW_FLAG_FW_RUNNING, rtwdev->flags);
0904 
0905 out:
0906     return ret;
0907 }
0908 
0909 int rtw_download_firmware(struct rtw_dev *rtwdev, struct rtw_fw_state *fw)
0910 {
0911     if (rtw_chip_wcpu_11n(rtwdev))
0912         return __rtw_download_firmware_legacy(rtwdev, fw);
0913 
0914     return __rtw_download_firmware(rtwdev, fw);
0915 }
0916 
0917 static u32 get_priority_queues(struct rtw_dev *rtwdev, u32 queues)
0918 {
0919     const struct rtw_rqpn *rqpn = rtwdev->fifo.rqpn;
0920     u32 prio_queues = 0;
0921 
0922     if (queues & BIT(IEEE80211_AC_VO))
0923         prio_queues |= BIT(rqpn->dma_map_vo);
0924     if (queues & BIT(IEEE80211_AC_VI))
0925         prio_queues |= BIT(rqpn->dma_map_vi);
0926     if (queues & BIT(IEEE80211_AC_BE))
0927         prio_queues |= BIT(rqpn->dma_map_be);
0928     if (queues & BIT(IEEE80211_AC_BK))
0929         prio_queues |= BIT(rqpn->dma_map_bk);
0930 
0931     return prio_queues;
0932 }
0933 
0934 static void __rtw_mac_flush_prio_queue(struct rtw_dev *rtwdev,
0935                        u32 prio_queue, bool drop)
0936 {
0937     struct rtw_chip_info *chip = rtwdev->chip;
0938     const struct rtw_prioq_addr *addr;
0939     bool wsize;
0940     u16 avail_page, rsvd_page;
0941     int i;
0942 
0943     if (prio_queue >= RTW_DMA_MAPPING_MAX)
0944         return;
0945 
0946     addr = &chip->prioq_addrs->prio[prio_queue];
0947     wsize = chip->prioq_addrs->wsize;
0948 
0949     /* check if all of the reserved pages are available for 100 msecs */
0950     for (i = 0; i < 5; i++) {
0951         rsvd_page = wsize ? rtw_read16(rtwdev, addr->rsvd) :
0952                      rtw_read8(rtwdev, addr->rsvd);
0953         avail_page = wsize ? rtw_read16(rtwdev, addr->avail) :
0954                       rtw_read8(rtwdev, addr->avail);
0955         if (rsvd_page == avail_page)
0956             return;
0957 
0958         msleep(20);
0959     }
0960 
0961     /* priority queue is still not empty, throw a warning,
0962      *
0963      * Note that if we want to flush the tx queue when having a lot of
0964      * traffic (ex, 100Mbps up), some of the packets could be dropped.
0965      * And it requires like ~2secs to flush the full priority queue.
0966      */
0967     if (!drop)
0968         rtw_warn(rtwdev, "timed out to flush queue %d\n", prio_queue);
0969 }
0970 
0971 static void rtw_mac_flush_prio_queues(struct rtw_dev *rtwdev,
0972                       u32 prio_queues, bool drop)
0973 {
0974     u32 q;
0975 
0976     for (q = 0; q < RTW_DMA_MAPPING_MAX; q++)
0977         if (prio_queues & BIT(q))
0978             __rtw_mac_flush_prio_queue(rtwdev, q, drop);
0979 }
0980 
0981 void rtw_mac_flush_queues(struct rtw_dev *rtwdev, u32 queues, bool drop)
0982 {
0983     u32 prio_queues = 0;
0984 
0985     /* If all of the hardware queues are requested to flush,
0986      * or the priority queues are not mapped yet,
0987      * flush all of the priority queues
0988      */
0989     if (queues == BIT(rtwdev->hw->queues) - 1 || !rtwdev->fifo.rqpn)
0990         prio_queues = BIT(RTW_DMA_MAPPING_MAX) - 1;
0991     else
0992         prio_queues = get_priority_queues(rtwdev, queues);
0993 
0994     rtw_mac_flush_prio_queues(rtwdev, prio_queues, drop);
0995 }
0996 
0997 static int txdma_queue_mapping(struct rtw_dev *rtwdev)
0998 {
0999     struct rtw_chip_info *chip = rtwdev->chip;
1000     const struct rtw_rqpn *rqpn = NULL;
1001     u16 txdma_pq_map = 0;
1002 
1003     switch (rtw_hci_type(rtwdev)) {
1004     case RTW_HCI_TYPE_PCIE:
1005         rqpn = &chip->rqpn_table[1];
1006         break;
1007     case RTW_HCI_TYPE_USB:
1008         if (rtwdev->hci.bulkout_num == 2)
1009             rqpn = &chip->rqpn_table[2];
1010         else if (rtwdev->hci.bulkout_num == 3)
1011             rqpn = &chip->rqpn_table[3];
1012         else if (rtwdev->hci.bulkout_num == 4)
1013             rqpn = &chip->rqpn_table[4];
1014         else
1015             return -EINVAL;
1016         break;
1017     default:
1018         return -EINVAL;
1019     }
1020 
1021     rtwdev->fifo.rqpn = rqpn;
1022     txdma_pq_map |= BIT_TXDMA_HIQ_MAP(rqpn->dma_map_hi);
1023     txdma_pq_map |= BIT_TXDMA_MGQ_MAP(rqpn->dma_map_mg);
1024     txdma_pq_map |= BIT_TXDMA_BKQ_MAP(rqpn->dma_map_bk);
1025     txdma_pq_map |= BIT_TXDMA_BEQ_MAP(rqpn->dma_map_be);
1026     txdma_pq_map |= BIT_TXDMA_VIQ_MAP(rqpn->dma_map_vi);
1027     txdma_pq_map |= BIT_TXDMA_VOQ_MAP(rqpn->dma_map_vo);
1028     rtw_write16(rtwdev, REG_TXDMA_PQ_MAP, txdma_pq_map);
1029 
1030     rtw_write8(rtwdev, REG_CR, 0);
1031     rtw_write8(rtwdev, REG_CR, MAC_TRX_ENABLE);
1032     if (rtw_chip_wcpu_11ac(rtwdev))
1033         rtw_write32(rtwdev, REG_H2CQ_CSR, BIT_H2CQ_FULL);
1034 
1035     return 0;
1036 }
1037 
1038 static int set_trx_fifo_info(struct rtw_dev *rtwdev)
1039 {
1040     struct rtw_fifo_conf *fifo = &rtwdev->fifo;
1041     struct rtw_chip_info *chip = rtwdev->chip;
1042     u16 cur_pg_addr;
1043     u8 csi_buf_pg_num = chip->csi_buf_pg_num;
1044 
1045     /* config rsvd page num */
1046     fifo->rsvd_drv_pg_num = 8;
1047     fifo->txff_pg_num = chip->txff_size >> 7;
1048     if (rtw_chip_wcpu_11n(rtwdev))
1049         fifo->rsvd_pg_num = fifo->rsvd_drv_pg_num;
1050     else
1051         fifo->rsvd_pg_num = fifo->rsvd_drv_pg_num +
1052                    RSVD_PG_H2C_EXTRAINFO_NUM +
1053                    RSVD_PG_H2C_STATICINFO_NUM +
1054                    RSVD_PG_H2CQ_NUM +
1055                    RSVD_PG_CPU_INSTRUCTION_NUM +
1056                    RSVD_PG_FW_TXBUF_NUM +
1057                    csi_buf_pg_num;
1058 
1059     if (fifo->rsvd_pg_num > fifo->txff_pg_num)
1060         return -ENOMEM;
1061 
1062     fifo->acq_pg_num = fifo->txff_pg_num - fifo->rsvd_pg_num;
1063     fifo->rsvd_boundary = fifo->txff_pg_num - fifo->rsvd_pg_num;
1064 
1065     cur_pg_addr = fifo->txff_pg_num;
1066     if (rtw_chip_wcpu_11ac(rtwdev)) {
1067         cur_pg_addr -= csi_buf_pg_num;
1068         fifo->rsvd_csibuf_addr = cur_pg_addr;
1069         cur_pg_addr -= RSVD_PG_FW_TXBUF_NUM;
1070         fifo->rsvd_fw_txbuf_addr = cur_pg_addr;
1071         cur_pg_addr -= RSVD_PG_CPU_INSTRUCTION_NUM;
1072         fifo->rsvd_cpu_instr_addr = cur_pg_addr;
1073         cur_pg_addr -= RSVD_PG_H2CQ_NUM;
1074         fifo->rsvd_h2cq_addr = cur_pg_addr;
1075         cur_pg_addr -= RSVD_PG_H2C_STATICINFO_NUM;
1076         fifo->rsvd_h2c_sta_info_addr = cur_pg_addr;
1077         cur_pg_addr -= RSVD_PG_H2C_EXTRAINFO_NUM;
1078         fifo->rsvd_h2c_info_addr = cur_pg_addr;
1079     }
1080     cur_pg_addr -= fifo->rsvd_drv_pg_num;
1081     fifo->rsvd_drv_addr = cur_pg_addr;
1082 
1083     if (fifo->rsvd_boundary != fifo->rsvd_drv_addr) {
1084         rtw_err(rtwdev, "wrong rsvd driver address\n");
1085         return -EINVAL;
1086     }
1087 
1088     return 0;
1089 }
1090 
1091 static int __priority_queue_cfg(struct rtw_dev *rtwdev,
1092                 const struct rtw_page_table *pg_tbl,
1093                 u16 pubq_num)
1094 {
1095     struct rtw_fifo_conf *fifo = &rtwdev->fifo;
1096     struct rtw_chip_info *chip = rtwdev->chip;
1097 
1098     rtw_write16(rtwdev, REG_FIFOPAGE_INFO_1, pg_tbl->hq_num);
1099     rtw_write16(rtwdev, REG_FIFOPAGE_INFO_2, pg_tbl->lq_num);
1100     rtw_write16(rtwdev, REG_FIFOPAGE_INFO_3, pg_tbl->nq_num);
1101     rtw_write16(rtwdev, REG_FIFOPAGE_INFO_4, pg_tbl->exq_num);
1102     rtw_write16(rtwdev, REG_FIFOPAGE_INFO_5, pubq_num);
1103     rtw_write32_set(rtwdev, REG_RQPN_CTRL_2, BIT_LD_RQPN);
1104 
1105     rtw_write16(rtwdev, REG_FIFOPAGE_CTRL_2, fifo->rsvd_boundary);
1106     rtw_write8_set(rtwdev, REG_FWHW_TXQ_CTRL + 2, BIT_EN_WR_FREE_TAIL >> 16);
1107 
1108     rtw_write16(rtwdev, REG_BCNQ_BDNY_V1, fifo->rsvd_boundary);
1109     rtw_write16(rtwdev, REG_FIFOPAGE_CTRL_2 + 2, fifo->rsvd_boundary);
1110     rtw_write16(rtwdev, REG_BCNQ1_BDNY_V1, fifo->rsvd_boundary);
1111     rtw_write32(rtwdev, REG_RXFF_BNDY, chip->rxff_size - C2H_PKT_BUF - 1);
1112     rtw_write8_set(rtwdev, REG_AUTO_LLT_V1, BIT_AUTO_INIT_LLT_V1);
1113 
1114     if (!check_hw_ready(rtwdev, REG_AUTO_LLT_V1, BIT_AUTO_INIT_LLT_V1, 0))
1115         return -EBUSY;
1116 
1117     rtw_write8(rtwdev, REG_CR + 3, 0);
1118 
1119     return 0;
1120 }
1121 
1122 static int __priority_queue_cfg_legacy(struct rtw_dev *rtwdev,
1123                        const struct rtw_page_table *pg_tbl,
1124                        u16 pubq_num)
1125 {
1126     struct rtw_fifo_conf *fifo = &rtwdev->fifo;
1127     struct rtw_chip_info *chip = rtwdev->chip;
1128     u32 val32;
1129 
1130     val32 = BIT_RQPN_NE(pg_tbl->nq_num, pg_tbl->exq_num);
1131     rtw_write32(rtwdev, REG_RQPN_NPQ, val32);
1132     val32 = BIT_RQPN_HLP(pg_tbl->hq_num, pg_tbl->lq_num, pubq_num);
1133     rtw_write32(rtwdev, REG_RQPN, val32);
1134 
1135     rtw_write8(rtwdev, REG_TRXFF_BNDY, fifo->rsvd_boundary);
1136     rtw_write16(rtwdev, REG_TRXFF_BNDY + 2, chip->rxff_size - REPORT_BUF - 1);
1137     rtw_write8(rtwdev, REG_DWBCN0_CTRL + 1, fifo->rsvd_boundary);
1138     rtw_write8(rtwdev, REG_BCNQ_BDNY, fifo->rsvd_boundary);
1139     rtw_write8(rtwdev, REG_MGQ_BDNY, fifo->rsvd_boundary);
1140     rtw_write8(rtwdev, REG_WMAC_LBK_BF_HD, fifo->rsvd_boundary);
1141 
1142     rtw_write32_set(rtwdev, REG_AUTO_LLT, BIT_AUTO_INIT_LLT);
1143 
1144     if (!check_hw_ready(rtwdev, REG_AUTO_LLT, BIT_AUTO_INIT_LLT, 0))
1145         return -EBUSY;
1146 
1147     return 0;
1148 }
1149 
1150 static int priority_queue_cfg(struct rtw_dev *rtwdev)
1151 {
1152     struct rtw_fifo_conf *fifo = &rtwdev->fifo;
1153     struct rtw_chip_info *chip = rtwdev->chip;
1154     const struct rtw_page_table *pg_tbl = NULL;
1155     u16 pubq_num;
1156     int ret;
1157 
1158     ret = set_trx_fifo_info(rtwdev);
1159     if (ret)
1160         return ret;
1161 
1162     switch (rtw_hci_type(rtwdev)) {
1163     case RTW_HCI_TYPE_PCIE:
1164         pg_tbl = &chip->page_table[1];
1165         break;
1166     case RTW_HCI_TYPE_USB:
1167         if (rtwdev->hci.bulkout_num == 2)
1168             pg_tbl = &chip->page_table[2];
1169         else if (rtwdev->hci.bulkout_num == 3)
1170             pg_tbl = &chip->page_table[3];
1171         else if (rtwdev->hci.bulkout_num == 4)
1172             pg_tbl = &chip->page_table[4];
1173         else
1174             return -EINVAL;
1175         break;
1176     default:
1177         return -EINVAL;
1178     }
1179 
1180     pubq_num = fifo->acq_pg_num - pg_tbl->hq_num - pg_tbl->lq_num -
1181            pg_tbl->nq_num - pg_tbl->exq_num - pg_tbl->gapq_num;
1182     if (rtw_chip_wcpu_11n(rtwdev))
1183         return __priority_queue_cfg_legacy(rtwdev, pg_tbl, pubq_num);
1184     else
1185         return __priority_queue_cfg(rtwdev, pg_tbl, pubq_num);
1186 }
1187 
1188 static int init_h2c(struct rtw_dev *rtwdev)
1189 {
1190     struct rtw_fifo_conf *fifo = &rtwdev->fifo;
1191     u8 value8;
1192     u32 value32;
1193     u32 h2cq_addr;
1194     u32 h2cq_size;
1195     u32 h2cq_free;
1196     u32 wp, rp;
1197 
1198     if (rtw_chip_wcpu_11n(rtwdev))
1199         return 0;
1200 
1201     h2cq_addr = fifo->rsvd_h2cq_addr << TX_PAGE_SIZE_SHIFT;
1202     h2cq_size = RSVD_PG_H2CQ_NUM << TX_PAGE_SIZE_SHIFT;
1203 
1204     value32 = rtw_read32(rtwdev, REG_H2C_HEAD);
1205     value32 = (value32 & 0xFFFC0000) | h2cq_addr;
1206     rtw_write32(rtwdev, REG_H2C_HEAD, value32);
1207 
1208     value32 = rtw_read32(rtwdev, REG_H2C_READ_ADDR);
1209     value32 = (value32 & 0xFFFC0000) | h2cq_addr;
1210     rtw_write32(rtwdev, REG_H2C_READ_ADDR, value32);
1211 
1212     value32 = rtw_read32(rtwdev, REG_H2C_TAIL);
1213     value32 &= 0xFFFC0000;
1214     value32 |= (h2cq_addr + h2cq_size);
1215     rtw_write32(rtwdev, REG_H2C_TAIL, value32);
1216 
1217     value8 = rtw_read8(rtwdev, REG_H2C_INFO);
1218     value8 = (u8)((value8 & 0xFC) | 0x01);
1219     rtw_write8(rtwdev, REG_H2C_INFO, value8);
1220 
1221     value8 = rtw_read8(rtwdev, REG_H2C_INFO);
1222     value8 = (u8)((value8 & 0xFB) | 0x04);
1223     rtw_write8(rtwdev, REG_H2C_INFO, value8);
1224 
1225     value8 = rtw_read8(rtwdev, REG_TXDMA_OFFSET_CHK + 1);
1226     value8 = (u8)((value8 & 0x7f) | 0x80);
1227     rtw_write8(rtwdev, REG_TXDMA_OFFSET_CHK + 1, value8);
1228 
1229     wp = rtw_read32(rtwdev, REG_H2C_PKT_WRITEADDR) & 0x3FFFF;
1230     rp = rtw_read32(rtwdev, REG_H2C_PKT_READADDR) & 0x3FFFF;
1231     h2cq_free = wp >= rp ? h2cq_size - (wp - rp) : rp - wp;
1232 
1233     if (h2cq_size != h2cq_free) {
1234         rtw_err(rtwdev, "H2C queue mismatch\n");
1235         return -EINVAL;
1236     }
1237 
1238     return 0;
1239 }
1240 
1241 static int rtw_init_trx_cfg(struct rtw_dev *rtwdev)
1242 {
1243     int ret;
1244 
1245     ret = txdma_queue_mapping(rtwdev);
1246     if (ret)
1247         return ret;
1248 
1249     ret = priority_queue_cfg(rtwdev);
1250     if (ret)
1251         return ret;
1252 
1253     ret = init_h2c(rtwdev);
1254     if (ret)
1255         return ret;
1256 
1257     return 0;
1258 }
1259 
1260 static int rtw_drv_info_cfg(struct rtw_dev *rtwdev)
1261 {
1262     u8 value8;
1263 
1264     rtw_write8(rtwdev, REG_RX_DRVINFO_SZ, PHY_STATUS_SIZE);
1265     if (rtw_chip_wcpu_11ac(rtwdev)) {
1266         value8 = rtw_read8(rtwdev, REG_TRXFF_BNDY + 1);
1267         value8 &= 0xF0;
1268         /* For rxdesc len = 0 issue */
1269         value8 |= 0xF;
1270         rtw_write8(rtwdev, REG_TRXFF_BNDY + 1, value8);
1271     }
1272     rtw_write32_set(rtwdev, REG_RCR, BIT_APP_PHYSTS);
1273     rtw_write32_clr(rtwdev, REG_WMAC_OPTION_FUNCTION + 4, BIT(8) | BIT(9));
1274 
1275     return 0;
1276 }
1277 
1278 int rtw_mac_init(struct rtw_dev *rtwdev)
1279 {
1280     struct rtw_chip_info *chip = rtwdev->chip;
1281     int ret;
1282 
1283     ret = rtw_init_trx_cfg(rtwdev);
1284     if (ret)
1285         return ret;
1286 
1287     ret = chip->ops->mac_init(rtwdev);
1288     if (ret)
1289         return ret;
1290 
1291     ret = rtw_drv_info_cfg(rtwdev);
1292     if (ret)
1293         return ret;
1294 
1295     rtw_hci_interface_cfg(rtwdev);
1296 
1297     return 0;
1298 }
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