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0001 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
0002 /* Copyright(c) 2018-2019  Realtek Corporation
0003  */
0004 
0005 #ifndef __RTW_FW_H_
0006 #define __RTW_FW_H_
0007 
0008 #define H2C_PKT_SIZE        32
0009 #define H2C_PKT_HDR_SIZE    8
0010 
0011 /* FW bin information */
0012 #define FW_HDR_SIZE         64
0013 #define FW_HDR_CHKSUM_SIZE      8
0014 
0015 #define FW_NLO_INFO_CHECK_SIZE      4
0016 
0017 #define FIFO_PAGE_SIZE_SHIFT        12
0018 #define FIFO_PAGE_SIZE          4096
0019 #define FIFO_DUMP_ADDR          0x8000
0020 
0021 #define DLFW_PAGE_SIZE_SHIFT_LEGACY 12
0022 #define DLFW_PAGE_SIZE_LEGACY       0x1000
0023 #define DLFW_BLK_SIZE_SHIFT_LEGACY  2
0024 #define DLFW_BLK_SIZE_LEGACY        4
0025 #define FW_START_ADDR_LEGACY        0x1000
0026 
0027 #define BCN_LOSS_CNT            10
0028 #define BCN_FILTER_NOTIFY_SIGNAL_CHANGE 0
0029 #define BCN_FILTER_CONNECTION_LOSS  1
0030 #define BCN_FILTER_CONNECTED        2
0031 #define BCN_FILTER_NOTIFY_BEACON_LOSS   3
0032 
0033 #define SCAN_NOTIFY_TIMEOUT  msecs_to_jiffies(10)
0034 
0035 #define RTW_CHANNEL_TIME        45
0036 #define RTW_OFF_CHAN_TIME       100
0037 #define RTW_PASS_CHAN_TIME      105
0038 #define RTW_DFS_CHAN_TIME       20
0039 #define RTW_CH_INFO_SIZE        4
0040 #define RTW_EX_CH_INFO_SIZE     3
0041 #define RTW_EX_CH_INFO_HDR_SIZE     2
0042 #define RTW_SCAN_WIDTH          0
0043 #define RTW_PRI_CH_IDX          1
0044 #define RTW_PROBE_PG_CNT        2
0045 
0046 enum rtw_c2h_cmd_id {
0047     C2H_CCX_TX_RPT = 0x03,
0048     C2H_BT_INFO = 0x09,
0049     C2H_BT_MP_INFO = 0x0b,
0050     C2H_BT_HID_INFO = 0x45,
0051     C2H_RA_RPT = 0x0c,
0052     C2H_HW_FEATURE_REPORT = 0x19,
0053     C2H_WLAN_INFO = 0x27,
0054     C2H_WLAN_RFON = 0x32,
0055     C2H_BCN_FILTER_NOTIFY = 0x36,
0056     C2H_ADAPTIVITY = 0x37,
0057     C2H_SCAN_RESULT = 0x38,
0058     C2H_HW_FEATURE_DUMP = 0xfd,
0059     C2H_HALMAC = 0xff,
0060 };
0061 
0062 enum rtw_c2h_cmd_id_ext {
0063     C2H_SCAN_STATUS_RPT = 0x3,
0064     C2H_CCX_RPT = 0x0f,
0065     C2H_CHAN_SWITCH = 0x22,
0066 };
0067 
0068 struct rtw_c2h_cmd {
0069     u8 id;
0070     u8 seq;
0071     u8 payload[];
0072 } __packed;
0073 
0074 struct rtw_c2h_adaptivity {
0075     u8 density;
0076     u8 igi;
0077     u8 l2h_th_init;
0078     u8 l2h;
0079     u8 h2l;
0080     u8 option;
0081 } __packed;
0082 
0083 enum rtw_rsvd_packet_type {
0084     RSVD_BEACON,
0085     RSVD_DUMMY,
0086     RSVD_PS_POLL,
0087     RSVD_PROBE_RESP,
0088     RSVD_NULL,
0089     RSVD_QOS_NULL,
0090     RSVD_LPS_PG_DPK,
0091     RSVD_LPS_PG_INFO,
0092     RSVD_PROBE_REQ,
0093     RSVD_NLO_INFO,
0094     RSVD_CH_INFO,
0095 };
0096 
0097 enum rtw_fw_rf_type {
0098     FW_RF_1T2R = 0,
0099     FW_RF_2T4R = 1,
0100     FW_RF_2T2R = 2,
0101     FW_RF_2T3R = 3,
0102     FW_RF_1T1R = 4,
0103     FW_RF_2T2R_GREEN = 5,
0104     FW_RF_3T3R = 6,
0105     FW_RF_3T4R = 7,
0106     FW_RF_4T4R = 8,
0107     FW_RF_MAX_TYPE = 0xF,
0108 };
0109 
0110 enum rtw_fw_feature {
0111     FW_FEATURE_SIG = BIT(0),
0112     FW_FEATURE_LPS_C2H = BIT(1),
0113     FW_FEATURE_LCLK = BIT(2),
0114     FW_FEATURE_PG = BIT(3),
0115     FW_FEATURE_TX_WAKE = BIT(4),
0116     FW_FEATURE_BCN_FILTER = BIT(5),
0117     FW_FEATURE_NOTIFY_SCAN = BIT(6),
0118     FW_FEATURE_ADAPTIVITY = BIT(7),
0119     FW_FEATURE_SCAN_OFFLOAD = BIT(8),
0120     FW_FEATURE_MAX = BIT(31),
0121 };
0122 
0123 enum rtw_beacon_filter_offload_mode {
0124     BCN_FILTER_OFFLOAD_MODE_0 = 0,
0125     BCN_FILTER_OFFLOAD_MODE_1,
0126     BCN_FILTER_OFFLOAD_MODE_2,
0127     BCN_FILTER_OFFLOAD_MODE_3,
0128 
0129     BCN_FILTER_OFFLOAD_MODE_DEFAULT = BCN_FILTER_OFFLOAD_MODE_0,
0130 };
0131 
0132 struct rtw_coex_info_req {
0133     u8 seq;
0134     u8 op_code;
0135     u8 para1;
0136     u8 para2;
0137     u8 para3;
0138 };
0139 
0140 struct rtw_iqk_para {
0141     u8 clear;
0142     u8 segment_iqk;
0143 };
0144 
0145 struct rtw_lps_pg_dpk_hdr {
0146     u16 dpk_path_ok;
0147     u8 dpk_txagc[2];
0148     u16 dpk_gs[2];
0149     u32 coef[2][20];
0150     u8 dpk_ch;
0151 } __packed;
0152 
0153 struct rtw_lps_pg_info_hdr {
0154     u8 macid;
0155     u8 mbssid;
0156     u8 pattern_count;
0157     u8 mu_tab_group_id;
0158     u8 sec_cam_count;
0159     u8 tx_bu_page_count;
0160     u16 rsvd;
0161     u8 sec_cam[MAX_PG_CAM_BACKUP_NUM];
0162 } __packed;
0163 
0164 struct rtw_rsvd_page {
0165     /* associated with each vif */
0166     struct list_head vif_list;
0167     struct rtw_vif *rtwvif;
0168 
0169     /* associated when build rsvd page */
0170     struct list_head build_list;
0171 
0172     struct sk_buff *skb;
0173     enum rtw_rsvd_packet_type type;
0174     u8 page;
0175     u16 tim_offset;
0176     bool add_txdesc;
0177     struct cfg80211_ssid *ssid;
0178     u16 probe_req_size;
0179 };
0180 
0181 enum rtw_keep_alive_pkt_type {
0182     KEEP_ALIVE_NULL_PKT = 0,
0183     KEEP_ALIVE_ARP_RSP = 1,
0184 };
0185 
0186 struct rtw_nlo_info_hdr {
0187     u8 nlo_count;
0188     u8 hidden_ap_count;
0189     u8 rsvd1[2];
0190     u8 pattern_check[FW_NLO_INFO_CHECK_SIZE];
0191     u8 rsvd2[8];
0192     u8 ssid_len[16];
0193     u8 chiper[16];
0194     u8 rsvd3[16];
0195     u8 location[8];
0196 } __packed;
0197 
0198 enum rtw_packet_type {
0199     RTW_PACKET_PROBE_REQ = 0x00,
0200 
0201     RTW_PACKET_UNDEFINE = 0x7FFFFFFF,
0202 };
0203 
0204 struct rtw_fw_wow_keep_alive_para {
0205     bool adopt;
0206     u8 pkt_type;
0207     u8 period;      /* unit: sec */
0208 };
0209 
0210 struct rtw_fw_wow_disconnect_para {
0211     bool adopt;
0212     u8 period;      /* unit: sec */
0213     u8 retry_count;
0214 };
0215 
0216 enum rtw_channel_type {
0217     RTW_CHANNEL_PASSIVE,
0218     RTW_CHANNEL_ACTIVE,
0219     RTW_CHANNEL_RADAR,
0220 };
0221 
0222 enum rtw_scan_extra_id {
0223     RTW_SCAN_EXTRA_ID_DFS,
0224 };
0225 
0226 enum rtw_scan_extra_info {
0227     RTW_SCAN_EXTRA_ACTION_SCAN,
0228 };
0229 
0230 enum rtw_scan_report_code {
0231     RTW_SCAN_REPORT_SUCCESS = 0x00,
0232     RTW_SCAN_REPORT_ERR_PHYDM = 0x01,
0233     RTW_SCAN_REPORT_ERR_ID = 0x02,
0234     RTW_SCAN_REPORT_ERR_TX = 0x03,
0235     RTW_SCAN_REPORT_CANCELED = 0x10,
0236     RTW_SCAN_REPORT_CANCELED_EXT = 0x11,
0237     RTW_SCAN_REPORT_FW_DISABLED = 0xF0,
0238 };
0239 
0240 enum rtw_scan_notify_id {
0241     RTW_SCAN_NOTIFY_ID_PRESWITCH = 0x00,
0242     RTW_SCAN_NOTIFY_ID_POSTSWITCH = 0x01,
0243     RTW_SCAN_NOTIFY_ID_PROBE_PRETX = 0x02,
0244     RTW_SCAN_NOTIFY_ID_PROBE_ISSUETX = 0x03,
0245     RTW_SCAN_NOTIFY_ID_NULL0_PRETX = 0x04,
0246     RTW_SCAN_NOTIFY_ID_NULL0_ISSUETX = 0x05,
0247     RTW_SCAN_NOTIFY_ID_NULL0_POSTTX = 0x06,
0248     RTW_SCAN_NOTIFY_ID_NULL1_PRETX = 0x07,
0249     RTW_SCAN_NOTIFY_ID_NULL1_ISSUETX = 0x08,
0250     RTW_SCAN_NOTIFY_ID_NULL1_POSTTX = 0x09,
0251     RTW_SCAN_NOTIFY_ID_DWELLEXT = 0x0A,
0252 };
0253 
0254 enum rtw_scan_notify_status {
0255     RTW_SCAN_NOTIFY_STATUS_SUCCESS = 0x00,
0256     RTW_SCAN_NOTIFY_STATUS_FAILURE = 0x01,
0257     RTW_SCAN_NOTIFY_STATUS_RESOURCE = 0x02,
0258     RTW_SCAN_NOTIFY_STATUS_TIMEOUT = 0x03,
0259 };
0260 
0261 struct rtw_ch_switch_option {
0262     u8 periodic_option;
0263     u32 tsf_high;
0264     u32 tsf_low;
0265     u8 dest_ch_en;
0266     u8 absolute_time_en;
0267     u8 dest_ch;
0268     u8 normal_period;
0269     u8 normal_period_sel;
0270     u8 normal_cycle;
0271     u8 slow_period;
0272     u8 slow_period_sel;
0273     u8 nlo_en;
0274     bool switch_en;
0275     bool back_op_en;
0276 };
0277 
0278 struct rtw_fw_hdr {
0279     __le16 signature;
0280     u8 category;
0281     u8 function;
0282     __le16 version;     /* 0x04 */
0283     u8 subversion;
0284     u8 subindex;
0285     __le32 rsvd;        /* 0x08 */
0286     __le32 feature;     /* 0x0C */
0287     u8 month;       /* 0x10 */
0288     u8 day;
0289     u8 hour;
0290     u8 min;
0291     __le16 year;        /* 0x14 */
0292     __le16 rsvd3;
0293     u8 mem_usage;       /* 0x18 */
0294     u8 rsvd4[3];
0295     __le16 h2c_fmt_ver; /* 0x1C */
0296     __le16 rsvd5;
0297     __le32 dmem_addr;   /* 0x20 */
0298     __le32 dmem_size;
0299     __le32 rsvd6;
0300     __le32 rsvd7;
0301     __le32 imem_size;   /* 0x30 */
0302     __le32 emem_size;
0303     __le32 emem_addr;
0304     __le32 imem_addr;
0305 } __packed;
0306 
0307 struct rtw_fw_hdr_legacy {
0308     __le16 signature;
0309     u8 category;
0310     u8 function;
0311     __le16 version; /* 0x04 */
0312     u8 subversion1;
0313     u8 subversion2;
0314     u8 month;   /* 0x08 */
0315     u8 day;
0316     u8 hour;
0317     u8 minute;
0318     __le16 size;
0319     __le16 rsvd2;
0320     __le32 idx; /* 0x10 */
0321     __le32 rsvd3;
0322     __le32 rsvd4;   /* 0x18 */
0323     __le32 rsvd5;
0324 } __packed;
0325 
0326 /* C2H */
0327 #define GET_CCX_REPORT_SEQNUM_V0(c2h_payload)   (c2h_payload[6] & 0xfc)
0328 #define GET_CCX_REPORT_STATUS_V0(c2h_payload)   (c2h_payload[0] & 0xc0)
0329 #define GET_CCX_REPORT_SEQNUM_V1(c2h_payload)   (c2h_payload[8] & 0xfc)
0330 #define GET_CCX_REPORT_STATUS_V1(c2h_payload)   (c2h_payload[9] & 0xc0)
0331 
0332 #define GET_SCAN_REPORT_RETURN_CODE(c2h_payload)    (c2h_payload[2] & 0xff)
0333 
0334 #define GET_CHAN_SWITCH_CENTRAL_CH(c2h_payload) (c2h_payload[2])
0335 #define GET_CHAN_SWITCH_ID(c2h_payload)     (c2h_payload[3])
0336 #define GET_CHAN_SWITCH_STATUS(c2h_payload) (c2h_payload[4])
0337 #define GET_RA_REPORT_RATE(c2h_payload)     (c2h_payload[0] & 0x7f)
0338 #define GET_RA_REPORT_SGI(c2h_payload)      ((c2h_payload[0] & 0x80) >> 7)
0339 #define GET_RA_REPORT_BW(c2h_payload)       (c2h_payload[6])
0340 #define GET_RA_REPORT_MACID(c2h_payload)    (c2h_payload[1])
0341 
0342 #define GET_BCN_FILTER_NOTIFY_TYPE(c2h_payload) (c2h_payload[1] & 0xf)
0343 #define GET_BCN_FILTER_NOTIFY_EVENT(c2h_payload)    (c2h_payload[1] & 0x10)
0344 #define GET_BCN_FILTER_NOTIFY_RSSI(c2h_payload) (c2h_payload[2] - 100)
0345 
0346 /* PKT H2C */
0347 #define H2C_PKT_CMD_ID 0xFF
0348 #define H2C_PKT_CATEGORY 0x01
0349 
0350 #define H2C_PKT_GENERAL_INFO 0x0D
0351 #define H2C_PKT_PHYDM_INFO 0x11
0352 #define H2C_PKT_IQK 0x0E
0353 
0354 #define H2C_PKT_CH_SWITCH 0x02
0355 #define H2C_PKT_UPDATE_PKT 0x0C
0356 #define H2C_PKT_SCAN_OFFLOAD 0x19
0357 
0358 #define H2C_PKT_CH_SWITCH_LEN 0x20
0359 #define H2C_PKT_UPDATE_PKT_LEN 0x4
0360 
0361 #define SET_PKT_H2C_CATEGORY(h2c_pkt, value)                                   \
0362     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(6, 0))
0363 #define SET_PKT_H2C_CMD_ID(h2c_pkt, value)                                     \
0364     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
0365 #define SET_PKT_H2C_SUB_CMD_ID(h2c_pkt, value)                                 \
0366     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 16))
0367 #define SET_PKT_H2C_TOTAL_LEN(h2c_pkt, value)                                  \
0368     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 0))
0369 
0370 static inline void rtw_h2c_pkt_set_header(u8 *h2c_pkt, u8 sub_id)
0371 {
0372     SET_PKT_H2C_CATEGORY(h2c_pkt, H2C_PKT_CATEGORY);
0373     SET_PKT_H2C_CMD_ID(h2c_pkt, H2C_PKT_CMD_ID);
0374     SET_PKT_H2C_SUB_CMD_ID(h2c_pkt, sub_id);
0375 }
0376 
0377 #define FW_OFFLOAD_H2C_SET_SEQ_NUM(h2c_pkt, value)                             \
0378     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(31, 16))
0379 #define GENERAL_INFO_SET_FW_TX_BOUNDARY(h2c_pkt, value)                        \
0380     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(23, 16))
0381 
0382 #define PHYDM_INFO_SET_REF_TYPE(h2c_pkt, value)                                \
0383     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(7, 0))
0384 #define PHYDM_INFO_SET_RF_TYPE(h2c_pkt, value)                                 \
0385     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(15, 8))
0386 #define PHYDM_INFO_SET_CUT_VER(h2c_pkt, value)                                 \
0387     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(23, 16))
0388 #define PHYDM_INFO_SET_RX_ANT_STATUS(h2c_pkt, value)                           \
0389     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(27, 24))
0390 #define PHYDM_INFO_SET_TX_ANT_STATUS(h2c_pkt, value)                           \
0391     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(31, 28))
0392 #define IQK_SET_CLEAR(h2c_pkt, value)                                          \
0393     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(0))
0394 #define IQK_SET_SEGMENT_IQK(h2c_pkt, value)                                    \
0395     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(1))
0396 
0397 #define CHSW_INFO_SET_CH(pkt, value)                           \
0398     le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(7, 0))
0399 #define CHSW_INFO_SET_PRI_CH_IDX(pkt, value)                       \
0400     le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(11, 8))
0401 #define CHSW_INFO_SET_BW(pkt, value)                           \
0402     le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(15, 12))
0403 #define CHSW_INFO_SET_TIMEOUT(pkt, value)                      \
0404     le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(23, 16))
0405 #define CHSW_INFO_SET_ACTION_ID(pkt, value)                    \
0406     le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(30, 24))
0407 #define CHSW_INFO_SET_EXTRA_INFO(pkt, value)                       \
0408     le32p_replace_bits((__le32 *)(pkt) + 0x00, value, BIT(31))
0409 
0410 #define CH_INFO_SET_CH(pkt, value)                         \
0411     u8p_replace_bits((u8 *)(pkt) + 0x00, value, GENMASK(7, 0))
0412 #define CH_INFO_SET_PRI_CH_IDX(pkt, value)                     \
0413     u8p_replace_bits((u8 *)(pkt) + 0x01, value, GENMASK(3, 0))
0414 #define CH_INFO_SET_BW(pkt, value)                         \
0415     u8p_replace_bits((u8 *)(pkt) + 0x01, value, GENMASK(7, 4))
0416 #define CH_INFO_SET_TIMEOUT(pkt, value)                        \
0417     u8p_replace_bits((u8 *)(pkt) + 0x02, value, GENMASK(7, 0))
0418 #define CH_INFO_SET_ACTION_ID(pkt, value)                      \
0419     u8p_replace_bits((u8 *)(pkt) + 0x03, value, GENMASK(6, 0))
0420 #define CH_INFO_SET_EXTRA_INFO(pkt, value)                     \
0421     u8p_replace_bits((u8 *)(pkt) + 0x03, value, BIT(7))
0422 
0423 #define EXTRA_CH_INFO_SET_ID(pkt, value)                       \
0424     u8p_replace_bits((u8 *)(pkt) + 0x04, value, GENMASK(6, 0))
0425 #define EXTRA_CH_INFO_SET_INFO(pkt, value)                     \
0426     u8p_replace_bits((u8 *)(pkt) + 0x04, value, BIT(7))
0427 #define EXTRA_CH_INFO_SET_SIZE(pkt, value)                     \
0428     u8p_replace_bits((u8 *)(pkt) + 0x05, value, GENMASK(7, 0))
0429 #define EXTRA_CH_INFO_SET_DFS_EXT_TIME(pkt, value)                 \
0430     u8p_replace_bits((u8 *)(pkt) + 0x06, value, GENMASK(7, 0))
0431 
0432 #define UPDATE_PKT_SET_SIZE(h2c_pkt, value)                    \
0433     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(15, 0))
0434 #define UPDATE_PKT_SET_PKT_ID(h2c_pkt, value)                      \
0435     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(23, 16))
0436 #define UPDATE_PKT_SET_LOCATION(h2c_pkt, value)                    \
0437     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(31, 24))
0438 
0439 #define CH_SWITCH_SET_START(h2c_pkt, value)                    \
0440     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(0))
0441 #define CH_SWITCH_SET_DEST_CH_EN(h2c_pkt, value)                   \
0442     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(1))
0443 #define CH_SWITCH_SET_ABSOLUTE_TIME(h2c_pkt, value)                \
0444     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(2))
0445 #define CH_SWITCH_SET_PERIODIC_OPT(h2c_pkt, value)                 \
0446     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(4, 3))
0447 #define CH_SWITCH_SET_SCAN_MODE(h2c_pkt, value)                    \
0448     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(5))
0449 #define CH_SWITCH_SET_BACK_OP_EN(h2c_pkt, value)                   \
0450     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(6))
0451 #define CH_SWITCH_SET_INFO_LOC(h2c_pkt, value)                     \
0452     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(15, 8))
0453 #define CH_SWITCH_SET_CH_NUM(h2c_pkt, value)                       \
0454     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(23, 16))
0455 #define CH_SWITCH_SET_PRI_CH_IDX(h2c_pkt, value)                   \
0456     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(27, 24))
0457 #define CH_SWITCH_SET_DEST_BW(h2c_pkt, value)                      \
0458     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(31, 28))
0459 #define CH_SWITCH_SET_DEST_CH(h2c_pkt, value)                      \
0460     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(7, 0))
0461 #define CH_SWITCH_SET_NORMAL_PERIOD(h2c_pkt, value)                \
0462     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(13, 8))
0463 #define CH_SWITCH_SET_NORMAL_PERIOD_SEL(h2c_pkt, value)                \
0464     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(15, 14))
0465 #define CH_SWITCH_SET_SLOW_PERIOD(h2c_pkt, value)                  \
0466     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(21, 16))
0467 #define CH_SWITCH_SET_SLOW_PERIOD_SEL(h2c_pkt, value)                  \
0468     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(23, 22))
0469 #define CH_SWITCH_SET_NORMAL_CYCLE(h2c_pkt, value)                 \
0470     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(31, 24))
0471 #define CH_SWITCH_SET_TSF_HIGH(h2c_pkt, value)                     \
0472     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x04, value, GENMASK(31, 0))
0473 #define CH_SWITCH_SET_TSF_LOW(h2c_pkt, value)                      \
0474     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x05, value, GENMASK(31, 0))
0475 #define CH_SWITCH_SET_INFO_SIZE(h2c_pkt, value)                    \
0476     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x06, value, GENMASK(15, 0))
0477 
0478 #define SCAN_OFFLOAD_SET_START(h2c_pkt, value)                     \
0479     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(0))
0480 #define SCAN_OFFLOAD_SET_BACK_OP_EN(h2c_pkt, value)                \
0481     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(1))
0482 #define SCAN_OFFLOAD_SET_RANDOM_SEQ_EN(h2c_pkt, value)                 \
0483     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(2))
0484 #define SCAN_OFFLOAD_SET_NO_CCK_EN(h2c_pkt, value)                 \
0485     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(3))
0486 #define SCAN_OFFLOAD_SET_VERBOSE(h2c_pkt, value)                   \
0487     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(4))
0488 #define SCAN_OFFLOAD_SET_CH_NUM(h2c_pkt, value)                    \
0489     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(15, 8))
0490 #define SCAN_OFFLOAD_SET_CH_INFO_SIZE(h2c_pkt, value)                  \
0491     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(31, 16))
0492 #define SCAN_OFFLOAD_SET_CH_INFO_LOC(h2c_pkt, value)                   \
0493     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(7, 0))
0494 #define SCAN_OFFLOAD_SET_OP_CH(h2c_pkt, value)                     \
0495     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(15, 8))
0496 #define SCAN_OFFLOAD_SET_OP_PRI_CH_IDX(h2c_pkt, value)                 \
0497     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(19, 16))
0498 #define SCAN_OFFLOAD_SET_OP_BW(h2c_pkt, value)                     \
0499     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(23, 20))
0500 #define SCAN_OFFLOAD_SET_OP_PORT_ID(h2c_pkt, value)                \
0501     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(26, 24))
0502 #define SCAN_OFFLOAD_SET_OP_DWELL_TIME(h2c_pkt, value)                 \
0503     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x04, value, GENMASK(15, 0))
0504 #define SCAN_OFFLOAD_SET_OP_GAP_TIME(h2c_pkt, value)                   \
0505     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x04, value, GENMASK(31, 16))
0506 #define SCAN_OFFLOAD_SET_MODE(h2c_pkt, value)                      \
0507     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x05, value, GENMASK(3, 0))
0508 #define SCAN_OFFLOAD_SET_SSID_NUM(h2c_pkt, value)                  \
0509     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x05, value, GENMASK(7, 4))
0510 #define SCAN_OFFLOAD_SET_PKT_LOC(h2c_pkt, value)                   \
0511     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x05, value, GENMASK(15, 8))
0512 
0513 /* Command H2C */
0514 #define H2C_CMD_RSVD_PAGE       0x0
0515 #define H2C_CMD_MEDIA_STATUS_RPT    0x01
0516 #define H2C_CMD_SET_PWR_MODE        0x20
0517 #define H2C_CMD_LPS_PG_INFO     0x2b
0518 #define H2C_CMD_RA_INFO         0x40
0519 #define H2C_CMD_RSSI_MONITOR        0x42
0520 #define H2C_CMD_BCN_FILTER_OFFLOAD_P0   0x56
0521 #define H2C_CMD_BCN_FILTER_OFFLOAD_P1   0x57
0522 #define H2C_CMD_WL_PHY_INFO     0x58
0523 #define H2C_CMD_SCAN            0x59
0524 #define H2C_CMD_ADAPTIVITY      0x5A
0525 
0526 #define H2C_CMD_COEX_TDMA_TYPE      0x60
0527 #define H2C_CMD_QUERY_BT_INFO       0x61
0528 #define H2C_CMD_FORCE_BT_TX_POWER   0x62
0529 #define H2C_CMD_IGNORE_WLAN_ACTION  0x63
0530 #define H2C_CMD_WL_CH_INFO      0x66
0531 #define H2C_CMD_QUERY_BT_MP_INFO    0x67
0532 #define H2C_CMD_BT_WIFI_CONTROL     0x69
0533 #define H2C_CMD_WIFI_CALIBRATION    0x6d
0534 #define H2C_CMD_QUERY_BT_HID_INFO   0x73
0535 
0536 #define H2C_CMD_KEEP_ALIVE      0x03
0537 #define H2C_CMD_DISCONNECT_DECISION 0x04
0538 #define H2C_CMD_WOWLAN          0x80
0539 #define H2C_CMD_REMOTE_WAKE_CTRL    0x81
0540 #define H2C_CMD_AOAC_GLOBAL_INFO    0x82
0541 #define H2C_CMD_NLO_INFO        0x8C
0542 
0543 #define SET_H2C_CMD_ID_CLASS(h2c_pkt, value)                       \
0544     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(7, 0))
0545 
0546 #define MEDIA_STATUS_RPT_SET_OP_MODE(h2c_pkt, value)                           \
0547     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
0548 #define MEDIA_STATUS_RPT_SET_MACID(h2c_pkt, value)                             \
0549     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
0550 
0551 #define SET_WL_PHY_INFO_TX_TP(h2c_pkt, value)                      \
0552     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(17, 8))
0553 #define SET_WL_PHY_INFO_RX_TP(h2c_pkt, value)                      \
0554     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(27, 18))
0555 #define SET_WL_PHY_INFO_TX_RATE_DESC(h2c_pkt, value)                   \
0556     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0))
0557 #define SET_WL_PHY_INFO_RX_RATE_DESC(h2c_pkt, value)                   \
0558     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8))
0559 #define SET_WL_PHY_INFO_RX_EVM(h2c_pkt, value)                     \
0560     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(23, 16))
0561 #define SET_BCN_FILTER_OFFLOAD_P1_MACID(h2c_pkt, value)                \
0562     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
0563 #define SET_BCN_FILTER_OFFLOAD_P1_ENABLE(h2c_pkt, value)               \
0564     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(16))
0565 #define SET_BCN_FILTER_OFFLOAD_P1_HYST(h2c_pkt, value)                 \
0566     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(20, 17))
0567 #define SET_BCN_FILTER_OFFLOAD_P1_OFFLOAD_MODE(h2c_pkt, value)             \
0568     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 21))
0569 #define SET_BCN_FILTER_OFFLOAD_P1_THRESHOLD(h2c_pkt, value)            \
0570     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
0571 #define SET_BCN_FILTER_OFFLOAD_P1_BCN_LOSS_CNT(h2c_pkt, value)             \
0572     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(3, 0))
0573 #define SET_BCN_FILTER_OFFLOAD_P1_BCN_INTERVAL(h2c_pkt, value)             \
0574     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(13, 4))
0575 
0576 #define SET_SCAN_START(h2c_pkt, value)                         \
0577     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
0578 
0579 #define SET_ADAPTIVITY_MODE(h2c_pkt, value)                    \
0580     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(11, 8))
0581 #define SET_ADAPTIVITY_OPTION(h2c_pkt, value)                      \
0582     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 12))
0583 #define SET_ADAPTIVITY_IGI(h2c_pkt, value)                     \
0584     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
0585 #define SET_ADAPTIVITY_L2H(h2c_pkt, value)                     \
0586     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
0587 #define SET_ADAPTIVITY_DENSITY(h2c_pkt, value)                     \
0588     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0))
0589 
0590 #define SET_PWR_MODE_SET_MODE(h2c_pkt, value)                                  \
0591     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(14, 8))
0592 #define SET_PWR_MODE_SET_RLBM(h2c_pkt, value)                                  \
0593     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(19, 16))
0594 #define SET_PWR_MODE_SET_SMART_PS(h2c_pkt, value)                              \
0595     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 20))
0596 #define SET_PWR_MODE_SET_AWAKE_INTERVAL(h2c_pkt, value)                        \
0597     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
0598 #define SET_PWR_MODE_SET_PORT_ID(h2c_pkt, value)                               \
0599     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 5))
0600 #define SET_PWR_MODE_SET_PWR_STATE(h2c_pkt, value)                             \
0601     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8))
0602 #define LPS_PG_INFO_LOC(h2c_pkt, value)                                        \
0603     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
0604 #define LPS_PG_DPK_LOC(h2c_pkt, value)                                         \
0605     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
0606 #define LPS_PG_SEC_CAM_EN(h2c_pkt, value)                                      \
0607     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
0608 #define LPS_PG_PATTERN_CAM_EN(h2c_pkt, value)                      \
0609     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(10))
0610 #define SET_RSSI_INFO_MACID(h2c_pkt, value)                                    \
0611     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
0612 #define SET_RSSI_INFO_RSSI(h2c_pkt, value)                                     \
0613     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
0614 #define SET_RSSI_INFO_STBC(h2c_pkt, value)                                     \
0615     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, BIT(1))
0616 #define SET_RA_INFO_MACID(h2c_pkt, value)                                      \
0617     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
0618 #define SET_RA_INFO_RATE_ID(h2c_pkt, value)                                    \
0619     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(20, 16))
0620 #define SET_RA_INFO_INIT_RA_LVL(h2c_pkt, value)                                \
0621     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(22, 21))
0622 #define SET_RA_INFO_SGI_EN(h2c_pkt, value)                                     \
0623     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(23))
0624 #define SET_RA_INFO_BW_MODE(h2c_pkt, value)                                    \
0625     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(25, 24))
0626 #define SET_RA_INFO_LDPC(h2c_pkt, value)                                       \
0627     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(26))
0628 #define SET_RA_INFO_NO_UPDATE(h2c_pkt, value)                                  \
0629     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(27))
0630 #define SET_RA_INFO_VHT_EN(h2c_pkt, value)                                     \
0631     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(29, 28))
0632 #define SET_RA_INFO_DIS_PT(h2c_pkt, value)                                     \
0633     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(30))
0634 #define SET_RA_INFO_RA_MASK0(h2c_pkt, value)                                   \
0635     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0))
0636 #define SET_RA_INFO_RA_MASK1(h2c_pkt, value)                                   \
0637     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8))
0638 #define SET_RA_INFO_RA_MASK2(h2c_pkt, value)                                   \
0639     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(23, 16))
0640 #define SET_RA_INFO_RA_MASK3(h2c_pkt, value)                                   \
0641     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(31, 24))
0642 #define SET_QUERY_BT_INFO(h2c_pkt, value)                                      \
0643     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
0644 #define SET_WL_CH_INFO_LINK(h2c_pkt, value)                                    \
0645     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
0646 #define SET_WL_CH_INFO_CHNL(h2c_pkt, value)                                    \
0647     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
0648 #define SET_WL_CH_INFO_BW(h2c_pkt, value)                                      \
0649     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
0650 #define SET_BT_MP_INFO_SEQ(h2c_pkt, value)                                     \
0651     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 12))
0652 #define SET_BT_MP_INFO_OP_CODE(h2c_pkt, value)                                 \
0653     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
0654 #define SET_BT_MP_INFO_PARA1(h2c_pkt, value)                                   \
0655     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
0656 #define SET_BT_MP_INFO_PARA2(h2c_pkt, value)                                   \
0657     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0))
0658 #define SET_BT_MP_INFO_PARA3(h2c_pkt, value)                                   \
0659     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8))
0660 #define SET_BT_TX_POWER_INDEX(h2c_pkt, value)                                  \
0661     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
0662 #define SET_IGNORE_WLAN_ACTION_EN(h2c_pkt, value)                              \
0663     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
0664 #define SET_COEX_TDMA_TYPE_PARA1(h2c_pkt, value)                               \
0665     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
0666 #define SET_COEX_TDMA_TYPE_PARA2(h2c_pkt, value)                               \
0667     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
0668 #define SET_COEX_TDMA_TYPE_PARA3(h2c_pkt, value)                               \
0669     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
0670 #define SET_COEX_TDMA_TYPE_PARA4(h2c_pkt, value)                               \
0671     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0))
0672 #define SET_COEX_TDMA_TYPE_PARA5(h2c_pkt, value)                               \
0673     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8))
0674 #define SET_BT_WIFI_CONTROL_OP_CODE(h2c_pkt, value)                            \
0675     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
0676 #define SET_BT_WIFI_CONTROL_DATA1(h2c_pkt, value)                              \
0677     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
0678 #define SET_BT_WIFI_CONTROL_DATA2(h2c_pkt, value)                              \
0679     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
0680 #define SET_BT_WIFI_CONTROL_DATA3(h2c_pkt, value)                              \
0681     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0))
0682 #define SET_BT_WIFI_CONTROL_DATA4(h2c_pkt, value)                              \
0683     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8))
0684 #define SET_BT_WIFI_CONTROL_DATA5(h2c_pkt, value)                              \
0685     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(23, 16))
0686 
0687 #define SET_COEX_QUERY_HID_INFO_SUBID(h2c_pkt, value)                          \
0688     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
0689 #define SET_COEX_QUERY_HID_INFO_DATA1(h2c_pkt, value)                          \
0690     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
0691 
0692 #define SET_KEEP_ALIVE_ENABLE(h2c_pkt, value)                      \
0693     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
0694 #define SET_KEEP_ALIVE_ADOPT(h2c_pkt, value)                       \
0695     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(9))
0696 #define SET_KEEP_ALIVE_PKT_TYPE(h2c_pkt, value)                    \
0697     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(10))
0698 #define SET_KEEP_ALIVE_CHECK_PERIOD(h2c_pkt, value)                \
0699     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
0700 
0701 #define SET_DISCONNECT_DECISION_ENABLE(h2c_pkt, value)                 \
0702     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
0703 #define SET_DISCONNECT_DECISION_ADOPT(h2c_pkt, value)                  \
0704     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(9))
0705 #define SET_DISCONNECT_DECISION_CHECK_PERIOD(h2c_pkt, value)               \
0706     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
0707 #define SET_DISCONNECT_DECISION_TRY_PKT_NUM(h2c_pkt, value)            \
0708     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
0709 
0710 #define SET_WOWLAN_FUNC_ENABLE(h2c_pkt, value)                     \
0711     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
0712 #define SET_WOWLAN_PATTERN_MATCH_ENABLE(h2c_pkt, value)                \
0713     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(9))
0714 #define SET_WOWLAN_MAGIC_PKT_ENABLE(h2c_pkt, value)                \
0715     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(10))
0716 #define SET_WOWLAN_UNICAST_PKT_ENABLE(h2c_pkt, value)                  \
0717     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(11))
0718 #define SET_WOWLAN_REKEY_WAKEUP_ENABLE(h2c_pkt, value)                 \
0719     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(14))
0720 #define SET_WOWLAN_DEAUTH_WAKEUP_ENABLE(h2c_pkt, value)                \
0721     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(15))
0722 
0723 #define SET_REMOTE_WAKECTRL_ENABLE(h2c_pkt, value)                 \
0724     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
0725 #define SET_REMOTE_WAKE_CTRL_NLO_OFFLOAD_EN(h2c_pkt, value)            \
0726     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(12))
0727 
0728 #define SET_AOAC_GLOBAL_INFO_PAIRWISE_ENC_ALG(h2c_pkt, value)              \
0729     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
0730 #define SET_AOAC_GLOBAL_INFO_GROUP_ENC_ALG(h2c_pkt, value)             \
0731     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
0732 
0733 #define SET_NLO_FUN_EN(h2c_pkt, value)                                         \
0734     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
0735 #define SET_NLO_PS_32K(h2c_pkt, value)                                         \
0736     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(9))
0737 #define SET_NLO_IGNORE_SECURITY(h2c_pkt, value)                                \
0738     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(10))
0739 #define SET_NLO_LOC_NLO_INFO(h2c_pkt, value)                                   \
0740     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
0741 
0742 #define GET_FW_DUMP_LEN(_header)                    \
0743     le32_get_bits(*((__le32 *)(_header) + 0x00), GENMASK(15, 0))
0744 #define GET_FW_DUMP_SEQ(_header)                    \
0745     le32_get_bits(*((__le32 *)(_header) + 0x00), GENMASK(22, 16))
0746 #define GET_FW_DUMP_MORE(_header)                   \
0747     le32_get_bits(*((__le32 *)(_header) + 0x00), BIT(23))
0748 #define GET_FW_DUMP_VERSION(_header)                    \
0749     le32_get_bits(*((__le32 *)(_header) + 0x00), GENMASK(31, 24))
0750 #define GET_FW_DUMP_TLV_TYPE(_header)                   \
0751     le32_get_bits(*((__le32 *)(_header) + 0x01), GENMASK(15, 0))
0752 #define GET_FW_DUMP_TLV_LEN(_header)                    \
0753     le32_get_bits(*((__le32 *)(_header) + 0x01), GENMASK(31, 16))
0754 #define GET_FW_DUMP_TLV_VAL(_header)                    \
0755     le32_get_bits(*((__le32 *)(_header) + 0x02), GENMASK(31, 0))
0756 
0757 #define RFK_SET_INFORM_START(h2c_pkt, value)                \
0758     le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
0759 static inline struct rtw_c2h_cmd *get_c2h_from_skb(struct sk_buff *skb)
0760 {
0761     u32 pkt_offset;
0762 
0763     pkt_offset = *((u32 *)skb->cb);
0764     return (struct rtw_c2h_cmd *)(skb->data + pkt_offset);
0765 }
0766 
0767 static inline bool rtw_fw_feature_check(struct rtw_fw_state *fw,
0768                     enum rtw_fw_feature feature)
0769 {
0770     return !!(fw->feature & feature);
0771 }
0772 
0773 void rtw_fw_c2h_cmd_rx_irqsafe(struct rtw_dev *rtwdev, u32 pkt_offset,
0774                    struct sk_buff *skb);
0775 void rtw_fw_c2h_cmd_handle(struct rtw_dev *rtwdev, struct sk_buff *skb);
0776 void rtw_fw_send_general_info(struct rtw_dev *rtwdev);
0777 void rtw_fw_send_phydm_info(struct rtw_dev *rtwdev);
0778 
0779 void rtw_fw_do_iqk(struct rtw_dev *rtwdev, struct rtw_iqk_para *para);
0780 void rtw_fw_inform_rfk_status(struct rtw_dev *rtwdev, bool start);
0781 void rtw_fw_set_pwr_mode(struct rtw_dev *rtwdev);
0782 void rtw_fw_set_pg_info(struct rtw_dev *rtwdev);
0783 void rtw_fw_query_bt_info(struct rtw_dev *rtwdev);
0784 void rtw_fw_wl_ch_info(struct rtw_dev *rtwdev, u8 link, u8 ch, u8 bw);
0785 void rtw_fw_query_bt_mp_info(struct rtw_dev *rtwdev,
0786                  struct rtw_coex_info_req *req);
0787 void rtw_fw_force_bt_tx_power(struct rtw_dev *rtwdev, u8 bt_pwr_dec_lvl);
0788 void rtw_fw_bt_ignore_wlan_action(struct rtw_dev *rtwdev, bool enable);
0789 void rtw_fw_coex_tdma_type(struct rtw_dev *rtwdev,
0790                u8 para1, u8 para2, u8 para3, u8 para4, u8 para5);
0791 void rtw_fw_coex_query_hid_info(struct rtw_dev *rtwdev, u8 sub_id, u8 data);
0792 
0793 void rtw_fw_bt_wifi_control(struct rtw_dev *rtwdev, u8 op_code, u8 *data);
0794 void rtw_fw_send_rssi_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si);
0795 void rtw_fw_send_ra_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si,
0796              bool reset_ra_mask);
0797 void rtw_fw_media_status_report(struct rtw_dev *rtwdev, u8 mac_id, bool conn);
0798 void rtw_fw_update_wl_phy_info(struct rtw_dev *rtwdev);
0799 void rtw_fw_beacon_filter_config(struct rtw_dev *rtwdev, bool connect,
0800                  struct ieee80211_vif *vif);
0801 int rtw_fw_write_data_rsvd_page(struct rtw_dev *rtwdev, u16 pg_addr,
0802                 u8 *buf, u32 size);
0803 void rtw_remove_rsvd_page(struct rtw_dev *rtwdev,
0804               struct rtw_vif *rtwvif);
0805 void rtw_add_rsvd_page_bcn(struct rtw_dev *rtwdev,
0806                struct rtw_vif *rtwvif);
0807 void rtw_add_rsvd_page_pno(struct rtw_dev *rtwdev,
0808                struct rtw_vif *rtwvif);
0809 void rtw_add_rsvd_page_sta(struct rtw_dev *rtwdev,
0810                struct rtw_vif *rtwvif);
0811 int rtw_fw_download_rsvd_page(struct rtw_dev *rtwdev);
0812 void rtw_fw_update_beacon_work(struct work_struct *work);
0813 void rtw_send_rsvd_page_h2c(struct rtw_dev *rtwdev);
0814 int rtw_dump_drv_rsvd_page(struct rtw_dev *rtwdev,
0815                u32 offset, u32 size, u32 *buf);
0816 void rtw_fw_set_remote_wake_ctrl_cmd(struct rtw_dev *rtwdev, bool enable);
0817 void rtw_fw_set_wowlan_ctrl_cmd(struct rtw_dev *rtwdev, bool enable);
0818 void rtw_fw_set_keep_alive_cmd(struct rtw_dev *rtwdev, bool enable);
0819 void rtw_fw_set_disconnect_decision_cmd(struct rtw_dev *rtwdev, bool enable);
0820 void rtw_fw_set_aoac_global_info_cmd(struct rtw_dev *rtwdev,
0821                      u8 pairwise_key_enc,
0822                      u8 group_key_enc);
0823 
0824 void rtw_fw_set_nlo_info(struct rtw_dev *rtwdev, bool enable);
0825 void rtw_fw_update_pkt_probe_req(struct rtw_dev *rtwdev,
0826                  struct cfg80211_ssid *ssid);
0827 void rtw_fw_channel_switch(struct rtw_dev *rtwdev, bool enable);
0828 void rtw_fw_h2c_cmd_dbg(struct rtw_dev *rtwdev, u8 *h2c);
0829 void rtw_fw_c2h_cmd_isr(struct rtw_dev *rtwdev);
0830 int rtw_fw_dump_fifo(struct rtw_dev *rtwdev, u8 fifo_sel, u32 addr, u32 size,
0831              u32 *buffer);
0832 void rtw_fw_scan_notify(struct rtw_dev *rtwdev, bool start);
0833 void rtw_fw_adaptivity(struct rtw_dev *rtwdev);
0834 void rtw_store_op_chan(struct rtw_dev *rtwdev);
0835 void rtw_hw_scan_start(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
0836                struct ieee80211_scan_request *req);
0837 void rtw_hw_scan_complete(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
0838               bool aborted);
0839 int rtw_hw_scan_offload(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
0840             bool enable);
0841 void rtw_hw_scan_status_report(struct rtw_dev *rtwdev, struct sk_buff *skb);
0842 void rtw_hw_scan_chan_switch(struct rtw_dev *rtwdev, struct sk_buff *skb);
0843 void rtw_hw_scan_abort(struct rtw_dev *rtwdev, struct ieee80211_vif *vif);
0844 #endif
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