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0005 #ifndef __RTW_COEX_H__
0006 #define __RTW_COEX_H__
0007
0008 #define COEX_CCK_2 0x1
0009 #define COEX_RESP_ACK_BY_WL_FW 0x1
0010 #define COEX_REQUEST_TIMEOUT msecs_to_jiffies(10)
0011
0012 #define COEX_MIN_DELAY 10
0013 #define COEX_RFK_TIMEOUT 600
0014 #define COEX_BT_GAMEHID_CNT 800
0015
0016 #define COEX_RF_OFF 0x0
0017 #define COEX_RF_ON 0x1
0018
0019 #define COEX_H2C69_WL_LEAKAP 0xc
0020 #define PARA1_H2C69_DIS_5MS 0x1
0021 #define PARA1_H2C69_EN_5MS 0x0
0022
0023 #define COEX_H2C69_TDMA_SLOT 0xb
0024 #define PARA1_H2C69_TDMA_4SLOT 0xc1
0025 #define PARA1_H2C69_TDMA_2SLOT 0x1
0026 #define PARA1_H2C69_TBTT_TIMES GENMASK(5, 0)
0027 #define PARA1_H2C69_TBTT_DIV100 BIT(7)
0028
0029 #define COEX_H2C69_TOGGLE_TABLE_A 0xd
0030 #define COEX_H2C69_TOGGLE_TABLE_B 0x7
0031
0032 #define TDMA_4SLOT BIT(8)
0033
0034 #define TDMA_TIMER_TYPE_2SLOT 0
0035 #define TDMA_TIMER_TYPE_4SLOT 3
0036
0037 #define COEX_RSSI_STEP 4
0038
0039 #define COEX_RSSI_HIGH(rssi) \
0040 ({ typeof(rssi) __rssi__ = rssi; \
0041 (__rssi__ == COEX_RSSI_STATE_HIGH || \
0042 __rssi__ == COEX_RSSI_STATE_STAY_HIGH ? true : false); })
0043
0044 #define COEX_RSSI_MEDIUM(rssi) \
0045 ({ typeof(rssi) __rssi__ = rssi; \
0046 (__rssi__ == COEX_RSSI_STATE_MEDIUM || \
0047 __rssi__ == COEX_RSSI_STATE_STAY_MEDIUM ? true : false); })
0048
0049 #define COEX_RSSI_LOW(rssi) \
0050 ({ typeof(rssi) __rssi__ = rssi; \
0051 (__rssi__ == COEX_RSSI_STATE_LOW || \
0052 __rssi__ == COEX_RSSI_STATE_STAY_LOW ? true : false); })
0053
0054 #define GET_COEX_RESP_BT_SUPP_VER(payload) \
0055 le64_get_bits(*((__le64 *)(payload)), GENMASK_ULL(39, 32))
0056 #define GET_COEX_RESP_BT_SUPP_FEAT(payload) \
0057 le64_get_bits(*((__le64 *)(payload)), GENMASK_ULL(39, 24))
0058 #define GET_COEX_RESP_BT_PATCH_VER(payload) \
0059 le64_get_bits(*((__le64 *)(payload)), GENMASK_ULL(55, 24))
0060 #define GET_COEX_RESP_BT_REG_VAL(payload) \
0061 le64_get_bits(*((__le64 *)(payload)), GENMASK_ULL(39, 24))
0062 #define GET_COEX_RESP_BT_SCAN_TYPE(payload) \
0063 le64_get_bits(*((__le64 *)(payload)), GENMASK(31, 24))
0064
0065 enum coex_mp_info_op {
0066 BT_MP_INFO_OP_PATCH_VER = 0x00,
0067 BT_MP_INFO_OP_READ_REG = 0x11,
0068 BT_MP_INFO_OP_SUPP_FEAT = 0x2a,
0069 BT_MP_INFO_OP_SUPP_VER = 0x2b,
0070 BT_MP_INFO_OP_SCAN_TYPE = 0x2d,
0071 BT_MP_INFO_OP_LNA_CONSTRAINT = 0x32,
0072 };
0073
0074 enum coex_set_ant_phase {
0075 COEX_SET_ANT_INIT,
0076 COEX_SET_ANT_WONLY,
0077 COEX_SET_ANT_WOFF,
0078 COEX_SET_ANT_2G,
0079 COEX_SET_ANT_5G,
0080 COEX_SET_ANT_POWERON,
0081 COEX_SET_ANT_2G_WLBT,
0082 COEX_SET_ANT_2G_FREERUN,
0083
0084 COEX_SET_ANT_MAX
0085 };
0086
0087 enum coex_runreason {
0088 COEX_RSN_2GSCANSTART = 0,
0089 COEX_RSN_5GSCANSTART = 1,
0090 COEX_RSN_SCANFINISH = 2,
0091 COEX_RSN_2GSWITCHBAND = 3,
0092 COEX_RSN_5GSWITCHBAND = 4,
0093 COEX_RSN_2GCONSTART = 5,
0094 COEX_RSN_5GCONSTART = 6,
0095 COEX_RSN_2GCONFINISH = 7,
0096 COEX_RSN_5GCONFINISH = 8,
0097 COEX_RSN_2GMEDIA = 9,
0098 COEX_RSN_5GMEDIA = 10,
0099 COEX_RSN_MEDIADISCON = 11,
0100 COEX_RSN_BTINFO = 12,
0101 COEX_RSN_LPS = 13,
0102 COEX_RSN_WLSTATUS = 14,
0103 COEX_RSN_BTSTATUS = 15,
0104
0105 COEX_RSN_MAX
0106 };
0107
0108 enum coex_lte_coex_table_type {
0109 COEX_CTT_WL_VS_LTE,
0110 COEX_CTT_BT_VS_LTE,
0111 };
0112
0113 enum coex_gnt_setup_state {
0114 COEX_GNT_SET_HW_PTA = 0x0,
0115 COEX_GNT_SET_SW_LOW = 0x1,
0116 COEX_GNT_SET_SW_HIGH = 0x3,
0117 };
0118
0119 enum coex_ext_ant_switch_pos_type {
0120 COEX_SWITCH_TO_BT,
0121 COEX_SWITCH_TO_WLG,
0122 COEX_SWITCH_TO_WLA,
0123 COEX_SWITCH_TO_NOCARE,
0124 COEX_SWITCH_TO_WLG_BT,
0125
0126 COEX_SWITCH_TO_MAX
0127 };
0128
0129 enum coex_ext_ant_switch_ctrl_type {
0130 COEX_SWITCH_CTRL_BY_BBSW,
0131 COEX_SWITCH_CTRL_BY_PTA,
0132 COEX_SWITCH_CTRL_BY_ANTDIV,
0133 COEX_SWITCH_CTRL_BY_MAC,
0134 COEX_SWITCH_CTRL_BY_BT,
0135 COEX_SWITCH_CTRL_BY_FW,
0136
0137 COEX_SWITCH_CTRL_MAX
0138 };
0139
0140 enum coex_algorithm {
0141 COEX_ALGO_NOPROFILE = 0,
0142 COEX_ALGO_HFP = 1,
0143 COEX_ALGO_HID = 2,
0144 COEX_ALGO_A2DP = 3,
0145 COEX_ALGO_PAN = 4,
0146 COEX_ALGO_A2DP_HID = 5,
0147 COEX_ALGO_A2DP_PAN = 6,
0148 COEX_ALGO_PAN_HID = 7,
0149 COEX_ALGO_A2DP_PAN_HID = 8,
0150
0151 COEX_ALGO_MAX
0152 };
0153
0154 enum coex_bt_profile {
0155 BPM_NOPROFILE = 0,
0156 BPM_HFP = BIT(0),
0157 BPM_HID = BIT(1),
0158 BPM_A2DP = BIT(2),
0159 BPM_PAN = BIT(3),
0160 BPM_HID_HFP = BPM_HID | BPM_HFP,
0161 BPM_A2DP_HFP = BPM_A2DP | BPM_HFP,
0162 BPM_A2DP_HID = BPM_A2DP | BPM_HID,
0163 BPM_A2DP_HID_HFP = BPM_A2DP | BPM_HID | BPM_HFP,
0164 BPM_PAN_HFP = BPM_PAN | BPM_HFP,
0165 BPM_PAN_HID = BPM_PAN | BPM_HID,
0166 BPM_PAN_HID_HFP = BPM_PAN | BPM_HID | BPM_HFP,
0167 BPM_PAN_A2DP = BPM_PAN | BPM_A2DP,
0168 BPM_PAN_A2DP_HFP = BPM_PAN | BPM_A2DP | BPM_HFP,
0169 BPM_PAN_A2DP_HID = BPM_PAN | BPM_A2DP | BPM_HID,
0170 BPM_PAN_A2DP_HID_HFP = BPM_PAN | BPM_A2DP | BPM_HID | BPM_HFP,
0171 };
0172
0173 enum coex_wl_link_mode {
0174 COEX_WLINK_2G1PORT = 0x0,
0175 COEX_WLINK_5G = 0x3,
0176 COEX_WLINK_2GFREE = 0x7,
0177 COEX_WLINK_MAX
0178 };
0179
0180 enum coex_wl2bt_scoreboard {
0181 COEX_SCBD_ACTIVE = BIT(0),
0182 COEX_SCBD_ONOFF = BIT(1),
0183 COEX_SCBD_SCAN = BIT(2),
0184 COEX_SCBD_UNDERTEST = BIT(3),
0185 COEX_SCBD_RXGAIN = BIT(4),
0186 COEX_SCBD_BT_RFK = BIT(5),
0187 COEX_SCBD_WLBUSY = BIT(6),
0188 COEX_SCBD_EXTFEM = BIT(8),
0189 COEX_SCBD_TDMA = BIT(9),
0190 COEX_SCBD_FIX2M = BIT(10),
0191 COEX_SCBD_ALL = GENMASK(15, 0),
0192 };
0193
0194 enum coex_power_save_type {
0195 COEX_PS_WIFI_NATIVE = 0,
0196 COEX_PS_LPS_ON = 1,
0197 COEX_PS_LPS_OFF = 2,
0198 };
0199
0200 enum coex_rssi_state {
0201 COEX_RSSI_STATE_HIGH,
0202 COEX_RSSI_STATE_MEDIUM,
0203 COEX_RSSI_STATE_LOW,
0204 COEX_RSSI_STATE_STAY_HIGH,
0205 COEX_RSSI_STATE_STAY_MEDIUM,
0206 COEX_RSSI_STATE_STAY_LOW,
0207 };
0208
0209 enum coex_notify_type_ips {
0210 COEX_IPS_LEAVE = 0x0,
0211 COEX_IPS_ENTER = 0x1,
0212 };
0213
0214 enum coex_notify_type_lps {
0215 COEX_LPS_DISABLE = 0x0,
0216 COEX_LPS_ENABLE = 0x1,
0217 };
0218
0219 enum coex_notify_type_scan {
0220 COEX_SCAN_FINISH,
0221 COEX_SCAN_START,
0222 COEX_SCAN_START_2G,
0223 COEX_SCAN_START_5G,
0224 };
0225
0226 enum coex_notify_type_switchband {
0227 COEX_NOT_SWITCH,
0228 COEX_SWITCH_TO_24G,
0229 COEX_SWITCH_TO_5G,
0230 COEX_SWITCH_TO_24G_NOFORSCAN,
0231 };
0232
0233 enum coex_notify_type_associate {
0234 COEX_ASSOCIATE_FINISH,
0235 COEX_ASSOCIATE_START,
0236 COEX_ASSOCIATE_5G_FINISH,
0237 COEX_ASSOCIATE_5G_START,
0238 };
0239
0240 enum coex_notify_type_media_status {
0241 COEX_MEDIA_DISCONNECT,
0242 COEX_MEDIA_CONNECT,
0243 COEX_MEDIA_CONNECT_5G,
0244 };
0245
0246 enum coex_bt_status {
0247 COEX_BTSTATUS_NCON_IDLE = 0,
0248 COEX_BTSTATUS_CON_IDLE = 1,
0249 COEX_BTSTATUS_INQ_PAGE = 2,
0250 COEX_BTSTATUS_ACL_BUSY = 3,
0251 COEX_BTSTATUS_SCO_BUSY = 4,
0252 COEX_BTSTATUS_ACL_SCO_BUSY = 5,
0253
0254 COEX_BTSTATUS_MAX
0255 };
0256
0257 enum coex_wl_tput_dir {
0258 COEX_WL_TPUT_TX = 0x0,
0259 COEX_WL_TPUT_RX = 0x1,
0260 COEX_WL_TPUT_MAX
0261 };
0262
0263 enum coex_wl_priority_mask {
0264 COEX_WLPRI_RX_RSP = 2,
0265 COEX_WLPRI_TX_RSP = 3,
0266 COEX_WLPRI_TX_BEACON = 4,
0267 COEX_WLPRI_TX_OFDM = 11,
0268 COEX_WLPRI_TX_CCK = 12,
0269 COEX_WLPRI_TX_BEACONQ = 27,
0270 COEX_WLPRI_RX_CCK = 28,
0271 COEX_WLPRI_RX_OFDM = 29,
0272 COEX_WLPRI_MAX
0273 };
0274
0275 enum coex_commom_chip_setup {
0276 COEX_CSETUP_INIT_HW = 0x0,
0277 COEX_CSETUP_ANT_SWITCH = 0x1,
0278 COEX_CSETUP_GNT_FIX = 0x2,
0279 COEX_CSETUP_GNT_DEBUG = 0x3,
0280 COEX_CSETUP_RFE_TYPE = 0x4,
0281 COEX_CSETUP_COEXINFO_HW = 0x5,
0282 COEX_CSETUP_WL_TX_POWER = 0x6,
0283 COEX_CSETUP_WL_RX_GAIN = 0x7,
0284 COEX_CSETUP_WLAN_ACT_IPS = 0x8,
0285 COEX_CSETUP_MAX
0286 };
0287
0288 enum coex_indirect_reg_type {
0289 COEX_INDIRECT_1700 = 0x0,
0290 COEX_INDIRECT_7C0 = 0x1,
0291 COEX_INDIRECT_MAX
0292 };
0293
0294 enum coex_pstdma_type {
0295 COEX_PSTDMA_FORCE_LPSOFF = 0x0,
0296 COEX_PSTDMA_FORCE_LPSON = 0x1,
0297 COEX_PSTDMA_MAX
0298 };
0299
0300 enum coex_btrssi_type {
0301 COEX_BTRSSI_RATIO = 0x0,
0302 COEX_BTRSSI_DBM = 0x1,
0303 COEX_BTRSSI_MAX
0304 };
0305
0306 struct coex_table_para {
0307 u32 bt;
0308 u32 wl;
0309 };
0310
0311 struct coex_tdma_para {
0312 u8 para[5];
0313 };
0314
0315 struct coex_5g_afh_map {
0316 u32 wl_5g_ch;
0317 u8 bt_skip_ch;
0318 u8 bt_skip_span;
0319 };
0320
0321 struct coex_rf_para {
0322 u8 wl_pwr_dec_lvl;
0323 u8 bt_pwr_dec_lvl;
0324 bool wl_low_gain_en;
0325 u8 bt_lna_lvl;
0326 };
0327
0328 static inline void rtw_coex_set_init(struct rtw_dev *rtwdev)
0329 {
0330 struct rtw_chip_info *chip = rtwdev->chip;
0331
0332 chip->ops->coex_set_init(rtwdev);
0333 }
0334
0335 static inline
0336 void rtw_coex_set_ant_switch(struct rtw_dev *rtwdev, u8 ctrl_type, u8 pos_type)
0337 {
0338 struct rtw_chip_info *chip = rtwdev->chip;
0339
0340 if (!chip->ops->coex_set_ant_switch)
0341 return;
0342
0343 chip->ops->coex_set_ant_switch(rtwdev, ctrl_type, pos_type);
0344 }
0345
0346 static inline void rtw_coex_set_gnt_fix(struct rtw_dev *rtwdev)
0347 {
0348 struct rtw_chip_info *chip = rtwdev->chip;
0349
0350 chip->ops->coex_set_gnt_fix(rtwdev);
0351 }
0352
0353 static inline void rtw_coex_set_gnt_debug(struct rtw_dev *rtwdev)
0354 {
0355 struct rtw_chip_info *chip = rtwdev->chip;
0356
0357 chip->ops->coex_set_gnt_debug(rtwdev);
0358 }
0359
0360 static inline void rtw_coex_set_rfe_type(struct rtw_dev *rtwdev)
0361 {
0362 struct rtw_chip_info *chip = rtwdev->chip;
0363
0364 chip->ops->coex_set_rfe_type(rtwdev);
0365 }
0366
0367 static inline void rtw_coex_set_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr)
0368 {
0369 struct rtw_chip_info *chip = rtwdev->chip;
0370
0371 chip->ops->coex_set_wl_tx_power(rtwdev, wl_pwr);
0372 }
0373
0374 static inline
0375 void rtw_coex_set_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain)
0376 {
0377 struct rtw_chip_info *chip = rtwdev->chip;
0378
0379 chip->ops->coex_set_wl_rx_gain(rtwdev, low_gain);
0380 }
0381
0382 void rtw_coex_info_response(struct rtw_dev *rtwdev, struct sk_buff *skb);
0383 u32 rtw_coex_read_indirect_reg(struct rtw_dev *rtwdev, u16 addr);
0384 void rtw_coex_write_indirect_reg(struct rtw_dev *rtwdev, u16 addr,
0385 u32 mask, u32 val);
0386 void rtw_coex_write_scbd(struct rtw_dev *rtwdev, u16 bitpos, bool set);
0387
0388 void rtw_coex_bt_relink_work(struct work_struct *work);
0389 void rtw_coex_bt_reenable_work(struct work_struct *work);
0390 void rtw_coex_defreeze_work(struct work_struct *work);
0391 void rtw_coex_wl_remain_work(struct work_struct *work);
0392 void rtw_coex_bt_remain_work(struct work_struct *work);
0393 void rtw_coex_wl_connecting_work(struct work_struct *work);
0394 void rtw_coex_bt_multi_link_remain_work(struct work_struct *work);
0395 void rtw_coex_wl_ccklock_work(struct work_struct *work);
0396
0397 void rtw_coex_power_on_setting(struct rtw_dev *rtwdev);
0398 void rtw_coex_power_off_setting(struct rtw_dev *rtwdev);
0399 void rtw_coex_init_hw_config(struct rtw_dev *rtwdev, bool wifi_only);
0400 void rtw_coex_ips_notify(struct rtw_dev *rtwdev, u8 type);
0401 void rtw_coex_lps_notify(struct rtw_dev *rtwdev, u8 type);
0402 void rtw_coex_scan_notify(struct rtw_dev *rtwdev, u8 type);
0403 void rtw_coex_connect_notify(struct rtw_dev *rtwdev, u8 type);
0404 void rtw_coex_media_status_notify(struct rtw_dev *rtwdev, u8 type);
0405 void rtw_coex_bt_info_notify(struct rtw_dev *rtwdev, u8 *buf, u8 length);
0406 void rtw_coex_bt_hid_info_notify(struct rtw_dev *rtwdev, u8 *buf, u8 length);
0407 void rtw_coex_wl_fwdbginfo_notify(struct rtw_dev *rtwdev, u8 *buf, u8 length);
0408 void rtw_coex_switchband_notify(struct rtw_dev *rtwdev, u8 type);
0409 void rtw_coex_wl_status_change_notify(struct rtw_dev *rtwdev, u32 type);
0410 void rtw_coex_wl_status_check(struct rtw_dev *rtwdev);
0411 void rtw_coex_query_bt_hid_list(struct rtw_dev *rtwdev);
0412 void rtw_coex_display_coex_info(struct rtw_dev *rtwdev, struct seq_file *m);
0413
0414 static inline bool rtw_coex_disabled(struct rtw_dev *rtwdev)
0415 {
0416 struct rtw_coex *coex = &rtwdev->coex;
0417 struct rtw_coex_stat *coex_stat = &coex->stat;
0418
0419 return coex_stat->bt_disabled;
0420 }
0421
0422 #endif
