realtek/rtw88/bf.h

0001 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
0002 /* Copyright(c) 2018-2019  Realtek Corporation.
0003  */
0004
0005 #ifndef __RTW_BF_H_
0006 #define __RTW_BF_H_
0007
0008 #define REG_TXBF_CTRL       0x042C
0009 #define REG_RRSR        0x0440
0010 #define REG_NDPA_OPT_CTRL   0x045F
0011
0012 #define REG_ASSOCIATED_BFMER0_INFO  0x06E4
0013 #define REG_ASSOCIATED_BFMER1_INFO  0x06EC
0014 #define REG_TX_CSI_RPT_PARAM_BW20   0x06F4
0015 #define REG_SND_PTCL_CTRL       0x0718
0016 #define BIT_DIS_CHK_VHTSIGB_CRC     BIT(6)
0017 #define BIT_DIS_CHK_VHTSIGA_CRC     BIT(5)
0018 #define BIT_MASK_BEAMFORM       (GENMASK(4, 0) | BIT(7))
0019 #define REG_MU_TX_CTL           0x14C0
0020 #define REG_MU_STA_GID_VLD      0x14C4
0021 #define REG_MU_STA_USER_POS_INFO    0x14C8
0022 #define REG_CSI_RRSR            0x1678
0023 #define REG_WMAC_MU_BF_OPTION       0x167C
0024 #define REG_WMAC_MU_BF_CTL      0x1680
0025
0026 #define BIT_WMAC_USE_NDPARATE           BIT(30)
0027 #define BIT_WMAC_TXMU_ACKPOLICY_EN      BIT(6)
0028 #define BIT_USE_NDPA_PARAMETER          BIT(30)
0029 #define BIT_MU_P1_WAIT_STATE_EN         BIT(16)
0030 #define BIT_EN_MU_MIMO              BIT(7)
0031
0032 #define R_MU_RL             0xf
0033 #define BIT_SHIFT_R_MU_RL       12
0034 #define BIT_SHIFT_WMAC_TXMU_ACKPOLICY   4
0035 #define BIT_SHIFT_CSI_RATE      24
0036
0037 #define BIT_MASK_R_MU_RL (R_MU_RL << BIT_SHIFT_R_MU_RL)
0038 #define BIT_MASK_R_MU_TABLE_VALID   0x3f
0039 #define BIT_MASK_CSI_RATE_VAL       0x3F
0040 #define BIT_MASK_CSI_RATE (BIT_MASK_CSI_RATE_VAL << BIT_SHIFT_CSI_RATE)
0041
0042 #define BIT_RXFLTMAP0_ACTIONNOACK   BIT(14)
0043 #define BIT_RXFLTMAP1_BF        (BIT(4) | BIT(5))
0044 #define BIT_RXFLTMAP1_BF_REPORT_POLL    BIT(4)
0045 #define BIT_RXFLTMAP4_BF_REPORT_POLL    BIT(4)
0046
0047 #define RTW_NDP_RX_STANDBY_TIME 0x70
0048 #define RTW_SND_CTRL_REMOVE 0x98
0049 #define RTW_SND_CTRL_SOUNDING   0x9B
0050
0051 enum csi_seg_len {
0052     HAL_CSI_SEG_4K = 0,
0053     HAL_CSI_SEG_8K = 1,
0054     HAL_CSI_SEG_11K = 2,
0055 };
0056
0057 struct cfg_mumimo_para {
0058     u8 sounding_sts[6];
0059     u16 grouping_bitmap;
0060     u8 mu_tx_en;
0061     u32 given_gid_tab[2];
0062     u32 given_user_pos[4];
0063 };
0064
0065 struct mu_bfer_init_para {
0066     u16 paid;
0067     u16 csi_para;
0068     u16 my_aid;
0069     enum csi_seg_len csi_length_sel;
0070     u8 bfer_address[ETH_ALEN];
0071 };
0072
0073 void rtw_bf_disassoc(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
0074              struct ieee80211_bss_conf *bss_conf);
0075 void rtw_bf_assoc(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
0076           struct ieee80211_bss_conf *bss_conf);
0077 void rtw_bf_init_bfer_entry_mu(struct rtw_dev *rtwdev,
0078                    struct mu_bfer_init_para *param);
0079 void rtw_bf_cfg_sounding(struct rtw_dev *rtwdev, struct rtw_vif *vif,
0080              enum rtw_trx_desc_rate rate);
0081 void rtw_bf_cfg_mu_bfee(struct rtw_dev *rtwdev, struct cfg_mumimo_para *param);
0082 void rtw_bf_del_bfer_entry_mu(struct rtw_dev *rtwdev);
0083 void rtw_bf_del_sounding(struct rtw_dev *rtwdev);
0084 void rtw_bf_enable_bfee_su(struct rtw_dev *rtwdev, struct rtw_vif *vif,
0085                struct rtw_bfee *bfee);
0086 void rtw_bf_enable_bfee_mu(struct rtw_dev *rtwdev, struct rtw_vif *vif,
0087                struct rtw_bfee *bfee);
0088 void rtw_bf_remove_bfee_su(struct rtw_dev *rtwdev, struct rtw_bfee *bfee);
0089 void rtw_bf_remove_bfee_mu(struct rtw_dev *rtwdev, struct rtw_bfee *bfee);
0090 void rtw_bf_set_gid_table(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
0091               struct ieee80211_bss_conf *conf);
0092 void rtw_bf_phy_init(struct rtw_dev *rtwdev);
0093 void rtw_bf_cfg_csi_rate(struct rtw_dev *rtwdev, u8 rssi, u8 cur_rate,
0094              u8 fixrate_en, u8 *new_rate);
0095 static inline void rtw_chip_config_bfee(struct rtw_dev *rtwdev, struct rtw_vif *vif,
0096                     struct rtw_bfee *bfee, bool enable)
0097 {
0098     if (rtwdev->chip->ops->config_bfee)
0099         rtwdev->chip->ops->config_bfee(rtwdev, vif, bfee, enable);
0100 }
0101
0102 static inline void rtw_chip_set_gid_table(struct rtw_dev *rtwdev,
0103                       struct ieee80211_vif *vif,
0104                       struct ieee80211_bss_conf *conf)
0105 {
0106     if (rtwdev->chip->ops->set_gid_table)
0107         rtwdev->chip->ops->set_gid_table(rtwdev, vif, conf);
0108 }
0109
0110 static inline void rtw_chip_cfg_csi_rate(struct rtw_dev *rtwdev, u8 rssi, u8 cur_rate,
0111                      u8 fixrate_en, u8 *new_rate)
0112 {
0113     if (rtwdev->chip->ops->cfg_csi_rate)
0114         rtwdev->chip->ops->cfg_csi_rate(rtwdev, rssi, cur_rate,
0115                         fixrate_en, new_rate);
0116 }
0117 #endif