0001
0002
0003
0004 #include "../wifi.h"
0005 #include "reg.h"
0006 #include "def.h"
0007 #include "phy.h"
0008 #include "rf.h"
0009 #include "dm.h"
0010
0011 static bool _rtl8821ae_phy_rf6052_config_parafile(struct ieee80211_hw *hw);
0012
0013 void rtl8821ae_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw, u8 bandwidth)
0014 {
0015 switch (bandwidth) {
0016 case HT_CHANNEL_WIDTH_20:
0017 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, BIT(11)|BIT(10), 3);
0018 rtl_set_rfreg(hw, RF90_PATH_B, RF_CHNLBW, BIT(11)|BIT(10), 3);
0019 break;
0020 case HT_CHANNEL_WIDTH_20_40:
0021 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, BIT(11)|BIT(10), 1);
0022 rtl_set_rfreg(hw, RF90_PATH_B, RF_CHNLBW, BIT(11)|BIT(10), 1);
0023 break;
0024 case HT_CHANNEL_WIDTH_80:
0025 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, BIT(11)|BIT(10), 0);
0026 rtl_set_rfreg(hw, RF90_PATH_B, RF_CHNLBW, BIT(11)|BIT(10), 0);
0027 break;
0028 default:
0029 pr_err("unknown bandwidth: %#X\n", bandwidth);
0030 break;
0031 }
0032 }
0033
0034 void rtl8821ae_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
0035 u8 *ppowerlevel)
0036 {
0037 struct rtl_priv *rtlpriv = rtl_priv(hw);
0038 struct rtl_phy *rtlphy = &rtlpriv->phy;
0039 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
0040 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
0041 u32 tx_agc[2] = {0, 0}, tmpval;
0042 bool turbo_scanoff = false;
0043 u8 idx1, idx2;
0044 u8 *ptr;
0045 u8 direction;
0046 u32 pwrtrac_value;
0047
0048 if (rtlefuse->eeprom_regulatory != 0)
0049 turbo_scanoff = true;
0050
0051 if (mac->act_scanning) {
0052 tx_agc[RF90_PATH_A] = 0x3f3f3f3f;
0053 tx_agc[RF90_PATH_B] = 0x3f3f3f3f;
0054
0055 if (turbo_scanoff) {
0056 for (idx1 = RF90_PATH_A;
0057 idx1 <= RF90_PATH_B;
0058 idx1++) {
0059 tx_agc[idx1] = ppowerlevel[idx1] |
0060 (ppowerlevel[idx1] << 8) |
0061 (ppowerlevel[idx1] << 16) |
0062 (ppowerlevel[idx1] << 24);
0063 }
0064 }
0065 } else {
0066 for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
0067 tx_agc[idx1] = ppowerlevel[idx1] |
0068 (ppowerlevel[idx1] << 8) |
0069 (ppowerlevel[idx1] << 16) |
0070 (ppowerlevel[idx1] << 24);
0071 }
0072
0073 if (rtlefuse->eeprom_regulatory == 0) {
0074 tmpval =
0075 (rtlphy->mcs_txpwrlevel_origoffset[0][6]) +
0076 (rtlphy->mcs_txpwrlevel_origoffset[0][7] <<
0077 8);
0078 tx_agc[RF90_PATH_A] += tmpval;
0079
0080 tmpval = (rtlphy->mcs_txpwrlevel_origoffset[0][14]) +
0081 (rtlphy->mcs_txpwrlevel_origoffset[0][15] <<
0082 24);
0083 tx_agc[RF90_PATH_B] += tmpval;
0084 }
0085 }
0086
0087 for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
0088 ptr = (u8 *)(&tx_agc[idx1]);
0089 for (idx2 = 0; idx2 < 4; idx2++) {
0090 if (*ptr > RF6052_MAX_TX_PWR)
0091 *ptr = RF6052_MAX_TX_PWR;
0092 ptr++;
0093 }
0094 }
0095 rtl8821ae_dm_txpower_track_adjust(hw, 1, &direction, &pwrtrac_value);
0096 if (direction == 1) {
0097 tx_agc[0] += pwrtrac_value;
0098 tx_agc[1] += pwrtrac_value;
0099 } else if (direction == 2) {
0100 tx_agc[0] -= pwrtrac_value;
0101 tx_agc[1] -= pwrtrac_value;
0102 }
0103 tmpval = tx_agc[RF90_PATH_A];
0104 rtl_set_bbreg(hw, RTXAGC_A_CCK11_CCK1, MASKDWORD, tmpval);
0105
0106 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
0107 "CCK PWR 1~11M (rf-A) = 0x%x (reg 0x%x)\n", tmpval,
0108 RTXAGC_A_CCK11_CCK1);
0109
0110 tmpval = tx_agc[RF90_PATH_B];
0111 rtl_set_bbreg(hw, RTXAGC_B_CCK11_CCK1, MASKDWORD, tmpval);
0112
0113 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
0114 "CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n", tmpval,
0115 RTXAGC_B_CCK11_CCK1);
0116 }
0117
0118 static void rtl8821ae_phy_get_power_base(struct ieee80211_hw *hw,
0119 u8 *ppowerlevel_ofdm,
0120 u8 *ppowerlevel_bw20,
0121 u8 *ppowerlevel_bw40, u8 channel,
0122 u32 *ofdmbase, u32 *mcsbase)
0123 {
0124 struct rtl_priv *rtlpriv = rtl_priv(hw);
0125 struct rtl_phy *rtlphy = &rtlpriv->phy;
0126 u32 powerbase0, powerbase1;
0127 u8 i, powerlevel[2];
0128
0129 for (i = 0; i < 2; i++) {
0130 powerbase0 = ppowerlevel_ofdm[i];
0131
0132 powerbase0 = (powerbase0 << 24) | (powerbase0 << 16) |
0133 (powerbase0 << 8) | powerbase0;
0134 *(ofdmbase + i) = powerbase0;
0135 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
0136 " [OFDM power base index rf(%c) = 0x%x]\n",
0137 ((i == 0) ? 'A' : 'B'), *(ofdmbase + i));
0138 }
0139
0140 for (i = 0; i < 2; i++) {
0141 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20)
0142 powerlevel[i] = ppowerlevel_bw20[i];
0143 else
0144 powerlevel[i] = ppowerlevel_bw40[i];
0145
0146 powerbase1 = powerlevel[i];
0147 powerbase1 = (powerbase1 << 24) |
0148 (powerbase1 << 16) | (powerbase1 << 8) | powerbase1;
0149
0150 *(mcsbase + i) = powerbase1;
0151
0152 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
0153 " [MCS power base index rf(%c) = 0x%x]\n",
0154 ((i == 0) ? 'A' : 'B'), *(mcsbase + i));
0155 }
0156 }
0157
0158 static void get_txpower_writeval_by_regulatory(struct ieee80211_hw *hw,
0159 u8 channel, u8 index,
0160 u32 *powerbase0,
0161 u32 *powerbase1,
0162 u32 *p_outwriteval)
0163 {
0164 struct rtl_priv *rtlpriv = rtl_priv(hw);
0165 struct rtl_phy *rtlphy = &rtlpriv->phy;
0166 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
0167 u8 i, chnlgroup = 0, pwr_diff_limit[4], pwr_diff = 0, customer_pwr_diff;
0168 u32 writeval, customer_limit, rf;
0169
0170 for (rf = 0; rf < 2; rf++) {
0171 switch (rtlefuse->eeprom_regulatory) {
0172 case 0:
0173 chnlgroup = 0;
0174
0175 writeval =
0176 rtlphy->mcs_txpwrlevel_origoffset[chnlgroup][index +
0177 (rf ? 8 : 0)]
0178 + ((index < 2) ? powerbase0[rf] : powerbase1[rf]);
0179
0180 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
0181 "RTK better performance, writeval(%c) = 0x%x\n",
0182 ((rf == 0) ? 'A' : 'B'), writeval);
0183 break;
0184 case 1:
0185 if (rtlphy->pwrgroup_cnt == 1) {
0186 chnlgroup = 0;
0187 } else {
0188 if (channel < 3)
0189 chnlgroup = 0;
0190 else if (channel < 6)
0191 chnlgroup = 1;
0192 else if (channel < 9)
0193 chnlgroup = 2;
0194 else if (channel < 12)
0195 chnlgroup = 3;
0196 else if (channel < 14)
0197 chnlgroup = 4;
0198 else if (channel == 14)
0199 chnlgroup = 5;
0200 }
0201
0202 writeval =
0203 rtlphy->mcs_txpwrlevel_origoffset[chnlgroup]
0204 [index + (rf ? 8 : 0)] + ((index < 2) ?
0205 powerbase0[rf] :
0206 powerbase1[rf]);
0207
0208 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
0209 "Realtek regulatory, 20MHz, writeval(%c) = 0x%x\n",
0210 ((rf == 0) ? 'A' : 'B'), writeval);
0211
0212 break;
0213 case 2:
0214 writeval =
0215 ((index < 2) ? powerbase0[rf] : powerbase1[rf]);
0216
0217 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
0218 "Better regulatory, writeval(%c) = 0x%x\n",
0219 ((rf == 0) ? 'A' : 'B'), writeval);
0220 break;
0221 case 3:
0222 chnlgroup = 0;
0223
0224 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) {
0225 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
0226 "customer's limit, 40MHz rf(%c) = 0x%x\n",
0227 ((rf == 0) ? 'A' : 'B'),
0228 rtlefuse->pwrgroup_ht40[rf][channel -
0229 1]);
0230 } else {
0231 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
0232 "customer's limit, 20MHz rf(%c) = 0x%x\n",
0233 ((rf == 0) ? 'A' : 'B'),
0234 rtlefuse->pwrgroup_ht20[rf][channel -
0235 1]);
0236 }
0237
0238 if (index < 2)
0239 pwr_diff = rtlefuse->txpwr_legacyhtdiff[rf][channel-1];
0240 else if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20)
0241 pwr_diff =
0242 rtlefuse->txpwr_ht20diff[rf][channel-1];
0243
0244 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40)
0245 customer_pwr_diff =
0246 rtlefuse->pwrgroup_ht40[rf][channel-1];
0247 else
0248 customer_pwr_diff =
0249 rtlefuse->pwrgroup_ht20[rf][channel-1];
0250
0251 if (pwr_diff > customer_pwr_diff)
0252 pwr_diff = 0;
0253 else
0254 pwr_diff = customer_pwr_diff - pwr_diff;
0255
0256 for (i = 0; i < 4; i++) {
0257 pwr_diff_limit[i] =
0258 (u8)((rtlphy->mcs_txpwrlevel_origoffset
0259 [chnlgroup][index + (rf ? 8 : 0)] &
0260 (0x7f << (i * 8))) >> (i * 8));
0261
0262 if (pwr_diff_limit[i] > pwr_diff)
0263 pwr_diff_limit[i] = pwr_diff;
0264 }
0265
0266 customer_limit = (pwr_diff_limit[3] << 24) |
0267 (pwr_diff_limit[2] << 16) |
0268 (pwr_diff_limit[1] << 8) | (pwr_diff_limit[0]);
0269
0270 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
0271 "Customer's limit rf(%c) = 0x%x\n",
0272 ((rf == 0) ? 'A' : 'B'), customer_limit);
0273
0274 writeval = customer_limit +
0275 ((index < 2) ? powerbase0[rf] : powerbase1[rf]);
0276
0277 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
0278 "Customer, writeval rf(%c)= 0x%x\n",
0279 ((rf == 0) ? 'A' : 'B'), writeval);
0280 break;
0281 default:
0282 chnlgroup = 0;
0283 writeval =
0284 rtlphy->mcs_txpwrlevel_origoffset[chnlgroup]
0285 [index + (rf ? 8 : 0)]
0286 + ((index < 2) ? powerbase0[rf] : powerbase1[rf]);
0287
0288 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
0289 "RTK better performance, writeval rf(%c) = 0x%x\n",
0290 ((rf == 0) ? 'A' : 'B'), writeval);
0291 break;
0292 }
0293
0294 if (rtlpriv->dm.dynamic_txhighpower_lvl == TXHIGHPWRLEVEL_BT1)
0295 writeval = writeval - 0x06060606;
0296 else if (rtlpriv->dm.dynamic_txhighpower_lvl ==
0297 TXHIGHPWRLEVEL_BT2)
0298 writeval = writeval - 0x0c0c0c0c;
0299 *(p_outwriteval + rf) = writeval;
0300 }
0301 }
0302
0303 static void _rtl8821ae_write_ofdm_power_reg(struct ieee80211_hw *hw,
0304 u8 index, u32 *pvalue)
0305 {
0306 struct rtl_priv *rtlpriv = rtl_priv(hw);
0307 u16 regoffset_a[6] = {
0308 RTXAGC_A_OFDM18_OFDM6, RTXAGC_A_OFDM54_OFDM24,
0309 RTXAGC_A_MCS03_MCS00, RTXAGC_A_MCS07_MCS04,
0310 RTXAGC_A_MCS11_MCS08, RTXAGC_A_MCS15_MCS12
0311 };
0312 u16 regoffset_b[6] = {
0313 RTXAGC_B_OFDM18_OFDM6, RTXAGC_B_OFDM54_OFDM24,
0314 RTXAGC_B_MCS03_MCS00, RTXAGC_B_MCS07_MCS04,
0315 RTXAGC_B_MCS11_MCS08, RTXAGC_B_MCS15_MCS12
0316 };
0317 u8 i, rf, pwr_val[4];
0318 u32 writeval;
0319 u16 regoffset;
0320
0321 for (rf = 0; rf < 2; rf++) {
0322 writeval = pvalue[rf];
0323 for (i = 0; i < 4; i++) {
0324 pwr_val[i] = (u8)((writeval & (0x7f <<
0325 (i * 8))) >> (i * 8));
0326
0327 if (pwr_val[i] > RF6052_MAX_TX_PWR)
0328 pwr_val[i] = RF6052_MAX_TX_PWR;
0329 }
0330 writeval = (pwr_val[3] << 24) | (pwr_val[2] << 16) |
0331 (pwr_val[1] << 8) | pwr_val[0];
0332
0333 if (rf == 0)
0334 regoffset = regoffset_a[index];
0335 else
0336 regoffset = regoffset_b[index];
0337 rtl_set_bbreg(hw, regoffset, MASKDWORD, writeval);
0338
0339 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
0340 "Set 0x%x = %08x\n", regoffset, writeval);
0341 }
0342 }
0343
0344 void rtl8821ae_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw,
0345 u8 *ppowerlevel_ofdm,
0346 u8 *ppowerlevel_bw20,
0347 u8 *ppowerlevel_bw40,
0348 u8 channel)
0349 {
0350 u32 writeval[2], powerbase0[2], powerbase1[2];
0351 u8 index;
0352 u8 direction;
0353 u32 pwrtrac_value;
0354
0355 rtl8821ae_phy_get_power_base(hw, ppowerlevel_ofdm,
0356 ppowerlevel_bw20,
0357 ppowerlevel_bw40,
0358 channel,
0359 &powerbase0[0],
0360 &powerbase1[0]);
0361
0362 rtl8821ae_dm_txpower_track_adjust(hw, 1, &direction, &pwrtrac_value);
0363
0364 for (index = 0; index < 6; index++) {
0365 get_txpower_writeval_by_regulatory(hw, channel, index,
0366 &powerbase0[0],
0367 &powerbase1[0],
0368 &writeval[0]);
0369 if (direction == 1) {
0370 writeval[0] += pwrtrac_value;
0371 writeval[1] += pwrtrac_value;
0372 } else if (direction == 2) {
0373 writeval[0] -= pwrtrac_value;
0374 writeval[1] -= pwrtrac_value;
0375 }
0376 _rtl8821ae_write_ofdm_power_reg(hw, index, &writeval[0]);
0377 }
0378 }
0379
0380 bool rtl8821ae_phy_rf6052_config(struct ieee80211_hw *hw)
0381 {
0382 struct rtl_priv *rtlpriv = rtl_priv(hw);
0383 struct rtl_phy *rtlphy = &rtlpriv->phy;
0384
0385 if (rtlphy->rf_type == RF_1T1R)
0386 rtlphy->num_total_rfpath = 1;
0387 else
0388 rtlphy->num_total_rfpath = 2;
0389
0390 return _rtl8821ae_phy_rf6052_config_parafile(hw);
0391 }
0392
0393 static bool _rtl8821ae_phy_rf6052_config_parafile(struct ieee80211_hw *hw)
0394 {
0395 struct rtl_priv *rtlpriv = rtl_priv(hw);
0396 struct rtl_phy *rtlphy = &rtlpriv->phy;
0397 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
0398 u8 rfpath;
0399 bool rtstatus = true;
0400
0401 for (rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++) {
0402 switch (rfpath) {
0403 case RF90_PATH_A: {
0404 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
0405 rtstatus =
0406 rtl8812ae_phy_config_rf_with_headerfile(hw,
0407 (enum radio_path)rfpath);
0408 else
0409 rtstatus =
0410 rtl8821ae_phy_config_rf_with_headerfile(hw,
0411 (enum radio_path)rfpath);
0412 break;
0413 }
0414 case RF90_PATH_B:
0415 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
0416 rtstatus =
0417 rtl8812ae_phy_config_rf_with_headerfile(hw,
0418 (enum radio_path)rfpath);
0419 else
0420 rtstatus =
0421 rtl8821ae_phy_config_rf_with_headerfile(hw,
0422 (enum radio_path)rfpath);
0423 break;
0424 case RF90_PATH_C:
0425 break;
0426 case RF90_PATH_D:
0427 break;
0428 }
0429
0430 if (!rtstatus) {
0431 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
0432 "Radio[%d] Fail!!\n", rfpath);
0433 return false;
0434 }
0435 }
0436
0437
0438 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "\n");
0439 return rtstatus;
0440 }
