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0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Copyright(c) 2009-2010  Realtek Corporation.*/
0003 
0004 #ifndef __RTL8821AE_PWRSEQ_H__
0005 #define __RTL8821AE_PWRSEQ_H__
0006 
0007 #include "../pwrseqcmd.h"
0008 #include "../btcoexist/halbt_precomp.h"
0009 
0010 #define RTL8812_TRANS_CARDEMU_TO_ACT_STEPS  15
0011 #define RTL8812_TRANS_ACT_TO_CARDEMU_STEPS  15
0012 #define RTL8812_TRANS_CARDEMU_TO_SUS_STEPS  15
0013 #define RTL8812_TRANS_SUS_TO_CARDEMU_STEPS  15
0014 #define RTL8812_TRANS_CARDEMU_TO_PDN_STEPS  25
0015 #define RTL8812_TRANS_PDN_TO_CARDEMU_STEPS  15
0016 #define RTL8812_TRANS_ACT_TO_LPS_STEPS      15
0017 #define RTL8812_TRANS_LPS_TO_ACT_STEPS      15
0018 #define RTL8812_TRANS_END_STEPS         1
0019 
0020 /* The following macros have the following format:
0021  * { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value
0022  *   comments },
0023  */
0024 #define RTL8812_TRANS_CARDEMU_TO_ACT                    \
0025     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0026     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0 \
0027     /* disable SW LPS 0x04[10]=0*/},    \
0028     {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0029     PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1 \
0030     /* wait till 0x04[17] = 1    power ready*/},    \
0031     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0032     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0 \
0033     /* disable HWPDN 0x04[15]=0*/}, \
0034     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0035     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0 \
0036     /* disable WL suspend*/},   \
0037     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0038     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
0039     /* polling until return 0*/},   \
0040     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0041     PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},
0042 
0043 #define RTL8812_TRANS_ACT_TO_CARDEMU                                                    \
0044     {0x0c00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0045     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04 \
0046      /* 0xc00[7:0] = 4  turn off 3-wire */},    \
0047     {0x0e00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0048     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04 \
0049      /* 0xe00[7:0] = 4  turn off 3-wire */},    \
0050     {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0051     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
0052      /* 0x2[0] = 0   RESET BB, CLOSE RF */},    \
0053     {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0054     PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US \
0055     /*Delay 1us*/}, \
0056     {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
0057     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
0058       /* Whole BB is reset*/},          \
0059     {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0060     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x2A \
0061      /* 0x07[7:0] = 0x28 sps pwm mode 0x2a for BT coex*/},  \
0062     {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
0063     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x02, 0 \
0064     /*0x8[1] = 0 ANA clk =500k */}, \
0065     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0066     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
0067      /*0x04[9] = 1 turn off MAC by HW state machine*/}, \
0068     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0069     PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0 \
0070      /*wait till 0x04[9] = 0 polling until return 0 to disable*/},
0071 
0072 #define RTL8812_TRANS_CARDEMU_TO_SUS                    \
0073     {0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
0074     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xc0}, \
0075     {0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
0076     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xE0}, \
0077     {0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0078     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x07 \
0079     /* gpio11 input mode, gpio10~8 output mode */}, \
0080     {0x0045, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0081     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00 \
0082     /* gpio 0~7 output same value as input ?? */},  \
0083     {0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0084     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xff \
0085     /* gpio0~7 output mode */}, \
0086     {0x0047, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0087     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \
0088     /* 0x47[7:0] = 00 gpio mode */},    \
0089     {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
0090     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \
0091     /* suspend option all off */},  \
0092     {0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0093     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, BIT7 \
0094     /*0x14[7] = 1 turn on ZCD */},  \
0095     {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0096     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, BIT0 \
0097     /* 0x15[0] =1 trun on ZCD */},  \
0098     {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0099     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, BIT4 \
0100     /*0x23[4] = 1 hpon LDO sleep mode */},  \
0101     {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
0102     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x02, 0 \
0103     /*0x8[1] = 0 ANA clk =500k */}, \
0104     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0105     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3 \
0106     /*0x04[11] = 2b'11 enable WL suspend for PCIe*/},
0107 
0108 #define RTL8812_TRANS_SUS_TO_CARDEMU                    \
0109     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0110     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0 \
0111     /*0x04[11] = 2b'01enable WL suspend*/},   \
0112     {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0113     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, 0 \
0114     /*0x23[4] = 0 hpon LDO sleep mode leave */},    \
0115     {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0116     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, 0 \
0117     /* 0x15[0] =0 trun off ZCD */}, \
0118     {0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0119     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, 0 \
0120     /*0x14[7] = 0 turn off ZCD */}, \
0121     {0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0122     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00 \
0123     /* gpio0~7 input mode */},  \
0124     {0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0125     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00 \
0126     /* gpio11 input mode, gpio10~8 input mode */},
0127 
0128 #define RTL8812_TRANS_CARDEMU_TO_CARDDIS                \
0129     {0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0130     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0 \
0131     /*0x03[2] = 0, reset 8051*/},   \
0132     {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0133     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x05 \
0134     /*0x80=05h if reload fw, fill the default value of host_CPU handshake field*/}, \
0135     {0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
0136     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xcc}, \
0137     {0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
0138     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xEC}, \
0139     {0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0140     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x07 \
0141     /* gpio11 input mode, gpio10~8 output mode */}, \
0142     {0x0045, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0143     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00 \
0144     /* gpio 0~7 output same value as input ?? */},  \
0145     {0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0146     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xff \
0147     /* gpio0~7 output mode */}, \
0148     {0x0047, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0149     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \
0150     /* 0x47[7:0] = 00 gpio mode */},    \
0151     {0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0152     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, BIT7 \
0153     /*0x14[7] = 1 turn on ZCD */},  \
0154     {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0155     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, BIT0 \
0156     /* 0x15[0] =1 trun on ZCD */},  \
0157     {0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0158     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, 0 \
0159     /*0x12[0] = 0 force PFM mode */},   \
0160     {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0161     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, BIT4 \
0162     /*0x23[4] = 1 hpon LDO sleep mode */},  \
0163     {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
0164     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x02, 0 \
0165     /*0x8[1] = 0 ANA clk =500k */}, \
0166     {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
0167     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20 \
0168      /*0x07=0x20 , SOP option to disable BG/MB*/},  \
0169     {0x001f, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
0170     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
0171      /*0x01f[1]=0 , disable RFC_0  control  REG_RF_CTRL_8812 */},   \
0172     {0x0076, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
0173     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
0174      /*0x076[1]=0 , disable RFC_1  control REG_OPT_CTRL_8812 +2 */},    \
0175     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0176     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3 \
0177      /*0x04[11] = 2b'01 enable WL suspend*/},
0178 
0179 #define RTL8812_TRANS_CARDDIS_TO_CARDEMU                \
0180     {0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0181     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
0182     /*0x12[0] = 1 force PWM mode */},   \
0183     {0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0184     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, 0 \
0185     /*0x14[7] = 0 turn off ZCD */}, \
0186     {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0187     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, 0 \
0188     /* 0x15[0] =0 trun off ZCD */}, \
0189     {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0190     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, 0 \
0191     /*0x23[4] = 0 hpon LDO leave sleep mode */},    \
0192     {0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0193     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00 \
0194     /* gpio0~7 input mode */},  \
0195     {0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0196     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00 \
0197     /* gpio11 input mode, gpio10~8 input mode */}, \
0198     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
0199     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0 \
0200      /*0x04[10] = 0, enable SW LPS PCIE only*/},    \
0201     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0202     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0 \
0203      /*0x04[11] = 2b'01enable WL suspend*/},    \
0204     {0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0205     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2 \
0206      /*0x03[2] = 1, enable 8051*/}, \
0207     {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
0208     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \
0209     /*PCIe DMA start*/},
0210 
0211 #define RTL8812_TRANS_CARDEMU_TO_PDN        \
0212     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0213     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7 \
0214     /* 0x04[15] = 1*/},
0215 
0216 #define RTL8812_TRANS_PDN_TO_CARDEMU            \
0217     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0218     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0 \
0219     /* 0x04[15] = 0*/},
0220 
0221 #define RTL8812_TRANS_ACT_TO_LPS        \
0222     {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
0223     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF \
0224     /*PCIe DMA stop*/}, \
0225     {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0226     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x7F \
0227     /*Tx Pause*/},      \
0228     {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0229     PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
0230     /*Should be zero if no packet is transmitting*/},   \
0231     {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0232     PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
0233     /*Should be zero if no packet is transmitting*/},   \
0234     {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0235     PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
0236     /*Should be zero if no packet is transmitting*/},   \
0237     {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0238     PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
0239     /*Should be zero if no packet is transmitting*/},   \
0240     {0x0c00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0241     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04 \
0242      /* 0xc00[7:0] = 4  turn off 3-wire */},    \
0243     {0x0e00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0244     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04 \
0245      /* 0xe00[7:0] = 4  turn off 3-wire */},    \
0246     {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0247     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
0248     /*CCK and OFDM are disabled,and clock are gated,and RF closed*/},   \
0249     {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0250     PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US \
0251     /*Delay 1us*/}, \
0252     {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
0253     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
0254       /* Whole BB is reset*/},          \
0255     {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0256     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03 \
0257     /*Reset MAC TRX*/},         \
0258     {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0259     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
0260     /*check if removed later*/},        \
0261     {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0262     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5 \
0263     /*Respond TxOK to scheduler*/},
0264 
0265 #define RTL8812_TRANS_LPS_TO_ACT                    \
0266     {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
0267     PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84 \
0268      /*SDIO RPWM*/},    \
0269     {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
0270     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84 \
0271      /*USB RPWM*/}, \
0272     {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
0273     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84 \
0274      /*PCIe RPWM*/},    \
0275     {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0276     PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS \
0277      /*Delay*/},    \
0278     {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0279     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \
0280      /*.    0x08[4] = 0      switch TSF to 40M*/},  \
0281     {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0282     PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0 \
0283      /*Polling 0x109[7]=0  TSF in 40M*/},           \
0284     {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0285     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6|BIT7, 0 \
0286      /*.    0x29[7:6] = 2b'00    enable BB clock*/},    \
0287     {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0288     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
0289      /*.    0x101[1] = 1*/},                    \
0290     {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0291     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF \
0292      /*.    0x100[7:0] = 0xFF    enable WMAC TRX*/},    \
0293     {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0294     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0 \
0295      /*.    0x02[1:0] = 2b'11    enable BB macro*/},    \
0296     {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0297     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \
0298      /*.    0x522 = 0*/},
0299 
0300 #define RTL8812_TRANS_END                   \
0301     {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
0302     0, PWR_CMD_END, 0, 0},
0303 
0304 extern struct wlan_pwr_cfg  rtl8812_power_on_flow
0305         [RTL8812_TRANS_CARDEMU_TO_ACT_STEPS +
0306          RTL8812_TRANS_END_STEPS];
0307 extern struct wlan_pwr_cfg  rtl8812_radio_off_flow
0308         [RTL8812_TRANS_ACT_TO_CARDEMU_STEPS +
0309          RTL8812_TRANS_END_STEPS];
0310 extern struct wlan_pwr_cfg  rtl8812_card_disable_flow
0311         [RTL8812_TRANS_ACT_TO_CARDEMU_STEPS +
0312          RTL8812_TRANS_CARDEMU_TO_PDN_STEPS +
0313          RTL8812_TRANS_END_STEPS];
0314 extern struct wlan_pwr_cfg  rtl8812_card_enable_flow
0315         [RTL8812_TRANS_ACT_TO_CARDEMU_STEPS +
0316          RTL8812_TRANS_CARDEMU_TO_PDN_STEPS +
0317          RTL8812_TRANS_END_STEPS];
0318 extern struct wlan_pwr_cfg  rtl8812_suspend_flow
0319         [RTL8812_TRANS_ACT_TO_CARDEMU_STEPS +
0320          RTL8812_TRANS_CARDEMU_TO_SUS_STEPS +
0321          RTL8812_TRANS_END_STEPS];
0322 extern struct wlan_pwr_cfg  rtl8812_resume_flow
0323         [RTL8812_TRANS_ACT_TO_CARDEMU_STEPS +
0324          RTL8812_TRANS_CARDEMU_TO_SUS_STEPS +
0325          RTL8812_TRANS_END_STEPS];
0326 extern struct wlan_pwr_cfg  rtl8812_hwpdn_flow
0327         [RTL8812_TRANS_ACT_TO_CARDEMU_STEPS +
0328          RTL8812_TRANS_CARDEMU_TO_PDN_STEPS +
0329          RTL8812_TRANS_END_STEPS];
0330 extern struct wlan_pwr_cfg  rtl8812_enter_lps_flow
0331         [RTL8812_TRANS_ACT_TO_LPS_STEPS +
0332          RTL8812_TRANS_END_STEPS];
0333 extern struct wlan_pwr_cfg  rtl8812_leave_lps_flow
0334         [RTL8812_TRANS_LPS_TO_ACT_STEPS +
0335          RTL8812_TRANS_END_STEPS];
0336 
0337 /* Check document WM-20130516-JackieLau-RTL8821A_Power_Architecture-R10.vsd
0338  *  There are 6 HW Power States:
0339  *  0: POFF--Power Off
0340  *  1: PDN--Power Down
0341  *  2: CARDEMU--Card Emulation
0342  *  3: ACT--Active Mode
0343  *  4: LPS--Low Power State
0344  *  5: SUS--Suspend
0345  *
0346  *  The transision from different states are defined below
0347  *  TRANS_CARDEMU_TO_ACT
0348  *  TRANS_ACT_TO_CARDEMU
0349  *  TRANS_CARDEMU_TO_SUS
0350  *  TRANS_SUS_TO_CARDEMU
0351  *  TRANS_CARDEMU_TO_PDN
0352  *  TRANS_ACT_TO_LPS
0353  *  TRANS_LPS_TO_ACT
0354  *
0355  *  TRANS_END
0356  */
0357 #define RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS 25
0358 #define RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS 15
0359 #define RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS 15
0360 #define RTL8821A_TRANS_SUS_TO_CARDEMU_STEPS 15
0361 #define RTL8821A_TRANS_CARDDIS_TO_CARDEMU_STEPS 15
0362 #define RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS 15
0363 #define RTL8821A_TRANS_PDN_TO_CARDEMU_STEPS 15
0364 #define RTL8821A_TRANS_ACT_TO_LPS_STEPS     15
0365 #define RTL8821A_TRANS_LPS_TO_ACT_STEPS     15
0366 #define RTL8821A_TRANS_END_STEPS        1
0367 
0368 #define RTL8821A_TRANS_CARDEMU_TO_ACT                   \
0369     {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,          \
0370      PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,\
0371     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
0372      /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/},   \
0373     {0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,      \
0374      PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,\
0375     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \
0376      /*0x67[0] = 0 to disable BT_GPS_SEL pins*/},   \
0377     {0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,          \
0378      PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,\
0379     PWR_BASEADDR_MAC, PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS \
0380     /*Delay 1ms*/},   \
0381     {0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,          \
0382      PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,\
0383     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0 \
0384      /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/},   \
0385     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0386     PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3|BIT2), 0 \
0387     /* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[12:11]=0*/}, \
0388     {0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
0389     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , BIT0 \
0390     /* Disable USB suspend */}, \
0391     {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0392     PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1 \
0393     /* wait till 0x04[17] = 1    power ready*/},    \
0394     {0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
0395     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , 0 \
0396     /* Enable USB suspend */},  \
0397     {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0398     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
0399     /* release WLON reset  0x04[16]=1*/},   \
0400     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0401     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0 \
0402     /* disable HWPDN 0x04[15]=0*/}, \
0403     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0404     PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3), 0 \
0405     /* disable WL suspend*/},   \
0406     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0407     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
0408     /* polling until return 0*/},   \
0409     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0410     PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0 \
0411     /**/},  \
0412     {0x004F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0413     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
0414     /*0x4C[24] = 0x4F[0] = 1, switch DPDT_SEL_P output from WL BB */},\
0415     {0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0416     PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT5|BIT4), (BIT5|BIT4) \
0417     /*0x66[13] = 0x67[5] = 1, switch for PAPE_G/PAPE_A  \
0418      from WL BB ; 0x66[12] = 0x67[4] = 1, switch LNAON from WL BB */},\
0419     {0x0025, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0420     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0 \
0421     /*anapar_mac<118> , 0x25[6]=0 by wlan single function*/},\
0422     {0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0423     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
0424     /*Enable falling edge triggering interrupt*/},\
0425     {0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0426     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
0427     /*Enable GPIO9 interrupt mode*/},\
0428     {0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0429     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
0430     /*Enable GPIO9 input mode*/},\
0431     {0x0058, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0432     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
0433     /*Enable HSISR GPIO[C:0] interrupt*/},\
0434     {0x005A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0435     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
0436     /*Enable HSISR GPIO9 interrupt*/},\
0437     {0x007A, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0438     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3A \
0439     /*0x7A = 0x3A start BT*/},\
0440     {0x002E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0441     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF , 0x82  \
0442     /* 0x2C[23:12]=0x820 ; XTAL trim */}, \
0443     {0x0010, PWR_CUT_A_MSK , PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0444     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 , BIT6  \
0445     /* 0x10[6]=1  */},
0446 
0447 #define RTL8821A_TRANS_ACT_TO_CARDEMU                   \
0448     {0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0449     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \
0450     /*0x1F[7:0] = 0 turn off RF*/}, \
0451     {0x004F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0452     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
0453     /*0x4C[24] = 0x4F[0] = 0, switch DPDT_SEL_P output from     \
0454      register 0x65[2] */},\
0455     {0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0456     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
0457     /*Enable rising edge triggering interrupt*/}, \
0458     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0459     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
0460      /*0x04[9] = 1 turn off MAC by HW state machine*/}, \
0461     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0462     PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0 \
0463      /*wait till 0x04[9] = 0 polling until return 0 to disable*/},  \
0464     {0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,          \
0465      PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,\
0466     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5 \
0467      /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/},   \
0468     {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,      \
0469      PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,\
0470     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
0471      /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/},
0472 
0473 #define RTL8821A_TRANS_CARDEMU_TO_SUS                   \
0474     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
0475     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3) \
0476      /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/},   \
0477     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,      \
0478      PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,\
0479     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3 \
0480      /*0x04[12:11] = 2b'01 enable WL suspend*/},    \
0481     {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
0482     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4 \
0483      /*0x23[4] = 1b'1 12H LDO enter sleep mode*/},   \
0484     {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
0485     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20 \
0486      /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/},   \
0487     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
0488     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4 \
0489      /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/},   \
0490     {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
0491     PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0 \
0492      /*Set SDIO suspend local register*/},  \
0493     {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
0494     PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0 \
0495      /*wait power state to suspend*/},
0496 
0497 #define RTL8821A_TRANS_SUS_TO_CARDEMU                   \
0498     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0499     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0 \
0500      /*clear suspend enable and power down enable*/},   \
0501     {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
0502     PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0 \
0503      /*Set SDIO suspend local register*/},  \
0504     {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
0505     PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1 \
0506      /*wait power state to suspend*/},\
0507     {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
0508     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \
0509      /*0x23[4] = 1b'0 12H LDO enter normal mode*/},   \
0510     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0511     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0 \
0512      /*0x04[12:11] = 2b'00 disable WL suspend*/},
0513 
0514 #define RTL8821A_TRANS_CARDEMU_TO_CARDDIS               \
0515     {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
0516     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20 \
0517      /*0x07=0x20 , SOP option to disable BG/MB*/},  \
0518     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,      \
0519      PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,\
0520     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3 \
0521      /*0x04[12:11] = 2b'01 enable WL suspend*/},    \
0522     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
0523     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2 \
0524      /*0x04[10] = 1, enable SW LPS*/},  \
0525         {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
0526     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1 \
0527      /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/},   \
0528     {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
0529     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4 \
0530      /*0x23[4] = 1b'1 12H LDO enter sleep mode*/},   \
0531     {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
0532     PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0 \
0533      /*Set SDIO suspend local register*/},  \
0534     {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
0535     PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0 \
0536      /*wait power state to suspend*/},
0537 
0538 #define RTL8821A_TRANS_CARDDIS_TO_CARDEMU               \
0539     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0540     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0 \
0541      /*clear suspend enable and power down enable*/},   \
0542     {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
0543     PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0 \
0544      /*Set SDIO suspend local register*/},  \
0545     {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
0546     PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1 \
0547      /*wait power state to suspend*/},\
0548     {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
0549     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
0550      /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/},   \
0551     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0552     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0 \
0553      /*0x04[12:11] = 2b'00 disable WL suspend*/},\
0554     {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
0555     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \
0556      /*0x23[4] = 1b'0 12H LDO enter normal mode*/},   \
0557     {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
0558     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \
0559     /*PCIe DMA start*/},
0560 
0561 #define RTL8821A_TRANS_CARDEMU_TO_PDN                   \
0562     {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
0563     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4 \
0564      /*0x23[4] = 1b'1 12H LDO enter sleep mode*/},   \
0565     {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,      \
0566      PWR_INTF_SDIO_MSK|PWR_INTF_USB_MSK,\
0567     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20 \
0568      /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/},   \
0569     {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0570     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
0571     /* 0x04[16] = 0*/},\
0572     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0573     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7 \
0574     /* 0x04[15] = 1*/},
0575 
0576 #define RTL8821A_TRANS_PDN_TO_CARDEMU               \
0577     {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0578     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0 \
0579     /* 0x04[15] = 0*/},
0580 
0581 #define RTL8821A_TRANS_ACT_TO_LPS                   \
0582     {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
0583     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF \
0584     /*PCIe DMA stop*/}, \
0585     {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0586     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF \
0587     /*Tx Pause*/},  \
0588     {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0589     PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
0590     /*Should be zero if no packet is transmitting*/},   \
0591     {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0592     PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
0593     /*Should be zero if no packet is transmitting*/},   \
0594     {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0595     PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
0596     /*Should be zero if no packet is transmitting*/},   \
0597     {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0598     PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
0599     /*Should be zero if no packet is transmitting*/},   \
0600     {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0601     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
0602     /*CCK and OFDM are disabled,and clock are gated*/}, \
0603     {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0604     PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US \
0605     /*Delay 1us*/}, \
0606     {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0607     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
0608     /*Whole BB is reset*/}, \
0609     {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0610     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03 \
0611     /*Reset MAC TRX*/}, \
0612     {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0613     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
0614     /*check if removed later*/},    \
0615     {0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
0616     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00 \
0617     /*When driver enter Sus/ Disable, enable LOP for BT*/}, \
0618     {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0619     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5 \
0620     /*Respond TxOK to scheduler*/},
0621 
0622 #define RTL8821A_TRANS_LPS_TO_ACT                   \
0623     {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
0624     PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84 \
0625      /*SDIO RPWM*/},\
0626     {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
0627     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84 \
0628      /*USB RPWM*/},\
0629     {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
0630     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84 \
0631      /*PCIe RPWM*/},\
0632     {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0633     PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS \
0634      /*Delay*/},\
0635     {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0636     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \
0637      /*.    0x08[4] = 0      switch TSF to 40M*/},\
0638     {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0639     PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0 \
0640      /*Polling 0x109[7]=0  TSF in 40M*/},\
0641     {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0642     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6|BIT7, 0 \
0643      /*.    0x29[7:6] = 2b'00    enable BB clock*/},\
0644     {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0645     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
0646      /*.    0x101[1] = 1*/},\
0647     {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0648     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF \
0649      /*.    0x100[7:0] = 0xFF    enable WMAC TRX*/},\
0650     {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0651     PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0 \
0652      /*.    0x02[1:0] = 2b'11    enable BB macro*/},\
0653     {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0654     PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \
0655      /*.    0x522 = 0*/},
0656 
0657 #define RTL8821A_TRANS_END                  \
0658     {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0659     0, PWR_CMD_END, 0, 0},
0660 
0661 extern struct wlan_pwr_cfg rtl8821A_power_on_flow
0662         [RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS +
0663          RTL8821A_TRANS_END_STEPS];
0664 extern struct wlan_pwr_cfg rtl8821A_radio_off_flow
0665         [RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS +
0666          RTL8821A_TRANS_END_STEPS];
0667 extern struct wlan_pwr_cfg rtl8821A_card_disable_flow
0668         [RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS +
0669          RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS +
0670          RTL8821A_TRANS_END_STEPS];
0671 extern struct wlan_pwr_cfg rtl8821A_card_enable_flow
0672         [RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS +
0673          RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS +
0674          RTL8821A_TRANS_END_STEPS];
0675 extern struct wlan_pwr_cfg rtl8821A_suspend_flow
0676         [RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS +
0677          RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS +
0678          RTL8821A_TRANS_END_STEPS];
0679 extern struct wlan_pwr_cfg rtl8821A_resume_flow
0680         [RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS +
0681          RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS +
0682          RTL8821A_TRANS_END_STEPS];
0683 extern struct wlan_pwr_cfg rtl8821A_hwpdn_flow
0684         [RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS +
0685          RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS +
0686          RTL8821A_TRANS_END_STEPS];
0687 extern struct wlan_pwr_cfg rtl8821A_enter_lps_flow
0688         [RTL8821A_TRANS_ACT_TO_LPS_STEPS +
0689          RTL8821A_TRANS_END_STEPS];
0690 extern struct wlan_pwr_cfg rtl8821A_leave_lps_flow
0691         [RTL8821A_TRANS_LPS_TO_ACT_STEPS +
0692          RTL8821A_TRANS_END_STEPS];
0693 
0694 /*RTL8812 Power Configuration CMDs for PCIe interface*/
0695 #define RTL8812_NIC_PWR_ON_FLOW         rtl8812_power_on_flow
0696 #define RTL8812_NIC_RF_OFF_FLOW         rtl8812_radio_off_flow
0697 #define RTL8812_NIC_DISABLE_FLOW        rtl8812_card_disable_flow
0698 #define RTL8812_NIC_ENABLE_FLOW         rtl8812_card_enable_flow
0699 #define RTL8812_NIC_SUSPEND_FLOW        rtl8812_suspend_flow
0700 #define RTL8812_NIC_RESUME_FLOW         rtl8812_resume_flow
0701 #define RTL8812_NIC_PDN_FLOW            rtl8812_hwpdn_flow
0702 #define RTL8812_NIC_LPS_ENTER_FLOW      rtl8812_enter_lps_flow
0703 #define RTL8812_NIC_LPS_LEAVE_FLOW      rtl8812_leave_lps_flow
0704 
0705 /* RTL8821 Power Configuration CMDs for PCIe interface */
0706 #define RTL8821A_NIC_PWR_ON_FLOW        rtl8821A_power_on_flow
0707 #define RTL8821A_NIC_RF_OFF_FLOW        rtl8821A_radio_off_flow
0708 #define RTL8821A_NIC_DISABLE_FLOW       rtl8821A_card_disable_flow
0709 #define RTL8821A_NIC_ENABLE_FLOW        rtl8821A_card_enable_flow
0710 #define RTL8821A_NIC_SUSPEND_FLOW       rtl8821A_suspend_flow
0711 #define RTL8821A_NIC_RESUME_FLOW        rtl8821A_resume_flow
0712 #define RTL8821A_NIC_PDN_FLOW           rtl8821A_hwpdn_flow
0713 #define RTL8821A_NIC_LPS_ENTER_FLOW     rtl8821A_enter_lps_flow
0714 #define RTL8821A_NIC_LPS_LEAVE_FLOW     rtl8821A_leave_lps_flow
0715 
0716 #endif
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