rtlwifi/rtl8821ae/def.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Copyright(c) 2009-2010  Realtek Corporation.*/
0003
0004 #ifndef __RTL8821AE_DEF_H__
0005 #define __RTL8821AE_DEF_H__
0006
0007 /*--------------------------Define -------------------------------------------*/
0008 #define USE_SPECIFIC_FW_TO_SUPPORT_WOWLAN   1
0009
0010 /* BIT 7 HT Rate*/
0011 /*TxHT = 0*/
0012 #define MGN_1M              0x02
0013 #define MGN_2M              0x04
0014 #define MGN_5_5M            0x0b
0015 #define MGN_11M             0x16
0016
0017 #define MGN_6M              0x0c
0018 #define MGN_9M              0x12
0019 #define MGN_12M             0x18
0020 #define MGN_18M             0x24
0021 #define MGN_24M             0x30
0022 #define MGN_36M             0x48
0023 #define MGN_48M             0x60
0024 #define MGN_54M             0x6c
0025
0026 /* TxHT = 1 */
0027 #define MGN_MCS0            0x80
0028 #define MGN_MCS1            0x81
0029 #define MGN_MCS2            0x82
0030 #define MGN_MCS3            0x83
0031 #define MGN_MCS4            0x84
0032 #define MGN_MCS5            0x85
0033 #define MGN_MCS6            0x86
0034 #define MGN_MCS7            0x87
0035 #define MGN_MCS8            0x88
0036 #define MGN_MCS9            0x89
0037 #define MGN_MCS10           0x8a
0038 #define MGN_MCS11           0x8b
0039 #define MGN_MCS12           0x8c
0040 #define MGN_MCS13           0x8d
0041 #define MGN_MCS14           0x8e
0042 #define MGN_MCS15           0x8f
0043 /* VHT rate */
0044 #define MGN_VHT1SS_MCS0     0x90
0045 #define MGN_VHT1SS_MCS1     0x91
0046 #define MGN_VHT1SS_MCS2     0x92
0047 #define MGN_VHT1SS_MCS3     0x93
0048 #define MGN_VHT1SS_MCS4     0x94
0049 #define MGN_VHT1SS_MCS5     0x95
0050 #define MGN_VHT1SS_MCS6     0x96
0051 #define MGN_VHT1SS_MCS7     0x97
0052 #define MGN_VHT1SS_MCS8     0x98
0053 #define MGN_VHT1SS_MCS9     0x99
0054 #define MGN_VHT2SS_MCS0     0x9a
0055 #define MGN_VHT2SS_MCS1     0x9b
0056 #define MGN_VHT2SS_MCS2     0x9c
0057 #define MGN_VHT2SS_MCS3     0x9d
0058 #define MGN_VHT2SS_MCS4     0x9e
0059 #define MGN_VHT2SS_MCS5     0x9f
0060 #define MGN_VHT2SS_MCS6     0xa0
0061 #define MGN_VHT2SS_MCS7     0xa1
0062 #define MGN_VHT2SS_MCS8     0xa2
0063 #define MGN_VHT2SS_MCS9     0xa3
0064
0065 #define MGN_VHT3SS_MCS0     0xa4
0066 #define MGN_VHT3SS_MCS1     0xa5
0067 #define MGN_VHT3SS_MCS2     0xa6
0068 #define MGN_VHT3SS_MCS3     0xa7
0069 #define MGN_VHT3SS_MCS4     0xa8
0070 #define MGN_VHT3SS_MCS5     0xa9
0071 #define MGN_VHT3SS_MCS6     0xaa
0072 #define MGN_VHT3SS_MCS7     0xab
0073 #define MGN_VHT3SS_MCS8     0xac
0074 #define MGN_VHT3SS_MCS9     0xad
0075
0076 #define MGN_MCS0_SG         0xc0
0077 #define MGN_MCS1_SG         0xc1
0078 #define MGN_MCS2_SG         0xc2
0079 #define MGN_MCS3_SG         0xc3
0080 #define MGN_MCS4_SG         0xc4
0081 #define MGN_MCS5_SG         0xc5
0082 #define MGN_MCS6_SG         0xc6
0083 #define MGN_MCS7_SG         0xc7
0084 #define MGN_MCS8_SG         0xc8
0085 #define MGN_MCS9_SG         0xc9
0086 #define MGN_MCS10_SG        0xca
0087 #define MGN_MCS11_SG        0xcb
0088 #define MGN_MCS12_SG        0xcc
0089 #define MGN_MCS13_SG        0xcd
0090 #define MGN_MCS14_SG        0xce
0091 #define MGN_MCS15_SG        0xcf
0092
0093 #define MGN_UNKNOWN         0xff
0094
0095 /* 30 ms */
0096 #define WIFI_NAV_UPPER_US               30000
0097 #define HAL_92C_NAV_UPPER_UNIT          128
0098
0099 #define MAX_RX_DMA_BUFFER_SIZE              0x3E80
0100
0101 #define HAL_PRIME_CHNL_OFFSET_DONT_CARE     0
0102 #define HAL_PRIME_CHNL_OFFSET_LOWER         1
0103 #define HAL_PRIME_CHNL_OFFSET_UPPER         2
0104
0105 #define RX_MPDU_QUEUE                       0
0106 #define RX_CMD_QUEUE                        1
0107
0108 #define MAX_RX_DMA_BUFFER_SIZE_8812 0x3E80
0109
0110 #define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3)
0111
0112 #define CHIP_8812               BIT(2)
0113 #define CHIP_8821               (BIT(0)|BIT(2))
0114
0115 #define CHIP_8821A              (BIT(0)|BIT(2))
0116 #define NORMAL_CHIP             BIT(3)
0117 #define RF_TYPE_1T1R                (~(BIT(4)|BIT(5)|BIT(6)))
0118 #define RF_TYPE_1T2R                BIT(4)
0119 #define RF_TYPE_2T2R                BIT(5)
0120 #define CHIP_VENDOR_UMC             BIT(7)
0121 #define B_CUT_VERSION               BIT(12)
0122 #define C_CUT_VERSION               BIT(13)
0123 #define D_CUT_VERSION               ((BIT(12)|BIT(13)))
0124 #define E_CUT_VERSION               BIT(14)
0125 #define RF_RL_ID            (BIT(31)|BIT(30)|BIT(29)|BIT(28))
0126
0127 enum version_8821ae {
0128     VERSION_TEST_CHIP_1T1R_8812 = 0x0004,
0129     VERSION_TEST_CHIP_2T2R_8812 = 0x0024,
0130     VERSION_NORMAL_TSMC_CHIP_1T1R_8812 = 0x100c,
0131     VERSION_NORMAL_TSMC_CHIP_2T2R_8812 = 0x102c,
0132     VERSION_NORMAL_TSMC_CHIP_1T1R_8812_C_CUT = 0x200c,
0133     VERSION_NORMAL_TSMC_CHIP_2T2R_8812_C_CUT = 0x202c,
0134     VERSION_TEST_CHIP_8821 = 0x0005,
0135     VERSION_NORMAL_TSMC_CHIP_8821 = 0x000d,
0136     VERSION_NORMAL_TSMC_CHIP_8821_B_CUT = 0x100d,
0137     VERSION_UNKNOWN = 0xFF,
0138 };
0139
0140 enum vht_data_sc {
0141     VHT_DATA_SC_DONOT_CARE = 0,
0142     VHT_DATA_SC_20_UPPER_OF_80MHZ = 1,
0143     VHT_DATA_SC_20_LOWER_OF_80MHZ = 2,
0144     VHT_DATA_SC_20_UPPERST_OF_80MHZ = 3,
0145     VHT_DATA_SC_20_LOWEST_OF_80MHZ = 4,
0146     VHT_DATA_SC_20_RECV1 = 5,
0147     VHT_DATA_SC_20_RECV2 = 6,
0148     VHT_DATA_SC_20_RECV3 = 7,
0149     VHT_DATA_SC_20_RECV4 = 8,
0150     VHT_DATA_SC_40_UPPER_OF_80MHZ = 9,
0151     VHT_DATA_SC_40_LOWER_OF_80MHZ = 10,
0152 };
0153
0154 /* MASK */
0155 #define IC_TYPE_MASK            (BIT(0)|BIT(1)|BIT(2))
0156 #define CHIP_TYPE_MASK          BIT(3)
0157 #define RF_TYPE_MASK            (BIT(4)|BIT(5)|BIT(6))
0158 #define MANUFACTUER_MASK        BIT(7)
0159 #define ROM_VERSION_MASK        (BIT(11)|BIT(10)|BIT(9)|BIT(8))
0160 #define CUT_VERSION_MASK        (BIT(15)|BIT(14)|BIT(13)|BIT(12))
0161
0162 /* Get element */
0163 #define GET_CVID_IC_TYPE(version)   ((version) & IC_TYPE_MASK)
0164 #define GET_CVID_CHIP_TYPE(version) ((version) & CHIP_TYPE_MASK)
0165 #define GET_CVID_RF_TYPE(version)   ((version) & RF_TYPE_MASK)
0166 #define GET_CVID_MANUFACTUER(version)   ((version) & MANUFACTUER_MASK)
0167 #define GET_CVID_ROM_VERSION(version)   ((version) & ROM_VERSION_MASK)
0168 #define GET_CVID_CUT_VERSION(version)   ((version) & CUT_VERSION_MASK)
0169
0170 #define IS_1T1R(version)    ((GET_CVID_RF_TYPE(version)) ? false : true)
0171 #define IS_1T2R(version)    ((GET_CVID_RF_TYPE(version) == RF_TYPE_1T2R)\
0172                             ? true : false)
0173 #define IS_2T2R(version)    ((GET_CVID_RF_TYPE(version) == RF_TYPE_2T2R)\
0174                             ? true : false)
0175
0176 #define IS_8812_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8812) ? \
0177                                 true : false)
0178 #define IS_8821_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8821) ? \
0179                                 true : false)
0180
0181 #define IS_VENDOR_8812A_TEST_CHIP(version)  ((IS_8812_SERIES(version)) ? \
0182                     ((IS_NORMAL_CHIP(version)) ? \
0183                         false : true) : false)
0184 #define IS_VENDOR_8812A_MP_CHIP(version)    ((IS_8812_SERIES(version)) ? \
0185                     ((IS_NORMAL_CHIP(version)) ? \
0186                         true : false) : false)
0187 #define IS_VENDOR_8812A_C_CUT(version)      ((IS_8812_SERIES(version)) ? \
0188                     ((GET_CVID_CUT_VERSION(version) == \
0189                     C_CUT_VERSION) ? \
0190                     true : false) : false)
0191
0192 #define IS_VENDOR_8821A_TEST_CHIP(version)  ((IS_8821_SERIES(version)) ? \
0193                     ((IS_NORMAL_CHIP(version)) ? \
0194                     false : true) : false)
0195 #define IS_VENDOR_8821A_MP_CHIP(version)    ((IS_8821_SERIES(version)) ? \
0196                     ((IS_NORMAL_CHIP(version)) ? \
0197                         true : false) : false)
0198 #define IS_VENDOR_8821A_B_CUT(version)      ((IS_8821_SERIES(version)) ? \
0199                     ((GET_CVID_CUT_VERSION(version) == \
0200                     B_CUT_VERSION) ? \
0201                     true : false) : false)
0202 enum board_type {
0203     ODM_BOARD_DEFAULT = 0,    /* The DEFAULT case. */
0204     ODM_BOARD_MINICARD = BIT(0), /* 0 = non-mini card, 1 = mini card. */
0205     ODM_BOARD_SLIM = BIT(1), /* 0 = non-slim card, 1 = slim card */
0206     ODM_BOARD_BT = BIT(2), /* 0 = without BT card, 1 = with BT */
0207     ODM_BOARD_EXT_PA = BIT(3), /* 1 = existing 2G ext-PA */
0208     ODM_BOARD_EXT_LNA = BIT(4), /* 1 = existing 2G ext-LNA */
0209     ODM_BOARD_EXT_TRSW = BIT(5), /* 1 = existing ext-TRSW */
0210     ODM_BOARD_EXT_PA_5G = BIT(6), /* 1 = existing 5G ext-PA */
0211     ODM_BOARD_EXT_LNA_5G = BIT(7), /* 1 = existing 5G ext-LNA */
0212 };
0213
0214 enum rf_optype {
0215     RF_OP_BY_SW_3WIRE = 0,
0216     RF_OP_BY_FW,
0217     RF_OP_MAX
0218 };
0219
0220 enum rf_power_state {
0221     RF_ON,
0222     RF_OFF,
0223     RF_SLEEP,
0224     RF_SHUT_DOWN,
0225 };
0226
0227 enum power_save_mode {
0228     POWER_SAVE_MODE_ACTIVE,
0229     POWER_SAVE_MODE_SAVE,
0230 };
0231
0232 enum power_polocy_config {
0233     POWERCFG_MAX_POWER_SAVINGS,
0234     POWERCFG_GLOBAL_POWER_SAVINGS,
0235     POWERCFG_LOCAL_POWER_SAVINGS,
0236     POWERCFG_LENOVO,
0237 };
0238
0239 enum interface_select_pci {
0240     INTF_SEL1_MINICARD = 0,
0241     INTF_SEL0_PCIE = 1,
0242     INTF_SEL2_RSV = 2,
0243     INTF_SEL3_RSV = 3,
0244 };
0245
0246 enum rtl_desc_qsel {
0247     QSLT_BK = 0x2,
0248     QSLT_BE = 0x0,
0249     QSLT_VI = 0x5,
0250     QSLT_VO = 0x7,
0251     QSLT_BEACON = 0x10,
0252     QSLT_HIGH = 0x11,
0253     QSLT_MGNT = 0x12,
0254     QSLT_CMD = 0x13,
0255 };
0256
0257 struct phy_sts_cck_8821ae_t {
0258     u8 adc_pwdb_X[4];
0259     u8 sq_rpt;
0260     u8 cck_agc_rpt;
0261 };
0262
0263 struct h2c_cmd_8821ae {
0264     u8 element_id;
0265     u32 cmd_len;
0266     u8 *p_cmdbuffer;
0267 };
0268
0269 #endif